For Systems (epo) Patents (Class 714/E11.202)
  • Patent number: 11388131
    Abstract: A contact center is operated by reference to response time statistics and social media analytics. A method for identifying a user population's sensitivity to response time delay comprises monitoring social network messaging activity to identify user messages associated with the user population. In some embodiments, the activity relates to at least one of an entity or a product or service associated with the entity. The user population may be selected on the basis of a socio-demographic characteristic or on the basis of observable social networking behavior and/or sentiment over a prior selection phase. The method further includes selecting a loyalty transition boundary identified by detecting a difference in aggregate sentiment between a first group of users receiving a response delayed by a first time period and a second group of users receiving a response delayed by a second time period greater than the first time period.
    Type: Grant
    Filed: December 30, 2014
    Date of Patent: July 12, 2022
    Assignee: Avaya Inc.
    Inventors: Reinhard Klemm, Valentine Matula
  • Publication number: 20140068336
    Abstract: Testing a test component is disclosed. A real-time input communication that has been forked from an input communication intended for a deployed component is received at the test component. At least a portion of the received real-time input communication is processed. A result of the processing is used to at least in part determine a test result of the test component.
    Type: Application
    Filed: September 4, 2012
    Publication date: March 6, 2014
    Inventor: Barak Reuven Naveh
  • Publication number: 20130151908
    Abstract: A failure detection method including: detecting, by a virtual computer, occurrence of the failure in a virtual function of an I/O device; acquiring, a virtual device name corresponding to the virtual function in which the failure has occurred; referring, to device information retaining a virtual device name of the I/O device assigned to the virtual computer and VF specific information on the I/O device, thereby acquiring the VF specific information based on the acquired virtual device name; transmitting, the acquired VF specific information to the host; referring, by the host, to I/O correspondence information retaining a slot number of a slot in which the I/O device is mounted, and VF specific information, thereby acquiring the slot number corresponding to the VF specific information received from the virtual computer; and identifying, the acquired slot number as the slot number of the I/O device on which the failure has occurred.
    Type: Application
    Filed: September 27, 2012
    Publication date: June 13, 2013
    Inventors: Miho IWANAGA, Masahiko YAMAUCHI, Daisuke NAKAYAMA
  • Publication number: 20130055031
    Abstract: A synchronization controller has a synchronization determiner for determining a synchronization deviation in a CPU, an abnormality sign related information obtainer for obtaining abnormality sign related information on the basis of transaction monitoring information, and an abnormality determiner, when there is a synchronization deviation, for determining the presence/absence of a sign of abnormality in the CPU on the basis of the abnormality sign related information.
    Type: Application
    Filed: August 21, 2012
    Publication date: February 28, 2013
    Applicant: NEC Corporation
    Inventor: Takanobu SAITO
  • Patent number: 8347268
    Abstract: Performance tracking of computing systems can be provided by monitoring, determining performance states, and displaying health information. Capacity planning recommendations can be provided by monitoring performance of a software application, determining a plurality of performance state transitions of the software application, and, based on the transitions, making capacity planning recommendations. Performance state transitions can be selected from a set of transitions between four possible quadrant states. Performance of a software application can be categorized into one of the four possible quadrant states from. Capacity planning recommendations can be provided by a capacity planning framework. The framework can comprise a performance monitoring module for monitoring performance of software applications, a quadrant tracking module for determining performance state transitions, and a capacity planning module for making capacity planning recommendations based on the transitions.
    Type: Grant
    Filed: October 12, 2007
    Date of Patent: January 1, 2013
    Assignee: Infosys Limited
    Inventors: Gaurav Caprihan, Nikhil Venugopal, Pratik Kumar
  • Patent number: 8332615
    Abstract: A management system detects a peak time period during which accesses are concentrated on a logical page included in a logical volume, and reallocates this logical page to an appropriate physical page. A management server detects an access variation of each logical volume, and selects a volume with a large access variation as a target volume. The management server measures the access status of each logical page in the target volume, and allocates a logical page to a more appropriate physical page.
    Type: Grant
    Filed: July 19, 2010
    Date of Patent: December 11, 2012
    Assignee: Hitachi, Ltd.
    Inventors: Yoshiki Fukui, Nobuo Beniyama
  • Publication number: 20120304020
    Abstract: A performance monitoring unit (PMU) and method for monitoring performance of events occurring in a multiprocessor system. The multiprocessor system comprises a plurality of processor devices units, each processor device for generating signals representing occurrences of events in the processor device, and, a single shared counter resource for performance monitoring. The performance monitor unit is shared by all processor cores in the multiprocessor system. The PMU is further programmed to monitor event signals issued from non-processor devices.
    Type: Application
    Filed: May 31, 2012
    Publication date: November 29, 2012
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: George Chiu, Alan G. Gara, Valentina Salapura
  • Publication number: 20120297252
    Abstract: A computer implemented method, computer program product and system for monitoring a plurality of hardware or software system resources for identifying hidden trends in the behavior of the system resources, includes: collecting metrics of at least one system resource indicative of the behavior of at least one system resource; for each of the at least one system resource, determining a spectrum representative of a time-based signal of the collected metrics; performing a wavelet transform on each of the at least one spectrum; and analyzing the result of the wavelet transform to identify possible linear trends in the behavior of the at least one system resource.
    Type: Application
    Filed: June 24, 2012
    Publication date: November 22, 2012
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Stefano Borghetti, Gianluca Della Corte, Leonida Gianfagna, Antonio Perrone, Antonio M. Sgro
  • Publication number: 20120266029
    Abstract: An arrangement for processing trace data information is provided, the arrangement including, a chip including one or more memory circuits configured to store trace data information relating to a series of instructions, and a trace data information port configured to provide off-chip access to the trace data information; and a direct memory access controller circuit configured to control the transportation of trace data information from the one or more memory circuits to the trace data information port.
    Type: Application
    Filed: April 18, 2011
    Publication date: October 18, 2012
    Applicant: INFINEON TECHNOLOGIES AG
    Inventors: Albrecht Mayer, Harry Siebert
  • Publication number: 20120254669
    Abstract: Embodiments are directed to predicting the health of a computer node using health report data and to proactively handling failures in database services. In an embodiment, a computer system monitors various health indicators for multiple nodes in a database cluster. The computer system accesses stored health indicators that provide a health history for the database cluster nodes. The computer system then generates a health status based on the monitored health factors and the health history. The generated health status indicates the likelihood that the node will be healthy within a specified future time period. The computer system then leverages the generated health status to handle current or predicted failures. The computer system also presents the generated health status to a user or other entity.
    Type: Application
    Filed: April 4, 2011
    Publication date: October 4, 2012
    Applicant: MICROSOFT CORPORATION
    Inventors: Hao Xia, Todd F. Pfleiger, Mark C. Benvenuto, Ajay Kalhan
  • Publication number: 20120246517
    Abstract: A first virtual I/O server (VIOS) provides a cluster aware (CA) operating system (OS) executing on a processor resource of the first VIOS to register the first VIOS within a VIOS cluster. The first VIOS comprises a first field/failure data capture (FFDC) module that executes within the first VIOS and performs the functions of: receiving from an event listener a signal indicating that an FFFDC event/condition has been detected by the first VIOS; and automatically transmitting FFDC data to the shared storage repository for storage of the FFDC data within the shared storage repository. The FFDC module further performs the functions of: transmitting to one or more second VIOSes within the VIOS cluster, one or more messages to inform the one or more second VIOSes of an occurrence of the FFDC event/condition that was detected by the first VIOS.
    Type: Application
    Filed: March 24, 2011
    Publication date: September 27, 2012
    Applicant: IBM CORPORATION
    Inventors: Carl Duane Bender, Veena Ganti, Maria deLourdes Garza, Neal Richard Marion, James A. Pafumi, Jacob Jason Rosales, Morgan Jeffrey Rosas, Vasu Vallabhaneni
  • Publication number: 20120166888
    Abstract: The present embodiments disclose a method and an associated computer program product for determining the quality of an information technology (IT) system including a plurality of hardware units and software modules. A total score value for the IT system is calculated from different score values ascertained independently of one another. The different score values are measures for deviations of the quality of the hardware units or the software modules from first predefinable target values. The total score value is a measure of a deviation of the quality of the IT system from a second predefinable target value.
    Type: Application
    Filed: June 23, 2011
    Publication date: June 28, 2012
    Inventor: Burkhard Kiesel
  • Publication number: 20120144244
    Abstract: A method that determines the system impact of single event upset (SEU) and a single event upset (SEU) wrapper that controls a SEU controller is disclosed. The method injects faults into a component (e.g. FPGA, ASIC) of an operational system that is carrying live traffic and monitors the system's response to the faults to determine the impact of SEU on the system. The SEU wrapper sends the SEU controller a pattern scheme that includes information indicating when, where, how often, and/or how long to inject bursts of one or more faults into memory of the component of the system. A burst of faults contains faults that are consecutively injected into the array of memory blocks. After each fault in a burst is injected, one or more errors in one or more memory elements are detected and/or corrected. Information regarding the detection and/or the correction of an error is updated using registers that store counters. After injecting a burst of faults, the SEU controller waits for a predetermined amount of time.
    Type: Application
    Filed: December 7, 2010
    Publication date: June 7, 2012
    Inventors: Yie-Fong Dan, Shi-Jie Wen, Raymond Ng
  • Publication number: 20120047403
    Abstract: Disclosed is a data processing system capable of detecting a sign of abnormality in such a manner as to increase the degree of safety and availability of the system. The data processing system uses a prediction circuit that detects a sign of abnormality in accordance with a cumulative history of significant events encountered during the processing of CPUs. The prediction circuit retains latest notification timing information about periodic notification from the CPUs in association with the CPUs, acquires elapsed time from the latest notification timing at predetermined intervals, and successively retains history information corresponding to changes in the elapsed time from a target value in association with the CPUs. When the retained history information reaches a predetermined threshold value, the prediction circuit concludes that there is a sign of abnormality.
    Type: Application
    Filed: August 4, 2011
    Publication date: February 23, 2012
    Inventor: Yasuhiko SAITO
  • Publication number: 20120042212
    Abstract: A program is executed on a processor to produce execution events. The execution events are traced using a first trace mode during a first portion of the program execution, wherein a portion of trace information for the execution events is omitted from a trace report while tracing in the first trace mode. The mode of tracing is dynamically changed to a second trace mode in response to an event trigger, such that all execution events that occur during the change of mode are captured. Execution events are traced during a second portion of the program execution using the second trace mode, wherein additional trace information for the execution events is included in the trace report while tracing in the second trace mode. The trace mode may be dynamically switched between the two trace modes during execution of the program.
    Type: Application
    Filed: August 18, 2010
    Publication date: February 16, 2012
    Inventor: Gilbert Laurenti
  • Publication number: 20110314340
    Abstract: A data processing apparatus is provided with trace circuitry for generating a plurality of trace streams including an instruction trace stream 10 and a data trace stream 12. The instruction elements within the instruction trace stream and the data elements within the data trace stream are marked with key values KV such that a match may be made between data elements and corresponding instruction elements. When predetermined conditions are met, synchronisation markers 66 are inserted in both the instruction trace stream 10 and the data trace stream 12 in order to permit a precise correlation to be made between the instruction elements and the data elements when the data is subsequently analysed.
    Type: Application
    Filed: May 13, 2011
    Publication date: December 22, 2011
    Applicant: ARM Limited
    Inventors: Paul Anthony Gilkerson, John Michael Horley
  • Publication number: 20110289359
    Abstract: A method begins by a processing module determining access performance to copies of dispersed storage encoded data, wherein the copies of the dispersed storage encoded data are stored in a set of a plurality of dispersed storage networks (DSNs). The method continues with the processing module modifying the set of the plurality of DSNs based on the access performance and the desired access performance level to produce a modified set of the plurality of DSNs when the access performance is not at a desired access performance level. The method continues with the processing module, for a new DSN of the modified set of the plurality of DSNs, determining error coding dispersal storage parameters based on local data retrieval accesses allocated to the new DSN and facilitating the new DSN storing another copy of the dispersed storage encoded data.
    Type: Application
    Filed: May 11, 2011
    Publication date: November 24, 2011
    Applicant: CLEVERSAFE, INC.
    Inventors: Jason K. Resch, Gary W. Grube, Timothy W. Markison
  • Publication number: 20110289363
    Abstract: The present application discloses a preventative, diagnostic maintenance system designed for gaming systems. Sensor and software monitor, accumulate, store and share information for efficient maintenance of the gaming systems. Diagnostic and prognostic tests are run and results prioritized wherein minor and intermittent problems that indicate potential future problems are stored. When a technician visit is prescribed, the system will present via a GUI a visualization of the status of gamed devices, and, forearm the technician with the high and low priority information regarding the high priority problems along with the low priority problems for all the game devices at the same site. The technician will be able to bring the specific tools, programs and parts to service the high and the low priority problems of all the game devices.
    Type: Application
    Filed: August 5, 2011
    Publication date: November 24, 2011
    Inventor: Bharat Kumar Gadher
  • Publication number: 20110283152
    Abstract: Systems and methods for cache optimization are provided. The method comprises tracing objects instantiated during execution of a program code under test according to type of access by one or more threads running in parallel, wherein said tracing provides information about order in which different instances of one or more objects are accessed by said one or more threads and whether the type of access is a read operation or a write operation; and utilizing tracing information to build a temporal relationship graph (TRG) for the accessed objects, wherein the objects are represented by nodes in the TRG and at least two types of edges for connecting the nodes are defined.
    Type: Application
    Filed: May 16, 2010
    Publication date: November 17, 2011
    Applicant: International Business Machines Corporation
    Inventors: Daniel Citron, Moshe Klausner, Aharon Kupershtok, Yousef Shajrawi, Yaakov Yaari
  • Publication number: 20110202801
    Abstract: An integrated circuit 2 is provided with a data source 6 in the form of a processor executing program instructions connected via a bus interconnect 16 to a trace output device 8. The trace output device 8 is memory mapped. Different memory addresses that are mapped to the trace output device 8 are associated with different priority levels. Trace data written to at least one memory address has a first level of priority in which it is either accepted or the transfer is stalled until the data can be processed by the trace output device 8. Another level of priority associated with a different memory address is such that the data is always accepted but is discarded if the trace output device 8 does not have the ability to process, e.g. store that data at that time.
    Type: Application
    Filed: February 14, 2011
    Publication date: August 18, 2011
    Applicant: ARM LIMITED
    Inventors: John Michael Horley, Michael John Williams, Katherine Elizabeth Kneebone, Alastair David Reid
  • Publication number: 20110138231
    Abstract: A system and method provides for generating high compression program flow trace data by generating first program flow trace data whenever a conditional branch instruction of a program is executed by a CPU, generating second program flow trace data whenever an indirect branch instruction of a subset of indirect branch instructions is executed by the CPU, and generating third program flow trace data whenever a stack for storing instruction addresses of the program is manipulated, the manipulation occurring after a CALL instruction to a function or subroutine of the program is executed by the CPU and before a RET instruction is executed by the CPU. The subset of indirect branch instructions excludes RET indirect branch instructions of any function or subroutine for which the stack is not manipulated after a CALL instruction to the functions or subroutines is executed by the CPU and before the RET instruction is executed by the CPU.
    Type: Application
    Filed: December 3, 2009
    Publication date: June 9, 2011
    Applicant: Infineon Technologies AG
    Inventor: Albrecht Mayer
  • Publication number: 20110078506
    Abstract: A method executes computerized instructions stored within a computer storage medium within an integrated and packaged semiconductor device using a centralized programming interface within the packaged semiconductor device to perform in-system preventive and recovery actions, configure and issue stimulus to chips, components and sensors within the semiconductor device. The method monitors chip, components and sensors within the packaged semiconductor device, using the centralized programming interface, to measure characteristics of the packaged semiconductor device in response to the stimulus. The structure including chips, components and sensors produce outputs representing the characteristics.
    Type: Application
    Filed: September 29, 2009
    Publication date: March 31, 2011
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Carole D. Graas, Pascal A. Nsame
  • Publication number: 20110055637
    Abstract: In an embodiment, a data processing system comprises a repository configured to store a plurality of event message definitions for error messages, syslog messages, or other notification messages that may be emitted by one or more managed network elements; event annotation logic coupled to the data repository and configured to receive and store one or more annotations to each of the event message definitions, wherein each of the annotations specifies event context information to be collected in the managed network elements when an associated event message occurs; event forensics definitions generator logic coupled to the event annotation logic and configured to generate an event forensics definitions file capable of interpretation by one or more managed network elements and comprising event type identifiers and context information identifiers for context information to be collected, and configured to cause distributing the event forensics definitions file to the one or more managed network elements.
    Type: Application
    Filed: August 31, 2009
    Publication date: March 3, 2011
    Inventors: L. Alexander Clemm, Carlos M. Pignataro, Rodney S. Dunn, Steve Chen-Lin Chang, Shyyunn Sheran Lin
  • Publication number: 20110016360
    Abstract: A computer implemented method, computer program product and system for monitoring a plurality of hardware or software system resources for identifying hidden trends in the behavior of the system resources, includes: collecting metrics of at least one system resource indicative of the behavior of at least one system resource; for each of the at least one system resource, determining a spectrum representative of a time-based signal of the collected metrics; performing a wavelet transform on each of the at least one spectrum; and analyzing the result of the wavelet transform to identify possible linear trends in the behavior of the at least one system resource.
    Type: Application
    Filed: April 6, 2010
    Publication date: January 20, 2011
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Stefano Borghetti, Gianluca Della Corte, Leonida Gianfagna, Antonio Perrone, Antonio M. Sgro
  • Publication number: 20100281309
    Abstract: In a method for monitoring power consumption by a system within an integrated circuit, one or more software programs are executed on the system on a chip (SOC). While the program executes, power control settings of a plurality of functional units within the SOC may be adjusted in response to executing the one or more software programs, whereby power consumption within the SOC varies over time. The power control settings may be changed in response to explicit directions from the executing software, or may occur autonomously in response to load monitoring control modules within the SOC. A sequence of power states is reported for the plurality of functional units within the SOC. Each of the sequence of power states may include clock frequencies from multiple clock domains, voltage levels for multiple voltage domains, initiator activity, target activity, memory module power enablement, or power enablement of each of the plurality of functional units.
    Type: Application
    Filed: June 4, 2009
    Publication date: November 4, 2010
    Inventors: Gilbert Laurenti, Dario Cardini
  • Publication number: 20100223507
    Abstract: The invention provides an information processing apparatus including: a plurality of abnormality detection sections provided in each of a plurality of detection target portions, that detect an abnormality caused by high temperature at a predetermined first frequency; an indication detecting section that detects an indication that the abnormality will occur; and a controller that controls to set the detection frequency of the plurality of abnormality detection sections to a second frequency which is higher than the first frequency, when the number of times that the indication is detected within a predetermined period is more than a predetermined number of times.
    Type: Application
    Filed: September 16, 2009
    Publication date: September 2, 2010
    Applicant: FUJI XEROX CO., LTD.
    Inventors: Kazuhiko NARUSHIMA, Shigekazu Yamagishi, Makoto Hashimoto, Ken Ikeda, Masafumi Ono, Hinki Ryu, Kenji Kuroishi
  • Publication number: 20100205483
    Abstract: An operation management apparatus monitors the performance information of a system executing services and extracts correlation variants of the performance information, thus allowing the management to detect and localize performance-degrading faults of the system. It is determined whether or not the range of correlation collapse ascribed to the performance information falls within the normal range of correlation collapse measured in the normal operation of the system. A history is retained with regard to the range of correlation collapse ascribed to the performance information which does not fall within the normal range of correlation collapse. It is determined whether or not the history accumulating the predetermined number of ranges of correlation collapse approximates to the fault range of correlation collapse measured in the faulty operation of the system, thus discriminating a fault model on the basis of the performance information.
    Type: Application
    Filed: February 10, 2010
    Publication date: August 12, 2010
    Inventor: Ken Ishiou
  • Publication number: 20100180156
    Abstract: Various embodiments for intelligent dump suppression in a computing environment following an error are provided. A plurality of historical information is considered in view of a current alert level to generate an output decision. The current alert level is one of an available plurality of alert levels configurable by a user. The current alert level is selectable by the user for a predetermined data collection restrictiveness. Data capture is performed according to the output decision.
    Type: Application
    Filed: January 15, 2009
    Publication date: July 15, 2010
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Herman Aranguren, David Bruce LeGendre, David Charles Reed, Max Douglas Smith
  • Publication number: 20100125758
    Abstract: A distributed system checker may check a distributed system against events to detect bugs in the distributed system. The events may include machines crashes, network partitions, and packet losses, for example. The distributed system checker may check a distributed system that can have multiple threads and multiple processes running on multiple nodes. To obtain control over a distributed system, a distributed system checker may insert an interposition layer between a process and the operating system on each node.
    Type: Application
    Filed: November 17, 2008
    Publication date: May 20, 2010
    Applicant: Microsoft Corporation
    Inventors: Junfeng Yang, Lintao Zhang, Lidong Zhou, Zhenyu Guo, Xuezheng Liu, Jian Tang, Mao Yang
  • Publication number: 20100100775
    Abstract: Methods, systems, and computer-readable media for filtering redundant fault events from an event stream generated by devices on a network based on a statistical correlation between fault events are provided. Event history data is collected from the fault events generated by devices on the network over a period of time. Statistical correlations are computed between each distinct pair of fault events in the event history data. Based on the statistical correlations, a list of redundant fault events and associated significant events is identified. The list of redundant events and associated significant events is utilized to filter the redundant fault events from the event stream generated by the devices on the network.
    Type: Application
    Filed: October 21, 2008
    Publication date: April 22, 2010
    Inventors: Lev Slutsman, Moshiur Rahman
  • Publication number: 20100088552
    Abstract: Provided are a method and system for integrated monitoring of fault and performance information in an integrated management system environment including an integrated management server that interworks with a managed server having a built-in agent for the sake of integrated management of a variety of management information.
    Type: Application
    Filed: April 11, 2007
    Publication date: April 8, 2010
    Applicant: SAMSUNG SDS CO., LTD.
    Inventors: Byung Seop Kim, Chi Hoon Lee, Cheol Ju Kang, Jae Hee Park, Hyeon Min Han, Seong Hyon Nam
  • Publication number: 20100082804
    Abstract: Routing network traffic on a computer network is described. In one embodiment, a method is presented which includes transmitting instructions to a client, the instructions executable by the client to request content from two or more content servers, measure two or more network performance characteristics associated with the two or more different content servers, and issue a report to an administrative server. The report may include a first network performance characteristic and a second network performance characteristic. The method may further include selecting a target content server from one of two or more content servers based on comparison of the two or more network performance characteristics; and transmitting routing instructions to an intermediate routing system, the routing instructions executable by the intermediate routing system to direct subsequent content requests transmitted by the client to the target content server.
    Type: Application
    Filed: October 1, 2008
    Publication date: April 1, 2010
    Applicant: MICROSOFT CORPORATION
    Inventors: Parveen Patel, Albert Gordon Greenberg, David Maltz
  • Publication number: 20100064173
    Abstract: This document relates to apparatus and methods to store and retrieve trace information in on-chip system memory of microcontrollers. A microcontroller comprises a microprocessor and a memory device accessible through a data bus and an address bus coupled to the microprocessor. The microcontroller includes on-chip debug logic coupled to the microprocessor. Trace data can be retrieved from system memory using a debug port of the debug logic. A system in accordance with the present invention will lower the cost of implementation of trace features in microcontrollers, and strongly reduce the cost of supporting such features in debug tools.
    Type: Application
    Filed: November 11, 2009
    Publication date: March 11, 2010
    Applicant: Atmel Corporation
    Inventors: Frode Milch Pedersen, Are Arseth
  • Publication number: 20090287965
    Abstract: A verification target register to be verified is specified from a configuration of a verification target circuit, and patterns requiring verification are extracted as a coverage standard with regard to the specified verification target register. When the patterns are extracted, a DIRW matrix is prepared to indicate possibly occurring state transitions among four states Declare, Initialize, Read, and Write in the register included in the verification target circuit, and used to decide two coverage standards, a matrix coverage standard and an implementation coverage standard.
    Type: Application
    Filed: January 23, 2009
    Publication date: November 19, 2009
    Applicant: FUJITSU LIMITED
    Inventors: Ryosuke Oishi, Akio Matsuda, Koichiro Takayama, Tsuneo Nakata
  • Publication number: 20090125756
    Abstract: A data processing apparatus is provided, comprising monitored circuitry for performing activities, trace circuitry for producing a stream of trace elements representative of at least some of these activities, and detection circuitry for detecting the occurrence of a predetermined subset of the activities for which the trace circuitry is producing trace elements. When an activity in that predetermined subset of activities is detected a timing indication is added to the stream of trace elements. Hence, the valuable trace bandwidth- may be preserved, by limiting the trace elements for which a timing indication is added into the trace stream to a predetermined subset of the activities for which trace elements are generated, and the valuable global or relative timing accuracy of those activities represented in the trace stream is retained, without flooding the trace stream with timing indications.
    Type: Application
    Filed: November 14, 2007
    Publication date: May 14, 2009
    Applicant: ARM LIMITED
    Inventors: Andrew Brookfield Swaine, Richard Roy Grisenthwaite, Michael John Williams
  • Publication number: 20090094487
    Abstract: A method to combine trace data for multiple systems within an embedded system is provided. This method involves coupling a set of trace sources within the embedded system to a trace system. A subset of trace source(s) may then be selected from the set of trace sources. The subset of trace sources may be formatted to produce a packetized trace stream. The packetized trace stream may then be provided to external interface circuitry. External circuitry coupled to the trace system allows for analysis of the packetized trace streams regarding internal operations within the embedded system. An arbitrator may determine which trace source(s) from the set of trace sources are selected to be within the subset of trace sources. The arbitrator may use several criteria to make this determination.
    Type: Application
    Filed: October 3, 2007
    Publication date: April 9, 2009
    Inventor: LANCE FLAKE
  • Publication number: 20080059844
    Abstract: A fiber channel switch (hereinafter, FC-SW) connected to a plurality of communications devices is provided with a buffer for temporarily storing data received from servers via a first communications port, a trace data storage memory for storing trace data, and a microprocessor (MP) for sending data accumulated in the buffer to a storage control system. The MP stores the information about the data about the received data into the trace data storage memory as trace data, issues a write command to the storage control system if it is detected that trace data sending condition is satisfied, and reads out the trace data stored in the trace data storage memory and sends it to the storage control system.
    Type: Application
    Filed: October 25, 2007
    Publication date: March 6, 2008
    Inventor: Kenichi MIYAMOTO