Abstract: A system for providing a computer configured to read an immutable value for a variable; read the value of the variable at a specific timestamp, thereby providing an ability to create looping constructs; set a current or next value of a loop variable as a function of previous or current loop variables; read a set of all values that a variable will assume; push or scatter the values into collections; reduce the collections into a single value; display graphical node representations to indicate computed values next to corresponding source code lines in an editor, and edge representations to indicate dependencies between values; visualize data output by a given node; permit the user to reorder source code lines by dragging nodes; cache or memoize computed values, and reuse cached or memoized values to implement reactive programming, minimizing recomputation in response to changes to program or data.

Abstract: Trace circuitry for monitoring a behaviour of at least one processor and for generating items of trace data indicative of processing activities of said at least one processor executing a stream of instructions is disclosed. The stream of instructions comprises different types of instructions, each type specifying a different operation, at least one type of instruction comprising a multiple transfer instruction specifying a plurality of data transfers.

Abstract: The present invention aims at providing an integrated circuit device which can perform on-chip tracing by using a system installed with the same chip as that of a mass produced product, and comprises: at least one or more kinds of first chips equipped with a circuit for performing data processing; and a second chip equipped with a circuit for tracing the operation of said circuit installed a the first chip, wherein a signal between said first chip and said second chip is transmitted by signal transmission utilizing electromagnetic induction.

Abstract: A processing system includes a processing circuit having one or more buses, a memory interface unit to control access by the processing circuit to a memory, and a metrics module. The metrics module includes one or more metrics registers and a metrics controller to monitor one or more operations selected from memory interface unit operations and bus operations, and to store metrics information corresponding to the monitored operations in the metrics registers. The monitored operations can include memory access operations, arbitration operations, bus operations, and the like. The metrics information can be analyzed to provide a basis for improving performance of a program that is executed on the processing system.

Abstract: Embodiments of the invention concern a method for transmitting digital messages through a microprocessor monitoring circuit of specific type and integrated to a microprocessor, each message including an identifier and consisting of several groups of successive and juxtaposed bits divided into segments. The method consists in successively transmitting segments associated with a first group corresponding to the identifier and comprising a fixed number of bits; with second groups, at least one of the second group comprising a fixed number of bits depending on the type of monitoring circuit, the number of other second groups being independent of the type of monitoring circuit; with a third group comprising a number of bits greater than one; and with fourth groups comprising each a number of bits greater than one, the number of fourth groups depending on the identifier and on the type of monitoring circuit.

Abstract: A debugging system includes a CPU that is a debugging target and a debugging circuit. The CPU has an output part configured to independently output stack access information of a stack access and data access information of a data access excluding the stack access, as data access information of the CPU that is monitored by the debugging circuit. The debugging circuit has a trace part configured to independently generate and output trace information of the stack access from the stack access information that is output from the CPU and trace information of the data access excluding the stack access from the data access information that is output from the CPU.