Abstract: Placing workloads in a multi-array system comprising a plurality of storage arrays, including: determining, for each of a plurality of storage arrays, a current system activity level trend of the storage array; receiving a performance profile of a workload to be executed on one of the storage arrays; generating, for each of the plurality of storage arrays in dependence upon the current system activity level trend of the storage array and the performance profile of the workload, a projected system activity level trend for the storage array; identifying, in dependence upon the projected system activity level trend for each of the plurality of storage arrays, an optimal storage array for receiving the workload; and placing the workload on the optimal storage array.

Abstract: A storage device includes a storage device communicably connected to a host; a nonvolatile memory configured to store calibration data of the host; and a calibration circuit configured to receive a descriptor from the host including the setting information and update the calibration data with the received setting information.

Abstract: A system, apparatus, and method for writing trace data to storage. Trace data is captured from one or more processors, and then the trace data is written to a trace buffer. The trace data includes program counters of instructions executed by the processors and other debug data. A direct memory access (DMA) controller in a non-real-time block of the system reads trace data from the trace buffer and then writes the trace data to memory via a non-real-time port of a memory controller.

Abstract: A random permutation code is described which provides efficient repair of data nodes. A specific implementation of a permutation code is also described, followed by description of a MISER-Permutation code. Finally, an optimal repair strategy is explained that involves an iterative process of downloading the most effective available parity data, updating costs of remaining parity data, and repeating until the data is recovered.

Abstract: A novel RDMA connection failover technique that minimizes disruption to upper subsystem modules (executed on a computer node), which create requests for data transfer. A new failover virtual layer performs failover of an RDMA connection in error so that the upper subsystem that created a request does not have knowledge of an error (which is recoverable in software and hardware), or of a failure on the RDMA connection due to the error. Since the upper subsystem does not have knowledge of a failure on the RDMA connection or of a performed failover of the RDMA connection, the upper subsystem continues providing requests to the failover virtual layer without interruption, thereby minimizing downtime of the data transfer activity.

Abstract: The embodiments described herein generally relate to methods and systems for using an extended patching procedure for correction or repair of logical data portions, pages, or sectors of a computer data storage device. The extended patching procedure targets for repair not only the page(s) appearing to be defective or unusable based on a failed read operation for a data transfer request, but also additional pages. Determining the additional pages to include for automatic patching is based on: statistical distribution analyses to include pages within the physical or logical vicinity of the original page, information about the underlying storage device technology or Input/Output (I/O) subsystem, and/or historical data about error conditions for areas related to the original page. Preemptively patching pages based on extended page lists improves system performance by reducing the total number of costly repair processes and by avoiding situations involving correction actions that fail to resolve.

Abstract: Some embodiments of the invention relate to an embedded processing system. The system includes a memory unit to store a plurality of operating instructions and a processing unit coupled to the memory unit. The processing unit can execute logical operations corresponding to respective operating instructions. An input/output (I/O) interface receives a first time-varying waveform and provides an I/O signal that is based on the first time-varying waveform. A comparison unit coupled to the processing unit and adapted to selectively assert an error signal based on whether the I/O signal has a predetermined relationship with a reference signal, wherein the predetermined relationship holds true during normal operation but fails to hold true when an unexpected event occurs and causes an unexpected change at least one of the I/O signal and reference signal.

Abstract: A method begins by a processing module identifying a set of stored files that includes an original file and one or more back-up copies of the original file. The method continues with the processing module dispersed storage error encoding one of the set of stored files to produce a plurality of sets of encoded data slices. The method continues with the processing module facilitating storage of the plurality of sets of encoded data slices. The method continues with the processing module facilitating deletion of the set of stored files.

Abstract: In a data processing system including a first master operably coupled to a peripheral bus interface and a plurality of peripherals operably coupled to the peripheral bus interface, wherein the first master communicates with each of the plurality of peripherals via the peripheral bus interface, a method includes initiating a write, by the first master, of configuration information to a first peripheral of the plurality of peripherals. In response to initiating the write, the configuration information is provided via the peripheral bus interface for storage into the first peripheral, wherein a first error syndrome of the configuration information is generated by the peripheral bus interface. The provided configuration information is stored in the first peripheral, and the first error syndrome is stored in storage circuitry of the peripheral bus interface. The first error syndrome can be used to check the integrity of configuration information during subsequent error checking.

Abstract: A data processing system includes an input/output (I/O) host bridge to which at least one I/O adapter is coupled by an I/O link. In a register of the I/O host bridge, a configuration partitionable endpoint (PE) field is set to identify a PE to be used for an I/O configuration operation. Thereafter, the host bridge initiates the I/O configuration operation on the I/O link and determines if an error occurred for the I/O configuration operation. In response to a determination that an error occurred for the I/O configuration operation, an error state is set in the I/O host bridge only for the PE indicated in the configuration PE field of the register in the I/O host bridge, wherein I/O configuration errors are isolated to particular PEs.

Abstract: An information handling system includes a peripheral component interconnect express root complex, a basic input output system, and a root complex mirroring block. The peripheral component interconnect express root complex includes a plurality of peripheral component interconnect express ports. The basic input output system is in communication with the peripheral component interconnect express root complex, and is configured to detect a peripheral component interconnect express adaptor configuration, and to set a peripheral component interconnect express mirroring setting based on the peripheral component interconnect express adaptor configuration. The root complex mirroring block is in communication with the basic input output system, and is configured to mirror data between a first peripheral component interconnect express adaptor and a second peripheral component interconnect express adaptor based on the peripheral component interconnect express mirroring setting.

Abstract: A method for maintaining reliable communication between a command initiator and a target device is provided. After the command initiator detects an error corresponding to the target device and a path between the command initiator and the target device, the command initiator performs a downshift evaluation. The initiator maintains a transmission speed if the downshift evaluation determines that forgoing a transmission speed downshift is required, and reduces the transmission speed if the downshift evaluation determines that transmission speed downshift is required. The command initiator then logs the downshift evaluation result and reports any transmission speed change to a user.

Abstract: An apparatus for selecting a candidate for a failure component causing errors from a plurality of components included in a network system, the apparatus includes a processor for executing a procedure. The procedure includes determining a relation class of a relation among the plurality of components on the basis of configuration information of the network system, each of the relations being classified into one of the relation classes in accordance with a direction of an error propagation, determining an investigation range for each component having an error on the basis of investigation information including an error type of an error occurred in the each component and an investigation direction corresponding to the relation class, the investigation range being a set of the components to be investigated, and selecting a component on the basis of an appearance frequency of each component in the investigation ranges as the candidate.

Abstract: A system for testing peripheral USB devices includes a test module and a plurality of USB ports equipped on an electronic device. The plurality of USB ports connects to a plurality of USB device. Each of the USB device includes a VID and a PID. The test module includes a storage module which stores a plurality of VIDs and PIDs. The test module connects to the plurality of USB ports, reads VIDs and PIDs of the plurality of USB device, and compares the VIDs and PIDs of the plurality of USB device with the VIDs and PIDs stored in the storage module.

Abstract: Embodiments relate to systems and methods for managing stalled storage devices of a storage system. In one embodiment, a method for managing access to storage devices includes determining that a first storage device, which stores a first resource, is stalled and transitioning the first storage device to a stalled state. The method also includes receiving an access request for at least a portion of the first resource while the first storage device is in the stalled state and attempting to provide access to a representation of the portion of the first resource from at least a second storage device that is not in a stalled state. In another embodiment, a method of managing access requests by a thread for a resource stored on a storage device includes initializing a thread access level for an access request by a thread for the resource.

Abstract: Methods and systems for implementing such methods for providing server fault notifications, diagnostic and system management information may include, but are not limited to: receiving a network fault status request input; illuminating one or more server node fault indicators for one or more degraded server nodes having one or more faults; receiving a server node fault status request input for a degraded server node having one or more faults; and displaying one or more diagnostic service notifications for one or more faults of the degraded server node. The displaying of the diagnostic service notifications may allow for the completion of various service operations associated with the service notifications once the information specific to a fault is presented.

Abstract: A method for tracing thread bus transactions in a multiprocessor system comprises decoding, by a processor, a first thread instruction of a thread, the thread comprising an ordered series of thread instructions. In the event the first thread instruction is a set bus trace enable bit (BTEB) instruction, the processor sets a bus trace enable bit corresponding to the thread. In the event the BTEB is set, the processor determines whether the first thread instruction is a trace-eligible instruction and, in the event the first thread instruction is a trace-eligible instruction, and the BTEB is set, the processor sets a snoop tag trace enable bit (STTEB). A hardware trace monitor (HTM) monitors bus transactions, each bus transaction comprising a STTE. In the event a monitored bus transaction comprises a set STTEB, the HTM stores the bus transaction as trace data. In the event a monitored bus transaction comprises a reset STTEB, the HTM does not store the bus transaction as trace data.

Abstract: A fault replay system uploads part or all of a log file from a subject system and replays the events detailed within the log file upon physical copies of devices present in the subject system. The replay of the log file events aid the determination of at which event a fault occurred and improves the accuracy of fault determination.

Abstract: Provided is a computer system including at least one host computer; and at least one storage system, characterized in that: the storage system has a disk drive and a disk controller, and provides a storage area of the disk drive as at least one logical unit; upon detecting a failure in a logical path serving as an access route from the host computer to the logical unit, the host computer specifies logical paths for accessing the same logical unit that is connected to the logical path where the failure is detected; the host computer executes failure detecting processing for the specified logical paths to judge whether the specified logical paths are normal or not; the host computer selects normal logical paths out of the specified logical paths; and the host computer accesses the logical unit via the normal logical paths selected.

Abstract: The peripheral device of the present invention is connected to a computer 200 through an interface cable 3, and is provided with a second memory device 13 for storing an evaluation program for 22 for evaluating the peripheral device 100 and its integrated circuit 400, a detection section 10 for detecting whether the mode indicating signal which is transmitted from the computer 200 indicates the test mode or the normal mode, and a starting means 15 which starts the evaluation program 22 on the second memory device 13 when the detection section 10 has detected that the mode indicating signal has shown the test mode. Thereby, the failure analysis of the peripheral device and its integrated circuit can be carried out in a state where the integrated circuit is mounted on the peripheral device.