Abstract: A method of guiding a semiconductor manufacturing process includes receiving semiconductor manufacturing process data corresponding to a target semiconductor product, generating first semiconductor characteristic data corresponding to the semiconductor manufacturing process data by using a technology computer-aided design (TCAD) model trained through machine learning based on training data including TCAD simulation data, generating second semiconductor characteristic data corresponding to the semiconductor manufacturing process data by using a compact model generated based on information of measurement of at least one semiconductor characteristic of a first semiconductor product, generating, based on the first semiconductor characteristic data and the second semiconductor characteristic data, a plurality of process policies respectively corresponding to a plurality of strategic references, by using a plurality of strategy models; and providing a final process policy corresponding to the target semiconductor p

Abstract: A method of designing a semiconductor device includes creating a library for test patterns on a frame and an on purpose violation layout on a main chip of a layout, and then creating filter marks according to the library. An OPC (optical proximity correction) is run using the layout, and an OPC verifying is performed for obtaining a pattern with hot spots to determine whether the hot spots are within the frame and the filter marks. When the hot spots are within the frame and the filter marks, a mask can be made. When the hot spots are outside the frame and the filter marks, it is necessary to check whether the hot spots need to be repaired. When the hot spots are within the frame and outside the filter marks, the hot spots are added into the library as data of the on purpose violation layout.

Abstract: A computer-implemented method and computing system are provided for failure prediction of a batch of manufactured objects. The method includes classifying, by a processor using a simulation, a set of samples with uniformly distributed parameter values, to generate sample classifications for the batch of manufactured objects. The method further includes determining, by the processor, a centroid of failing ones of the samples in the set, based on the sample classifications. The method also includes generating, by the processor, a new set of samples with a distribution around the centroid of the failing ones of the sample in the set. The method additionally includes populating, by the processor, a nearest neighbor vector space using the new set of samples. The method further includes classifying, by the processor, the new set of samples by performing a nearest neighbor search on the nearest neighbor vector space using a distance metric.

Abstract: Semiconductor yield is modeled at the die level to predict die that are susceptible to early lifetime failure (ELF). A first die yield calculation is made from parametric data obtained from wafer testing in a semiconductor manufacturing process. A second die yield calculation is made from die location only. The difference between the first die yield calculation and the second die yield calculation is a prediction delta. Based on an evaluation of the first die yield calculation and the prediction delta, the likelihood of early lifetime failure can be identified and an acceptable level of die loss can be established to remove die from further processing.

Abstract: A metrology method for use in determining one or more parameters of a three-dimensional patterned structure, the method including performing a fitting procedure between measured TEM image data of the patterned structure and simulated TEM image data of the patterned structure, determining a measured Lamellae position of at least one measured TEM image in the TEM image data from a best fit condition between the measured and simulated data, and generating output data indicative of the simulated TEM image data corresponding to the best fit condition to thereby enable determination therefrom of the one or more parameters of the structure.

Abstract: Provided is a method for patterning a substrate, comprising: forming a layer of radiation-sensitive material on a substrate; preparing a pattern in the layer of radiation-sensitive material using a lithographic process, the pattern being characterized by material structures having a critical dimension (CD) and a roughness; following the preparing the pattern, performing a shrink process to reduce the CD to a reduced CD; and performing a growth process to grow the reduced CD to a target CD. Roughness includes a line edge roughness (LER), a line width roughness (LWR), or both LER and LWR. Performing the shrink process comprises: coating the pattern with a hard mask, the coating generating a hard mask coated resist; baking the hard mask coated resist in a temperature range for a time period, the baking generating a baked coated resist; and developing the baked coated resist in deionized water.

Abstract: Methods and systems for fabricating an integrated circuit include training a machine learning model using a training set that includes known physical design layout patterns that are classified according to whether the patterns include a hotspot. It is determined whether an input physical design layout pattern includes a hotspot using the machine learning model. A hotspot localization is generated for the input physical design layout patterns. The input physical design pattern is adjusted to cure the hotspot. A circuit is fabricated in accordance with the adjusted input physical design layout pattern.

Abstract: A system, methods, and a computer program product for estimating a yield and creating corners of a circuit design with the aid of a failure boundary classification. The system, methods and computer program product provide for determining, based on how many sampling factors have failures, whether data samples are sufficient as input to scaled-sigma sampling. If the data samples are insufficient, the failure boundary classification is usable to determine whether the yield is high enough to meet a yield target. A design corner can be located by applying a binary search to results of scaled-sigma sampling. The failure boundary classification can aid in setting up the search.

Abstract: Selective importance sampling includes: first phase importance sampling of a plurality of data points to form a first subset of data points; determining a center of gravity of the first subset; determining, based upon the center of gravity, an orthogonal hyperplane; and a second phase importance sampling comprising: determining, for each point in the first subset, whether each point is above the hyperplane; and forming a second subset of data points, wherein the second subset is a subset of the first subset and wherein the second subset excludes each point of the first subset that has been determined to be above the hyperplane. The second subset also excludes all points within an ellipse below the hyperplane. Critical radial distances are determined from binary search or projection of first phase samples onto center of gravity direction as well as the maximal radius of the first subset around the center of gravity.

Abstract: A method of processing a wafer in a production tool includes receiving a wafer at a process tool, the wafer associated with a wafer process history, acquiring data associated with wafers processed by the process tool and having the wafer process history, when the amount of acquired data is insufficient, acquiring additional data associated with wafers processed by the process tool and having a process history differing from the wafer process history by a single factor, when the amount of acquired data is sufficient, determining a process parameter using the acquired data, and processing the wafer with the production tool using the process parameter.

Abstract: A non-transitory computer readable storage medium, comprising executable instructions to collect network traffic data, produce a Fourier signature from the network traffic data, associate the Fourier signature with a known pattern, collect new network traffic data, produce a new Fourier signature from the new network traffic data, compare the new Fourier signature with the Fourier signature to selectively identify a match and associate the new network traffic data with the known pattern upon a match.

Abstract: Selective importance sampling includes: first phase importance sampling of a plurality of data points to form a first subset of data points; determining a center of gravity of the first subset; determining, based upon the center of gravity, an orthogonal hyperplane; and a second phase importance sampling comprising: determining, for each point in the first subset, whether each point is above the hyperplane; and forming a second subset of data points, wherein the second subset is a subset of the first subset and wherein the second subset excludes each point of the first subset that has been determined to be above the hyperplane. The second subset also excludes all points within an ellipse below the hyperplane. Critical radial distances are determined from binary search or projection of first phase samples onto center of gravity direction as well as the maximal radius of the first subset around the center of gravity.

Abstract: Methods and systems for determining a source shape, a mask shape and a target shape for a lithography process are disclosed. One such method includes receiving source, mask and target constraints and formulating an optimization problem that is based on the source, mask and target constraints and incorporates contour-based assessments for the target shape that are based on physical design quality of a circuit. Further, the optimization problem is solved by integrating over process condition variations to simultaneously determine the source shape, the mask shape and the target shape. In addition, the determined source shape and mask shape are output.

Abstract: For mapping a sustainable, differentially reliable architecture for dark silicon, a calculation module calculates an expected energy efficiency for a prior mapping of process threads for a plurality of cores. The calculation module further calculates a workload acceptance capacity (WAC) from degradation rates for the plurality of cores. A map module maps the process threads to the plurality of cores based on at least one of the expected energy efficiency and the WAC to satisfy a mapping policy. A specified number of the plurality of cores is not powered.

Abstract: For improving wafer fabrication, yield and lifetime of wafers are predicted by determining coefficients of a yield domain for wafer yield prediction and a lifetime domain for a wafer lifetime prediction, an integral domain, an electric/layout domain, a metrology/defect domain, and a machine sensor domain in a hierarchical manner. With the aid of the hierarchically-determined coefficients, noises in prediction can be reduced so that precision of prediction results of the yields or the lifetimes of wafers can be raised.

Abstract: One or more embodiments of techniques or systems for variation factor assignment for a device are provided herein. In some embodiments, a peripheral environment is determined for a device. A peripheral environment is a layout structure or an instance. When the peripheral environment is the layout structure, a variation factor is assigned to the device based on an architecture associated with the layout structure. When the peripheral environment is the instance, the variation factor is assigned to the device based on a bounding window created for the instance. In this manner, variation factor assignment is provided, such that a first device within a first block of a die has a different variation factor than a second device within a second block of the die, thus giving finer granularity to variation factor assignments.

Abstract: Disclosed are embodiments of a method, system and computer program product for optimizing integrated circuit product yield by re-centering the manufacturing line and, optionally, adjusting wafer-level chip dispositioning rules based on the results of post-manufacture (e.g., wafer-level or module-level) performance path testing. In the embodiments, a correlation is made between in-line parameter measurements and performance measurements acquired during the post-manufacture performance path testing. Then, based on this correlation, the manufacturing line can be re-centered. Optionally, an additional correlation is made between performance measurements acquired during wafer-level performance testing and performance measurements acquired particularly during module-level performance path testing and, based on this additional correlation, adjustments can be made to the wafer-level chip dispositioning rules to further minimize yield loss.

Abstract: A layout decomposition method and a method for manufacturing a semiconductor device applying the same are provided. According to the layout decomposition method, a design layout is received by the logic processer of a computing system. A design rule for layout decomposition is then identified by the logic processer, including identifying the loose areas (areas with loosely distributed features) and dense areas (areas with densely distributed features) on a substrate, and identifying first areas with odd-numbered features and second areas with even-numbered features on the substrate. Next, a first mask with a first pattern and a second mask with a second pattern are generated corresponding to results of design rule identification by the computing system.

Abstract: A method of correcting assist features includes the following steps. At first, a first layout pattern is received by a computer system, and the first layout pattern is split into a plurality of first regions. Subsequently, a plurality of assist features are added into the first layout pattern to form a second layout pattern, wherein at least one of the assist features neighboring any one of the edges of the first regions is defined as a selected pattern. Then, the second layout pattern is split into a plurality of second regions. Afterwards, a check step is performed on the second region including the selected pattern, and the second layout pattern is corrected to form a corrected second layout pattern.

Abstract: A method for optimizing mask assignment for multiple pattern processes includes, through a computing system, defining which of a number of vias to be formed between two metal layers are critical based on metal lines interacting with the vias, determining overlay control errors for an alignment tree that defines mask alignment for formation of the two metal layers and the vias, and setting both the alignment tree and mask assignment for the vias so as to maximize the placement of critical vias on masks that have less overlay control error to the masks forming the relevant metal lines.

Abstract: One or more techniques or systems for incorporating a common template into a system on chip (SOC) design are provided herein. For example, a common template mask set is generated based on a first set of polygon positions from a first vendor and a second set of polygon positions from a second vendor. A third party creates a third party SOC design using a set of design rules generated based on the common template mask set. The common template is fabricated based on the third party SOC design using the common template mask set. Because the common template is formed using the common template mask set and because the common template mask set is based on polygon positions from both the first vendor and the second vendor, a part can be connected to the SOC regardless of whether the part is sourced from the first vendor or the second vendor.

Abstract: Impact on parametric performance of physical design choices for transistors is scored for on-current and off-current of the transistors. The impact of the design parameters are incorporated into parameters that measure predicted shift in mean on-current and mean off-current and parameters that measure predicted increase in deviations in the distribution of on-current and the off-current. Statistics may be taken at a cell level, a block level, or a chip level to optimize a chip design in a design phase, or to predict changes in parametric yield during manufacturing or after a depressed parametric yield is observed. Further, parametric yield and current level may be predicted region by region and compared with observed thermal emission to pinpoint any anomaly region in a chip to facilitate detection and correction in any mistakes in chip design.

Abstract: The fabrication of the wafer may be analyzed starting from when the wafer is in a partially fabricated state. The value of a specified performance parameter may be determined at a plurality of locations on an active area of a die of the wafer. The specified performance parameter is known to be indicative of a particular fabrication process in the fabrication. Evaluation information may then be obtained based on a variance of the value of the performance parameter at the plurality of locations. This may be done without affecting a usability of a chip that is created from the die. The evaluation information may be used to evaluate how one or more processes that include the particular fabrication process that was indicated by the performance parameter value was performed.

Abstract: A reticle including exposure monitoring keys. The reticle includes an exposure region that is to be exposed to light during an exposure process, and a non-exposure region surrounding the exposure region and not to be exposed to the light. The exposure monitoring keys are disposed across a boundary between the exposure region and the non-exposure region.

Abstract: In accordance with an embodiment, an evaluation sample includes a substrate and a polycrystalline film on the substrate. The polycrystalline film has crystal grains. A specific orientation plane is exposed on the surface of each crystal grain. The orientation planes exhibit random angles to the surface of the substrate.

Abstract: A method includes generating one or more routes usable for implementing a conductive path of an integrated circuit. A corresponding cost function value for the one or more routes is calculated according to a first cost function, including adjusting the corresponding cost function value based on whether the corresponding route is at least partially assigned to be formed in a conductive layer by a first patterning process or a second patterning process. The integrated circuit has electrical devices and the conductive layer, and the conductive layer has a first set of conductive lines formed by the first patterning process and a second set of conductive lines formed by the second patterning process. The first set of conductive lines has a unit resistance less than that of the second set of conductive lines. The conductive path electrically connects two of the electrical devices of the integrated circuit.

Abstract: A portion of a layout of a single layer of an integrated circuit is to be multi-patterned. The patterns are divided into first and second groups, to be patterned on the single layer by a first mask or a second mask. For each portion of each pattern, a spacing relationship is determined between that portion and any adjacent pattern on either or both sides. A processor computes a first capacitance (C), resistance (R), or resistance-capacitance (RC) cost of assigning the first group to the first mask and the second group to the second mask, and a second cost of assigning the first group to the second mask and the second group to the first mask, based on the spacing relationships. The first group is assigned to the first mask and the second group to the second mask if the first cost is lower than the second cost.

Abstract: Variation of a parameter of interest is reduced over a field of interest in, for example, an object design, such as a circuit design. The field of interest is divided into tiles. A parameter value is found for each tile and for a group of tiles around each tile. Using these values, variation of the parameter is determined. An adjusted value of the parameter for each tile is determined taking limits into account, iterating until variation is below a threshold value. Parameter uniformity is improved in some applications by over 30% with runtime reduced by an order of magnitude.

Abstract: A method and system for fracturing or mask data preparation is disclosed in which the central core portion of a diagonal pattern is fractured using overlapping variable shaped beam (VSB) shots, and an outer portion of the diagonal pattern is fractured using non-overlapping VSB shots. A transition region is interposed between the central core and outer pattern portions, and transition region shots are generated so as to produce in the transferred pattern a smooth transition in pattern characteristics such as line edge roughness or period of waviness, from the central core portion of the pattern to the outer portion of the pattern. A pattern determined by the transition region shots is then compared to a reticle pattern created using conventional non-overlapping VSB shots. Methods for forming a semiconductor device layout pattern on a reticle or substrate are also disclosed.

Abstract: A mask includes a main pattern for resolving a target pattern to be formed on a substrate and an auxiliary pattern not resolving. Values of parameters of the main pattern and the auxiliary pattern are set. An image is calculated that is formed when the main pattern and the auxiliary pattern determined by the values of the parameters of the main pattern and the auxiliary pattern are projected by a projection optical system. Based on a result of the calculation that is performed by modifying the values of the parameters of the main pattern and the auxiliary pattern, the values of the parameters of the main pattern and the auxiliary pattern are determined to generate data of the mask including the main pattern and the auxiliary pattern determined.

Abstract: A route technique includes: receiving an input specifying a plurality of semiconductor device components and their logical connections; determining route information pertaining to a plurality of routes that connect in one or more metal layers the semiconductor device components according to their logical connections, the determination being based at least in part on a plurality of predefined tracks associated with a metal layer; and outputting at least a portion of the route information. A first portion of the plurality of predefined tracks corresponds to a first color and a second portion of the plurality of predefined tracks corresponds to a second color.

Abstract: A layout decomposition method and a method for manufacturing a semiconductor device applying the same are provided. According to the layout decomposition method, a design layout is received by the logic processor of a computing system. A design rule for layout decomposition is then identified by the logic processor, including identifying dense areas (areas with densely distributed features) on a substrate, and identifying areas with odd-numbered features on the substrate. Next, a first mask with a first pattern and a second mask with a second pattern are generated corresponding to results of design rule identification by the computing system for fabricating patterns of features in at least two of the areas with odd-numbered features in one of the dense areas.

Abstract: A mask pattern design method includes: dividing design layout data for a pattern into multiple regions and extracting any region wherein transfer dimensions obtained from a transfer simulation of the pattern from the plurality of regions exceeds a predetermined allowance range; setting a process window of which multiple transfer conditions of the pattern data from the region extracted by the process are each changed, and computing transfer dimensions obtained from a transfer simulation with each transfer condition with the process window; and extracting the transfer conditions wherein the transfer dimension obtained from the transfer simulation with each transfer condition with the process window exceeds a predetermined allowance range, and computing yield from an occurrence probability regarding the transfer condition.

Abstract: A process and apparatus are provided for automated pattern-based semiconductor design layout correction. Embodiments include scanning a drawn semiconductor design layout to determine a difficult-to-manufacture pattern within the drawn semiconductor design layout based on a match with a pre-characterized difficult-to-manufacture pattern, determining a corrected pattern based on a pre-determined correlation between the corrected pattern and the pre-characterized difficult-to-manufacture pattern, and replacing the difficult-to-manufacture pattern with the corrected pattern within the drawn semiconductor design layout.

Abstract: The present invention relates to methods and systems for designing gauge patterns that are extremely sensitive to parameter variation, and thus robust against random and repetitive measurement errors in calibration of a lithographic process utilized to image a target design having a plurality of features. The method may include identifying most sensitive line width/pitch combination with optimal assist feature placement which leads to most sensitive CD (or other lithography response parameter) changes against lithography process parameter variations, such as wavefront aberration parameter variation. The method may also include designing gauges which have more than one test patterns, such that a combined response of the gauge can be tailored to generate a certain response to wavefront-related or other lithographic process parameters. The sensitivity against parameter variation leads to robust performance against random measurement error and/or any other measurement error.

Abstract: Aspects of the invention relate to techniques for detecting and correcting electrical hotspots in a layout design for a circuit design comprising an analog circuit. Layout parameters for device instances associated with electrical constraints are first extracted. Based on the extracted layout parameters, electrical parameter variations for the device instances may be computed to identify one or more electrical hotspots in the layout design. A sensitivity analysis of the one or more electrical hotspots is performed to generate repair hints. Based on the repair hints, the layout design is adjusted.

Abstract: According to one embodiment, generating virtual data by mirroring data based on a dimension measurement result in a measurement region on an inner side of a shot region to a non-shot region on an outer side of a shot edge, and calculating dose data of the measurement region and a non-measurement region based on data in the measurement region and the virtual data are included.

Abstract: A semiconductor inspection apparatus identifies regions of a reticle or semiconductor wafer appropriate for cell-to-cell inspection by analyzing a semiconductor design database. Appropriate regions can be identified in a region map for use by offline inspection tools.

Abstract: One illustrative method disclosed herein involves producing an initial circuit layout, prior to decomposing the initial circuit layout, identifying at least one potential non-double-patterning-compliant (NDPC) pattern in the initial circuit layout, fixing the at least one potential non-double-patterning-compliant (NDPC) pattern so as to produce a double-patterning-compliant (DPT) pattern, producing a modified circuit layout by removing the potential non-double-patterning-compliant (NDPC) pattern and adding the double-patterning-compliant (DPT) pattern to the initial circuit layout, and performing design rule checking and double patterning compliance checking on the modified circuit layout.

Abstract: A method for printing a periodic pattern having a first symmetry and a first period into a photosensitive layer. The method includes providing a mask bearing a pattern of at least two overlapping sub-patterns which have a second symmetry and a second period, the features of each sub-pattern being formed in a transmissive material, providing a substrate bearing the layer, arranging the mask with a separation from the substrate, providing light having a central wavelength for illuminating the mask to generate a light-field in which light of the central wavelength forms a range of intensity distributions between Talbot planes, illuminating said mask pattern with said light while maintaining the separation or changing it by a distance whereby the photosensitive layer is exposed to an average of the range of intensity distributions, wherein the light transmitted by each sub-pattern is shifted in phase relative to that transmitted by another sub-pattern.

Abstract: The present invention relates to a method for tuning lithography systems so as to allow different lithography systems to image different patterns utilizing a known process that does not require a trial and error process to be performed to optimize the process and lithography system settings for each individual lithography system. According to some aspects, the present invention relates to a method for a generic model-based matching and tuning which works for any pattern. Thus it eliminates the requirements for CD measurements or gauge selection. According to further aspects, the invention is also versatile in that it can be combined with certain conventional techniques to deliver excellent performance for certain important patterns while achieving universal pattern coverage at the same time.

Abstract: A method for reducing an effect of flare produced by a lithographic apparatus for imaging a design layout onto a substrate is described. A flare map in an exposure field of the lithographic apparatus is simulated by mathematically combining a density map of the design layout at the exposure field with a point spread function (PSF), wherein system-specific effects on the flare map may be incorporated in the simulation. Location-dependent flare corrections for the design layout are calculated by using the determined flare map, thereby reducing the effect of flare. Some of the system-specific effects included in the simulation are: a flare effect due to reflection from black border of a mask, a flare effect due to reflection from one or more reticle-masking blades defining an exposure slit, a flare effect due to overscan, a flare effect due reflections from a gas-lock sub-aperture of a dynamic gas lock (DGL) mechanism, and a flare effect due to contribution from neighboring exposure fields.

Abstract: Data associated with a substrate can be processed by measuring a property of at least a first type of specific features and a second type of specific features on a substrate. The first type of specific features is measured at a first plurality of locations on the substrate to generate a first group of measured values, and the second type of specific features is measured at a second plurality of locations on the substrate to generate a second group of measured values, in which the first and second groups of measured values are influenced by critical dimension variations of the substrate. A combined measurement function is defined based on combining the at least first and second groups of measured values. At least one group of measured values is transformed prior to combining with another group or other groups of measured values, in which the transformation is defined by a group of coefficients.

Abstract: An inspection data generator generates inspection data used to inspect a pattern transferred onto the same material layer using exposure processes. An input part of the generator receives first layout data for a mask used in a first exposure process and second layout data for a mask used in a second exposure process, and receives a measured value of a misalignment between a first transfer pattern actually transferred onto the material layer in the first exposure process and a second transfer pattern actually transferred onto the material layer in the second exposure process. A processor unit generates the inspection data by shifting the first layout data and the second layout data from each other by an amount corresponding to the measured value and then combining the first layout data with the second layout data. An output part outputs the inspection data to inspect the pattern transferred onto the material layer.

Abstract: A method of forming a semiconductor circuit includes receiving target layout. An optical proximity correction process is performed on the target layout data to generate a post-OPC layout. A patterning process is performed using the post-OPC layout. The post-OPC layout may be adjusted to compensate for a top loss of an etch mask layer.

Abstract: A process and apparatus are provided for generating and evaluating one or more metrics for analyzing the design and manufacture of semiconductor devices. Embodiments include scanning a drawn semiconductor design layout to determine a difficult-to-manufacture pattern within the drawn semiconductor design layout based on a match with a pre-characterized difficult-to-manufacture pattern determining a corrected pattern based on a pre-determined correlation between the corrected pattern and the pre-characterized difficult-to-manufacture pattern, and replacing the difficult-to-manufacture pattern with the corrected pattern within the drawn semiconductor design layout.

Abstract: Methods are disclosed of modifying an integrated circuit (IC) design that utilizes multiple patterning technology (MPT). The methods include configuring a first layout of an integrated circuit, having at least one layer with features to be formed utilizing fabrication by at least two masks. The at least one layer includes a plurality of active cells and a plurality of spare cells. A second layout is configured to re-route the spare cells and active cells, wherein the re-routing utilizes at least a portion of the plurality of spare cells. Fewer than all of the at least two masks are replaced to configure the second layout.

Abstract: The invention provides for the acceleration of a source mask optimization process. In some implementations, a layout design is analyzed by a pattern matching process, wherein sections of the layout design having similar patterns are identified and consolidated into pattern groups. Subsequently, sections of the layout design corresponding to the pattern groups may be analyzed to determine their compatibility with the optical lithographic process, and the compatibility of these sections may be classified based upon a “cost function.” With further implementations, the analyzed sections may be classified as printable or difficult to print, depending upon the particular lithographic system. The compatibility of various sections of a layout design may then be utilized to optimize the layout design during a lithographic friendly design process. For example, during the design phase, sections categorized as difficult to print may be flagged for further optimization, processing, or redesign.

Abstract: A process and apparatus are provided for generating and evaluating one or more metrics for analyzing the design and manufacture of semiconductor devices. Embodiments include scanning a drawn semiconductor design layout to determine a difficult-to-manufacture pattern within the drawn semiconductor design layout based on a match with a pre-characterized difficult-to-manufacture pattern determining a corrected pattern based on a pre-determined correlation between the corrected pattern and the pre-characterized difficult-to-manufacture pattern, and replacing the difficult-to-manufacture pattern with the corrected pattern within the drawn semiconductor design layout.

Abstract: In an imaging recipe creating apparatus that uses a scanning electron microscope to create an imaging recipe for SEM observation of a semiconductor pattern, in order that the imaging recipe for measuring the wiring width and other various dimension values of the pattern from an observation image and thus evaluating the shape of the pattern is automatically generated within a minimum time by the analysis using the CAD image obtained by conversion from CAD data, an CAD image creation unit that creates the CAD image by converting the CAD data into an image format includes an image-quantizing width determining section, a brightness information providing section, and a pattern shape deformation processing section; the imaging recipe being created using the CAD image created by the CAD image creation unit.