Design Of Semiconductor Mask Or Reticle Patents (Class 716/50)
  • Patent number: 10430544
    Abstract: A method of generating a plurality of photomasks includes generating a circuit graph. The circuit graph comprises a plurality of vertices and a plurality of edges. Each of the plurality of vertices is representative of one of a plurality of conductive lines. The plurality of edges are representative of a spacing between the conductive lines less than an acceptable minimum distance. Kn+1 graph comprising a first set of vertices selected from the plurality of vertices connected in series by a first set of edges selected from the plurality of edges and having at least one non-series edge connection between a first vertex and a second vertex selected from the first set of vertices is reduced by merging a third vertex into a fourth vertex selected from the first set of the plurality of vertices. An n-pattern conflict check is performed and the photomasks generated based on the result.
    Type: Grant
    Filed: September 2, 2016
    Date of Patent: October 1, 2019
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Nien-Yu Tsai, Chin-Chang Hsu, Wen-Ju Preet Yang, Hsien-Hsin Sean Lee
  • Patent number: 10429731
    Abstract: The invention relates to a method and a device for generating a reference image in the characterization of a mask for microlithography, wherein the mask comprises a plurality of structures and wherein the reference image is generated by simulation of the imaging of said mask, said imaging being effected by a given optical system, both using a rigorous simulation and using a Kirchhoff simulation, wherein the method comprises the following steps: assigning each structure of said plurality of structures either to a first category or to a second category, calculating a plurality of first partial spectra for structures of the first category with implementation of rigorous simulations, calculating a second partial spectrum for structures of the second category with implementation of a Kirchhoff simulation, generating a hybrid spectrum on the basis of the first partial spectra and the second partial spectrum, and generating the reference image with implementation of an optical forward propagation of said hybrid spec
    Type: Grant
    Filed: November 9, 2017
    Date of Patent: October 1, 2019
    Assignee: Carl Zeiss SMT GmbH
    Inventors: Carsten Schmidt, Michael Himmelhaus
  • Patent number: 10423745
    Abstract: A method for reducing an effect of flare produced by a lithographic apparatus for imaging a design layout onto a substrate is described. A flare map in an exposure field of the lithographic apparatus is simulated by mathematically combining a density map of the design layout at the exposure field with a point spread function (PSF), wherein system-specific effects on the flare map may be incorporated in the simulation. Location-dependent flare corrections for the design layout are calculated by using the determined flare map, thereby reducing the effect of flare.
    Type: Grant
    Filed: November 10, 2014
    Date of Patent: September 24, 2019
    Assignee: ASML Netherlands B.V.
    Inventors: Hua-Yu Liu, Jiangwei Li, Luoqi Chen, Wei Liu, Jiong Jiang
  • Patent number: 10417376
    Abstract: Source beam optimization (SBO) methods are disclosed herein for enhancing lithography printability. An exemplary method includes receiving an integrated circuit (IC) design layout and performing an SBO process using the IC design layout to generate a mask shot map and an illumination source map. The SBO process uses an SBO model that collectively simulates a mask making process using the mask shot map and a wafer making process using the illumination source map. A mask can be fabricated using the mask shot map, and a wafer can be fabricated using the illumination source map (and, in some implementations, using the mask fabricated using the mask shot map). The wafer includes a final wafer pattern that corresponds with a target wafer pattern defined by the IC design layout. The SBO methods disclosed herein can significantly reduce (or eliminate) variances between the final wafer pattern and the target wafer pattern.
    Type: Grant
    Filed: June 4, 2018
    Date of Patent: September 17, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Hsu-Ting Huang, Shuo-Yen Chou, Ru-Gun Liu
  • Patent number: 10408754
    Abstract: Disclosed is a method of measuring a target, an associated substrate, a metrology apparatus and a lithographic apparatus. In one arrangement the target comprises a layered structure. The layered structure has a first target structure in a first layer and a second target structure in a second layer. The method comprises illuminating the target with measurement radiation. Scattered radiation formed by interference between plural predetermined diffraction orders is detected. The predetermined diffraction orders are generated by diffraction of the measurement radiation from the first target structure and are subsequently diffracted from the second target structure. A characteristic of the lithographic process is calculated using the detected scattered radiation formed by the interference between the predetermined diffraction orders.
    Type: Grant
    Filed: July 20, 2017
    Date of Patent: September 10, 2019
    Assignee: ASML Netherlands B.V.
    Inventors: Euclid Eberle Moon, Arie Jeffrey Den Boef
  • Patent number: 10387601
    Abstract: Systems and methods are disclosed for storing dynamic layer content in a design file. A design file is received having design data corresponding to a plurality of process layers. A geometric operation formula is also received. A processor generates a polygon having dynamic layer content that is formed by applying the geometric operation formula on two or more of the plurality of process layers. The updated design file is stored, the design file now having a polygon having dynamic layer content.
    Type: Grant
    Filed: November 22, 2016
    Date of Patent: August 20, 2019
    Assignee: KLA-Tencor Corporation
    Inventors: Thirupurasundari Jayaraman, Srikanth Kandukuri, Gordon Rouse, Anil Raman, Kenong Wu, Praveen Gunasekaran, Aravindh Balaji, Ankit Jain
  • Patent number: 10386727
    Abstract: A method to improve a lithographic process for imaging a portion of a design layout onto a substrate using a lithographic projection apparatus, the method including: computing a multi-variable cost function of a plurality of design variables that are characteristics of the lithographic process, and reconfiguring the characteristics of the lithographic process by adjusting the design variables until a predefined termination condition is satisfied. The multi-variable cost function may be a function of one or more pattern shift errors. Reconfiguration of the characteristics may be under one or more constraints on the one or more pattern shift errors.
    Type: Grant
    Filed: March 3, 2015
    Date of Patent: August 20, 2019
    Assignee: ASML Netherlands B.V.
    Inventors: Duan-Fu Stephen Hsu, Jianjun Jia, Xiaofeng Liu, Cuiping Zhang
  • Patent number: 10354886
    Abstract: According to one embodiment of the present invention, a computer-implemented method for validating a design includes generating, using the computer, a first graph representative of the design, when the computer is invoked to validate the design, and decompose, using the computer, the first graph into at least three sets using a hybrid evolutionary algorithm to form a colored graph.
    Type: Grant
    Filed: February 20, 2014
    Date of Patent: July 16, 2019
    Assignee: Synopsys, Inc.
    Inventors: Erdem Cilingir, Srini Arikati
  • Patent number: 10339250
    Abstract: A method of generating an ECO-layout of an ECO base cell includes: generating first and second active area patterns and arranging them on opposite sides of a first axis; generating non-overlapping first, second and third conductive patterns and arranging each of them so as to correspondingly overlap the first and second active area patterns; locating the first conductive pattern between the second and third conductive patterns; generating a first cut-pattern which overlaps corresponding central regions of the second, and third conductive patterns; aligning the first cut-pattern relative to the first axis; generating a fourth conductive pattern; locating the fourth conductive pattern over an area bounded by the first cut-pattern; and expanding the fourth conductive pattern to occupy an area which substantially overlaps a first segment of the first conductive pattern and a first segment of one of the second and third conductive patterns, thereby resulting in the ECO-layout.
    Type: Grant
    Filed: March 30, 2017
    Date of Patent: July 2, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Li-Chun Tien, Ting-Wei Chiang, Shun Li Chen, Ting Yu Chen, XinYong Wang
  • Patent number: 10331043
    Abstract: A method of devising a target arrangement, and associated target and reticle. The target includes a plurality of gratings, each grating having a plurality of substructures. The method includes: defining a target area; locating the substructures within the target area so as to form the gratings; and locating assist features at the periphery of the gratings, the assist features being configured to reduce measured intensity peaks at the periphery of the gratings. The method may include an optimization process including modelling a resultant image obtained by inspection of the target using a metrology process; and evaluating whether the target arrangement is optimized for detection using a metrology process.
    Type: Grant
    Filed: January 29, 2015
    Date of Patent: June 25, 2019
    Assignee: ASML Netherlands B.V.
    Inventors: Henricus Wilhelmus Maria Van Buel, Johannes Marcus Maria Beltman, Xing Lan Liu, Hendrik Jan Hidde Smilde, Richard Johannes Franciscus Van Haren
  • Patent number: 10331844
    Abstract: Methods for designing and fabricating a current mirror. A first layout is received for a first back-end-of-line (BEOL) stack that is coupled with an emitter of a bipolar junction transistor in a current mirror that has a first current ratio. A second layout for a second back-end-of-line (BEOL) stack, which differs from the first BEOL stack, is determined such that, when the second BEOL stack is coupled with the emitter of the bipolar junction transistor, the first current ratio is changed to a second current ratio. The change from the first current ratio to the second current ratio, which is based on the change from the first layout for the first BEOL stack to the second layout for the second BEOL stack, is accomplished without changing a front-end-of-line (FEOL) layout of the bipolar junction transistor.
    Type: Grant
    Filed: October 11, 2016
    Date of Patent: June 25, 2019
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Vibhor Jain, James W. Adkisson
  • Patent number: 10318698
    Abstract: A method includes operations below. A layout of a circuit is converted to a first conflict graph. A first vertex and a second vertex in the first conflict graph are adjusted based on first data indicating a color patterns assignment for the circuit, in order to generate a second conflict graph, in which the first vertex indicates a first pattern in the layout, and the second vertex indicates a second pattern in the layout. According to the second conflict graph, a first color pattern is assigned to both of the first pattern and the second pattern, or the first color pattern is assigned to the first pattern and a second color pattern is assigned to the second pattern, in order to generate second data for fabricating the circuit.
    Type: Grant
    Filed: May 15, 2017
    Date of Patent: June 11, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Yen-Hung Lin, Yuan-Te Hou, Chin-Chang Hsu
  • Patent number: 10303840
    Abstract: Integrated circuits are manufactured using a direct write lithography step to at least partially form at least one layer within the integrated circuit. The performance characteristics of an at least partially formed integrated circuit are measured and then the layout design to be applied with a direct write lithography step is varied in dependence upon those performance characteristics. Accordingly, the performance of an individual integrated circuit, wafer of integrated circuits or batch of wafers may be altered.
    Type: Grant
    Filed: April 27, 2017
    Date of Patent: May 28, 2019
    Assignee: ARM Limited
    Inventor: Gregory Munson Yeric
  • Patent number: 10268791
    Abstract: A method is disclosed that includes the operation below. Vertices in a conflict graph are sorted into a first clique and a second clique, in which the conflict graph corresponds to a layout of a circuit. A first vertex of the vertices is merged with a second vertex of the vertices, to generate a reduced graph, in which the first clique excludes the second vertex, and the second clique excludes the first vertex. A first color pattern of a plurality of color patterns is assigned to a first pattern, corresponding to the first vertex, and a second pattern, corresponding to the second vertex, in the layout according to the reduced graph.
    Type: Grant
    Filed: December 11, 2015
    Date of Patent: April 23, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Yen-Hung Lin, Chung-Hsing Wang, Chin-Chou Liu, Chi-Wei Hu
  • Patent number: 10255397
    Abstract: A method for rasterizing a mask layout includes driving an image converter to obtain a raster image of the mask layout. The raster image is obtained by providing a pattern from the mask layout on a grid, obtaining grid points surrounding an edge of the pattern, constructing a path on the pattern which extends from the edge toward adjacent edges of the pattern, and allocating a raster value to each of the grid points. The raster value corresponds to an overlap area between a pixel, having a center located on one of the grid points, and the pattern having a boundary limited by the path.
    Type: Grant
    Filed: January 30, 2017
    Date of Patent: April 9, 2019
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Sibo Cai, Moon-Gyu Jeong
  • Patent number: 10209615
    Abstract: A method and an apparatus for determining near field images for optical lithography include receiving a thin mask image indicative of a photomask feature, in which the thin mask image is determined without considering a mask topography effect associated with the photomask feature, and determining a near field image from the thin mask image by a processor using an artificial neural network (ANN), in which the ANN uses the thin mask image as input. The apparatus includes a processor and a memory coupled to the processor. The memory configured to store instructions executed by the processor to perform the method.
    Type: Grant
    Filed: May 26, 2017
    Date of Patent: February 19, 2019
    Assignee: Xtal, Inc.
    Inventors: Jiangwei Li, Yumin Wang, Jun Liu
  • Patent number: 10146124
    Abstract: A method, an apparatus, and a non-transitory computer readable medium for full chip mask pattern generation include: generating, by a processor, an initial mask image from target polygons, performing, by the processor, a global image based full chip optimization of the initial mask image to generate new mask pattern polygons, wherein the global image based full chip optimization co-optimizes main feature polygons and SRAF image pixels, determining performance index information based on the global image based full chip optimization, wherein the performance index information comprises data for assisting a global polygon optimization, generating a mask based on the global polygon optimization of the new mask pattern polygons using the performance index information, and generating optimized mask patterns based on a localized polygon optimization of the mask.
    Type: Grant
    Filed: February 23, 2017
    Date of Patent: December 4, 2018
    Assignee: Xtal, Inc.
    Inventors: Jiangwei Li, Jihui Huang, Ke Zhao
  • Patent number: 10055531
    Abstract: In some embodiments, in a method performed by at least one processor, spaces among a plurality of layout segments is analyzed by the at least one processor to determine at least one first-type conflicted edge according to a first predetermined length. Spaces among the plurality of layout segments is analyzed by the at least one processor to determine a plurality of potential conflicted edges according to a second predetermined length different from the first predetermined length. At least one second-type conflicted edge is determined by the at least one processor according to the plurality of potential conflicted edges. If at least one odd-vertex loop is formed in the plurality of layout segments is checked by the at least one processor according to the at least one first-type conflicted edge and the at least one second-type conflicted edge to determine if a violation occurs in the plurality of layout segments.
    Type: Grant
    Filed: February 13, 2015
    Date of Patent: August 21, 2018
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Chung-Hsing Wang, King-Ho Tam, Yuan-Te Hou, Chin-Chang Hsu, Meng-Kai Hsu
  • Patent number: 9934347
    Abstract: A method of designing a layout of an integrated circuit (IC) includes placing a first cell in the layout, placing a second cell in the layout adjacent to the first cell at a first boundary between the first and second cells, and generating a plurality of commands executable by a processor to form a semiconductor device based on the layout. The first cell includes a first pattern and a second pattern. The first and second patterns are adjacent to the first boundary, the first and second patterns have different colors, and a first boundary space between the first pattern and the first boundary is different from a second boundary space between the second pattern and the first boundary.
    Type: Grant
    Filed: September 29, 2015
    Date of Patent: April 3, 2018
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Jae-Woo Seo, Ha-Young Kim, Hyun-Jeong Roh
  • Patent number: 9836556
    Abstract: Aspects of the disclosed technology relate to techniques of optical proximity correction for directed self-assembly guiding patterns. An initial mask pattern for photomask fabrication is first generated by performing a plurality of conventional optical proximity correction iterations. Predicted print errors for two or more via-type features are then determined based on a predicted guiding pattern for the two or more via-type features, a target guiding pattern for the two or more via-type features, and correlation information between a plurality of guiding pattern parameters and location and size parameters for the two or more via-type features. Here the predicted guiding pattern is derived based on the initial mask pattern. Based on the predicted print errors and the correlation information, the initial mask pattern is adjusted to generate a new mask pattern.
    Type: Grant
    Filed: March 30, 2016
    Date of Patent: December 5, 2017
    Assignee: Mentor Graphics Corporation
    Inventors: Junjiang Lei, Le Hong, Yuansheng Ma
  • Patent number: 9766539
    Abstract: A method which determines patterns for a plurality of masks to be executed by a processor includes acquiring data on a pattern containing a plurality of pattern elements, and assigning the acquired plurality of pattern elements into masks, decomposing the acquired plurality of pattern elements into patterns of the masks, and calculating an evaluation value for an evaluation index, based on a number of masks, the distances between a plurality of pattern elements in each mask, and an angle of a line connecting a plurality of pattern elements in each mask. In the method, a pattern of each mask is determined based on the calculated evaluation value.
    Type: Grant
    Filed: February 19, 2014
    Date of Patent: September 19, 2017
    Assignee: CANON KABUSHIKI KAISHA
    Inventors: Ryo Nakayama, Yuichi Gyoda
  • Patent number: 9711372
    Abstract: In some embodiments, the disclosure relates to a method of forming an integrated circuit device. The method is performed by forming a first mask layer over a substrate and a second mask layer over the first mask layer. The second mask layer is patterned to form cut regions. A mandrel is formed over the first mask layer and the cut regions, and the first mask layer is etched using the mandrel form a patterned first mask. The substrate is etched according to the patterned first mask and the cut regions to form trenches in the substrate, and the trenches are filled with conductive metal to form conductive lines.
    Type: Grant
    Filed: November 9, 2015
    Date of Patent: July 18, 2017
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chia-Ying Lee, Jyu-Horng Shieh
  • Patent number: 9690187
    Abstract: Methods for selecting the best measurement sites for OPC model calibration are disclosed. Embodiments include selecting a predetermined number, n, of structures representing an IC design layout eligible for SEM measurement; specifying an image parameter space of image parameters for the n structures; optimizing a redundancy in the image parameter space of measurement sites for the n structures; and calibrating an OPC model for the IC design layout based on the optimized redundancy.
    Type: Grant
    Filed: April 3, 2015
    Date of Patent: June 27, 2017
    Assignee: GLOBALFOUNDRIES INC.
    Inventor: Francois Weisbuch
  • Patent number: 9672316
    Abstract: Integrated circuits are manufactured using a direct write lithography step to at least partially form at least one layer within the integrated circuit. The performance characteristics of an at least partially formed integrated circuit are measured and then the layout design to be applied with a direct write lithography step is varied in dependence upon those performance characteristics. Accordingly, the performance of an individual integrated circuit, wafer of integrated circuits or batch of wafers may be altered.
    Type: Grant
    Filed: July 17, 2013
    Date of Patent: June 6, 2017
    Assignee: ARM Limited
    Inventor: Gregory Munson Yeric
  • Patent number: 9646373
    Abstract: A method for counterfeit IC detection includes: providing a computer, an optical and an X-ray imager; optically imaging a package of one or more ICs; pattern matching the package image to identify an IC type; selecting one or more reference images from a reference library; X-ray imaging one or more ICs; performing in any order: comparing an internal lead frame structure of the one or more ICs to images from the reference library to determine a first numerical indicator; and determining a composition of the lead frame of the one or more ICs and to a corresponding composition from the reference library to determine a second numerical indicator; calculating an indication of authenticity based on the first numerical indicator and the second numerical indicator; and accepting or rejecting the one or more ICs based on the indication of authenticity. A system for counterfeit IC detection is also described.
    Type: Grant
    Filed: September 17, 2014
    Date of Patent: May 9, 2017
    Assignee: IEC Electronics Corp.
    Inventors: Achilleas Tziazas, Mark Northrup, Daniel F. Martinelli
  • Patent number: 9640480
    Abstract: A MOS device includes first, second, third, and fourth interconnects. The first interconnect extends on a first track in a first direction. The first interconnect is configured in a metal layer. The second interconnect extends on the first track in the first direction. The second interconnect is configured in the metal layer. The third interconnect extends on a second track in the first direction. The third interconnect is configured in the metal layer. The second track is parallel to the first track. The third interconnect is coupled to the second interconnect. The second and third interconnects are configured to provide a first signal. The fourth interconnect extends on the second track in the first direction. The fourth interconnect is configured in the metal layer. The fourth interconnect is coupled to the first interconnect. The first and fourth interconnects are configured to provide a second signal different than the first signal.
    Type: Grant
    Filed: May 27, 2015
    Date of Patent: May 2, 2017
    Assignee: QUALCOMM Incorporated
    Inventors: Mukul Gupta, Xiangdong Chen, Ohsang Kwon
  • Patent number: 9626906
    Abstract: Disclosed is an organic light emitting display in which a sensing period during which the source voltage of the driving TFT is raised toward a data voltage applied to a gate electrode of the driving TFT in order to compensate a change in mobility of the driving TFT, a first gate signal is maintained at an ON level and a second gate signal is maintained at an OFF level, and the first and second gate signals are maintained at an OFF level in a light emission period following the sensing period; and a first falling time of the first gate signal and a second falling time of the second gate signal, which indicate a period of time required to change from the ON level to the OFF level, are set to be longer than a predetermined reference value, respectively.
    Type: Grant
    Filed: December 2, 2014
    Date of Patent: April 18, 2017
    Assignee: LG DISPLAY CO., LTD.
    Inventors: Dongik Kim, Kiwon Son
  • Patent number: 9612530
    Abstract: A method and system for fracturing or mask data preparation are presented in which a set of shots is determined for a multi-beam charged particle beam writer. The edge slope of a pattern formed by the set of shots is calculated. An edge of the pattern which has an edge slope below a target level is identified, and the dosage of a beamlet in a shot in the set of shots is increased to improve the edge slope. The improved edge slope remains less than the target level.
    Type: Grant
    Filed: March 11, 2016
    Date of Patent: April 4, 2017
    Assignee: D2S, Inc.
    Inventors: Akira Fujimura, Kazuyuki Hagiwara, Stephen F. Meier, Ingo Bork
  • Patent number: 9599575
    Abstract: A system for generating calibration information usable for wafer inspection, the system including: (I) a displacement analysis module, configured to: (a) calculate a displacement for each target out of multiple targets selected in multiple scanned frames which are included in a scanned area of the wafer, the calculating based on a correlation of: (i) an image associated with the respective target which was obtained during a scanning of the wafer, and (ii) design data corresponding to the image; and (b) determining a displacement for each of the multiple scanned frames, the determining based on the displacements calculated for multiple targets in the respective scanned frame; and (II) a subsequent processing module, configured to generate calibration information including the displacements determined for the multiple scanned frames, and a target database that includes target image and location information of each target of a group of database targets.
    Type: Grant
    Filed: February 7, 2012
    Date of Patent: March 21, 2017
    Assignee: Applied Materials Israel, Ltd.
    Inventors: Zvi Goren, Nir Ben-David Dodzin
  • Patent number: 9582629
    Abstract: At least one method disclosed herein involves creating an overall pattern layout for an integrated circuit that is to be manufactured using a self-aligned double patterning (SADP) process, forming a first metal feature having a first width on a first track of a metal layer using the SADP process, forming a second metal feature having a second width on a second track of the metal layer. The second track is adjacent to the first track. The method also includes forming an electrical connection between the first metal feature and the second metal feature to provide an effectively single metal pattern having a third width that is the sum of the first and second widths, rendering the first and second features decomposable using the SADP process; and decomposing the overall pattern layout with the first and second metal features into a mandrel mask pattern and a block mask pattern.
    Type: Grant
    Filed: April 4, 2014
    Date of Patent: February 28, 2017
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Lei Yuan, Li Yang, Jongwook Kye
  • Patent number: 9569578
    Abstract: A computer implemented method of mask decomposition and optimization for directed self assembly (DSA) which includes: inputting design information of an integrated circuit that is to be patterned using a DSA process; mapping the design information into a tree graph comprising nodes and edges; searching the tree graph to identify a longest path through the tree graph; identifying a branch comprising an edge on the tree graph not on the longest path and stemming from one of the nodes on the longest path; outputting the one node on the longest path that connects to the branch as a hot spot; and modifying a photomask by removing the branch from the photomask; wherein the method is performed by one or more computing devices.
    Type: Grant
    Filed: December 14, 2015
    Date of Patent: February 14, 2017
    Assignee: International Business Machines Corporation
    Inventors: Kafai Lai, Rasit O. Topaloglu
  • Patent number: 9558545
    Abstract: Systems and methods for predicting and controlling pattern quality data (e.g., critical dimension and/or pattern defectivity) in patterned wafers using patterned wafer geometry (PWG) measurements are disclosed. Correlations between PWG measurements and pattern quality data measurements may be established, and the established correlations may be utilized to provide pattern quality data predictions for a given wafer based on geometry measurements obtained for the give wafer. The predictions produced may be provided to a lithography tool, which may utilize the predictions to correct focus and/or title errors that may occur during the lithography process.
    Type: Grant
    Filed: June 4, 2015
    Date of Patent: January 31, 2017
    Assignee: KLA-Tencor Corporation
    Inventors: Pradeep Vukkadala, Sathish Veeraraghavan, Soham Dey, Jaydeep Sinha
  • Patent number: 9514262
    Abstract: A programmable analog tile integrated circuit is configured over a standardized bus by communicating tile configuration information from a first integrated circuit tile, through a second integrated circuit tile, to a third integrated circuit tile. Each of the three integrated circuit tiles is part of an integrated circuit. The standardized bus is formed when the tiles are placed adjacent one another. Data bus and control signal conductors of the adjacent tiles line up and interconnect such that each signal conductor is electrically connected to every tile. Tile configuration information may be written to a selected register identified by an address in any selected one of the tiles using the data bus and control lines, regardless of the relative physical locations of the tile sending and the tile receiving the information. Thus, tile configuration information may pass from one tile to another tile, through any number of intermediate tiles.
    Type: Grant
    Filed: March 27, 2015
    Date of Patent: December 6, 2016
    Assignee: Active-Semi, Inc.
    Inventors: Steven Huynh, Matthew A. Grant, Gary M. Hurtz, David J. Kunst, Trey A. Roessig
  • Patent number: 9489479
    Abstract: A computer-implemented method for obtaining values of one or more design variables of one or more design rules for a pattern transfer process comprising a lithographic projection apparatus, the method comprising: simultaneously optimizing one or more design variables of the pattern transfer process and the one or more design variables of the one or more design rules. The optimizing comprises evaluating a cost function that measures a metric characteristic of the pattern transfer process, the cost function being a function of one or more design variables of the pattern transfer process and one or more design variables of the one or more design rules.
    Type: Grant
    Filed: April 16, 2013
    Date of Patent: November 8, 2016
    Assignee: ASML NETHERLANDS B.V.
    Inventor: Xiaofeng Liu
  • Patent number: 9443055
    Abstract: Methods for retargeting a circuit design layout for a multiple patterning lithography process and for fabricating a semiconductor device are provided. In an exemplary embodiment, a computer-executed method for retargeting a circuit design layout for a multiple patterning lithography process is provided. The method includes decomposing a circuit design layout file to produce decomposed layout files in a computer. Each decomposed layout file is associated with a respective mask for use in the multiple patterning lithography process. The method includes preparing retargeted layout files in the computer by retargeting selected decomposed layout files based on photolithography limitations specific to each selected decomposed layout file to produce retargeted layout files. Also, the method includes determining in the computer that a combination of layout files includes a spacing conflict.
    Type: Grant
    Filed: April 29, 2015
    Date of Patent: September 13, 2016
    Assignee: GLOBALFOUNDRIES, INC.
    Inventors: Ayman Hamouda, Chidam Kallingal, Norman Chen
  • Patent number: 9405185
    Abstract: A method of manufacturing a photomask includes forming a mask pattern with a critical mask feature on a photomask. Shape information which is descriptive for an outline of the critical mask feature is obtained from the photomask. The shape information contains position information identifying the positions of landmarks on the outline relative to each other. The landmarks may indicate local curvature extrema, points of inflexion, sharp bends in the curvature and/or local curvature-change maxima in the outline of the mask feature, respectively. The shape information may enable a shape metrology which is not completely based on rectangular approximations of mask features.
    Type: Grant
    Filed: April 7, 2014
    Date of Patent: August 2, 2016
    Assignee: Advanced Mask Technology Center GmbH & Co. KG
    Inventors: Clemens Utzny, Markus Bender, Christian Buergel, Albrecht Ullrich
  • Patent number: 9400857
    Abstract: A method for mask data preparation (MDP) is disclosed, in which a set of shots is determined that will form a pattern on a reticle, where the determination includes calculating the pattern that will be formed on a substrate using an optical lithographic process with a reticle formed using the set of shots. A method for optical proximity correction (OPC) or MDP is also disclosed, in which a preliminary set of charged particle beam shots is generated using a preliminary mask model, and then the shots are modified by calculating both a reticle pattern using a final mask model, and a resulting substrate pattern. A method for OPC is also disclosed, in which an ideal pattern for a photomask is calculated from a desired substrate pattern, where the model used in the calculation includes only optical lithography effects and/or substrate processing effects.
    Type: Grant
    Filed: April 15, 2013
    Date of Patent: July 26, 2016
    Assignee: D2S, Inc.
    Inventors: Akira Fujimura, Anatoly Aadamov, Eldar Khaliullin, Ingo Bork
  • Patent number: 9372955
    Abstract: Methods and systems for implementing repetitive track patterns for electronic designs are disclosed. The method determines a track pattern within a period and repeats the track pattern for a number of times to form repetitive track patterns. Compliance with photomask designation design rules and track pattern design rules by both the track pattern and the repetitive track patterns is maintained by adding one or more intermediate tracks. A track may be added or removed from the track pattern or replaced by another track associated with a different width by using one or more intermediate tracks. The method may validate a period and replace an invalid period with a valid period. During the identification of the tracks in a track pattern for constructing repetitive track patterns, the method also forward predicts a predetermined number of tracks or predicts one or more tracks for a predetermined distance.
    Type: Grant
    Filed: May 30, 2014
    Date of Patent: June 21, 2016
    Assignee: Cadence Design Systems, Inc.
    Inventors: Yinnie Lee, Jeffrey Markham, Roland Ruehl, Karun Sharma
  • Patent number: 9298870
    Abstract: Methods and computer program products for designing topographic patterns for directing the formation of self-assembled domains at specified locations on substrates. The methods include generating mathematical models that operate on mathematical descriptions of the number and locations of cylindrical self-assembled domains in a mathematical description of a guiding pattern.
    Type: Grant
    Filed: May 16, 2012
    Date of Patent: March 29, 2016
    Assignee: International Business Machines Corporation
    Inventors: Joy Cheng, Kafai Lai, Chi-Chun Liu, Jed W. Pitera, Charles T. Rettner
  • Patent number: 9292627
    Abstract: The present invention provides a method for compensating infidelities of a process that transfers a pattern to a layer of an integrated circuit, by minimizing, with respect to a photomask pattern, a cost function that quantifies the deviation between designed and simulated values of circuit parameters of the pattern formed on a semiconductor wafer.
    Type: Grant
    Filed: October 28, 2013
    Date of Patent: March 22, 2016
    Assignee: Cadence Design Systems, Inc.
    Inventors: Dipankar Pramanik, Michiel Victor Paul Kruger, Roy V. Prasad, Abdurrahman Sezginer
  • Patent number: 9235676
    Abstract: Some embodiments of the present disclosure provide an integrated circuit (IC) design method. The method includes (1) receiving a first layout comprising stripe patterns with a first separation and a first width; (2) receiving a second layout comprising stripe patterns with a second width narrower than the first separation, each stripe on the second layout is configured to situate between two adjacent stripes on the first layout when overlaying the first layout and the second layout; (3) performing a separation check by identifying a spacing between a stripe on the second layout and one of the two adjacent stripes on the first layout; and (4) adjusting the spacing between the stripe on the second layout and one of the two adjacent stripes on the first layout when the separation check determining the spacing is greater than a predetermined value.
    Type: Grant
    Filed: April 25, 2014
    Date of Patent: January 12, 2016
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Chuan-Fang Su, Chih-Chun Hsu, Hsing-Wang Chen, Rung-Shiang Chen, Ching-Juinn Huang
  • Patent number: 9170481
    Abstract: A design layout for a semiconductor chip includes information on shapes desired to be fabricated. Clusters of photolithographic exposure “shots” are generated and subject to a measure of shot density to approximate a mask shape that generates the desired fabricated shapes when exposed during wafer fabrication. A simulation is run on the clusters of shots to estimate the resulting fabrication shapes that the clusters of shots create. The clusters of shots are modified to align the estimated fabrication shapes more closely with desired fabrication shapes. The process of simulating and modifying the shots is iterative, repeating until the estimated fabrication shapes are within a desired error difference of the planned fabrication shape.
    Type: Grant
    Filed: March 14, 2014
    Date of Patent: October 27, 2015
    Assignee: Synopsys, Inc.
    Inventors: Michael Lawrence Rieger, Thomas Christopher Cecil, Benjamin David Painter
  • Patent number: 9158876
    Abstract: In one embodiment, a computer-implemented method includes accessing mask input data. The mask input data includes a mathematical representation of a mask in a mask representation space, where the mask is configured to create an integrated circuit microprocessor. A set of values is obtained based on a derivative of the mask input data. The set of values is optimized, by a computer processor, in a derivative domain to obtain optimized mask data. The optimized mask data is transformed into the mask representation space to obtain printable mask output data.
    Type: Grant
    Filed: November 26, 2013
    Date of Patent: October 13, 2015
    Assignee: International Business Machines Corporation
    Inventors: Stefan Apostol, Paul Hurley, Radu-Christian Ionescu
  • Patent number: 9134254
    Abstract: Systems and methods for determining a position of output of an inspection system in design data space are provided. One method includes merging more than one feature in design data for a wafer into a single feature that has a periphery that encompasses all of the features that are merged. The method also includes storing information for the single feature without the design data for the features that are merged. The information includes a position of the single feature in design data space. The method further includes aligning output of an inspection system for the wafer to the information for the single feature such that positions of the output in the design data space can be determined based on the position of the single feature in the design data space.
    Type: Grant
    Filed: March 14, 2013
    Date of Patent: September 15, 2015
    Assignee: KLA-Tencor Corp.
    Inventor: Vijayakumar Ramachandran
  • Patent number: 9034542
    Abstract: In a method for fracturing or mask data preparation or mask process correction for charged particle beam lithography, a plurality of shots are determined that will form a pattern on a surface, where shots are determined so as to reduce sensitivity of the resulting pattern to changes in beam blur (?f). In some embodiments, the sensitivity to changes in ?f is reduced by varying the charged particle surface dosage for a portion of the pattern. Methods for forming patterns on a surface, and for manufacturing an integrated circuit are also disclosed, in which pattern sensitivity to changes in ?f is reduced.
    Type: Grant
    Filed: April 21, 2014
    Date of Patent: May 19, 2015
    Assignee: D2S, Inc.
    Inventors: Akira Fujimura, Ingo Bork
  • Patent number: 9032342
    Abstract: A method of patterning a plurality of layers of a work piece in a series of writing cycles in one or a plurality of write machines, the workpiece being deviced to have a number of N layers and layers of the workpiece having one or a plurality of boundary condition(s) for pattern position, the method comprising the steps of: determining the boundary conditions of layers 1 to N, calculating deviations due to the boundary conditions and calculating a compensation for the deviation of the first transformation added with the assigned part of the deviation due to the boundary conditions.
    Type: Grant
    Filed: February 28, 2011
    Date of Patent: May 12, 2015
    Assignee: Mycronic AB
    Inventors: Mikael Wahlsten, Per-Erik Gustafsson
  • Patent number: 9026956
    Abstract: Some embodiments of the present disclosure relate to a method to simulate patterning of a layout. The method comprises simulating formation of a layout pattern under a first lithography condition. The first lithography condition comprises a set of parameters, wherein a value of each parameter is defined by a corresponding process model. The method further comprises randomly varying the value of each parameter of the first lithography condition within a range of values defined by the corresponding process model of the parameter, to create a second lithography condition. Formation of a layout pattern is then re-simulated under the second lithography condition. Random variation of the value of each parameter is repeated to create additional lithography conditions. And, each lithography condition is re-simulated until the value of each parameter has been substantially varied across a range of its respective process model.
    Type: Grant
    Filed: October 11, 2013
    Date of Patent: May 5, 2015
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chia-Cheng Chang, Wei-Kuan Yu, Tsai-Ming Huang, Chin-Min Huang, Cherng-Shyan Tsay, Chien Wen Lai, Hua-Tai Lin, Shih-Ming Chang
  • Patent number: 9026955
    Abstract: The present disclosure relates to a method of integrated chip (IC) design pattern correction that reduces pattern correction cycle time by separately correcting main feature shapes and dummy shapes of the IC design, and an associated apparatus. In some embodiments, the method is performed by forming an IC design having a plurality of main feature shapes. A plurality of dummy shapes are added to the IC design to improve a process window of the IC design. The plurality of main feature shapes are corrected using a first pattern correction process. One or more of the plurality of dummy shapes are subsequently corrected using a second pattern correction process separate from the first pattern correction process. By separately correcting dummy shapes and main feature shapes, the dummy shapes can be subjected to a different pattern correction process having lower time/resource demands, thereby reducing the pattern correction cycle time.
    Type: Grant
    Filed: October 11, 2013
    Date of Patent: May 5, 2015
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Hung-Chun Wang, Ming-Hui Chih, Ping-Chieh Wu, Chun-Hung Wu, Feng-Ju Chang, Cheng-Kun Tsai, Wen-Chun Huang, Ru-Gun Liu
  • Patent number: 9026958
    Abstract: Computer-implemented method, system and computer program product for double patterning technology (DPT) odd loops visualization within an integrated circuit design layout are disclosed. The method, system and computer program product comprise mapping all violations of the integrated circuit design layout to a graph. The method, system and computer programming product also includes partitioning the graph into a plurality of sub-graphs. Each of the plurality of sub-graphs includes multiple edges and multiple nodes. The method, system and computer product further include detecting all possible odd loops in each of the plurality of sub-graphs; and visualizing all of the odd loops in at least one of the plurality of sub-graphs.
    Type: Grant
    Filed: March 11, 2013
    Date of Patent: May 5, 2015
    Assignee: Cadence Design Systems, Inc.
    Inventors: Sanjib Ghosh, Harindranath Parameswaran, Henry Yu
  • Patent number: 9021405
    Abstract: A plurality of gate electrode patterns to be laid out in parallel are alternately set as first patterns to be formed in a first exposure step of double patterning and as second patterns to be formed in a second exposure step. Subsequently, a circuit that includes transistor pairs each formed by connecting one of the first patterns and one of the second patterns in parallel is laid out. This reduces the risk of variations in characteristics of transistors caused by double patterning.
    Type: Grant
    Filed: June 12, 2012
    Date of Patent: April 28, 2015
    Assignee: Fujitsu Semiconductor Limited
    Inventors: Takanori Hiramoto, Toshio Hino, Tsuyoshi Sakata, Yutaka Mizuno, Katsuya Ogata