Abstract: Various aspects of the present disclosed technology relate to techniques for classifying layout patterns. First, a set of density feature vectors for a set of layout regions in the layout design are extracted using a set of rings. Each component of a density feature vector in the set of density feature vectors corresponds to a ring in the set of rings. The set of rings do not overlap with each other and cover a whole area of a circle when being placed together. Next, a machine learning-based clustering process is performed to separate layout features in the set of layout regions into clusters of layout features based on the set of density feature vectors. Each of the clusters of layout features may be further divided into subclusters based on one or more properties.

Abstract: A first device includes a rectangular substrate having a first width and a first length and a first pattern of electrical interface nodes at first, second and third sides with a first set of electrical interface nodes at the fourth side. A second device includes a second rectangular substrate having a second width equal to the first width, a second length and a median line extending in the direction of the second width. A second pattern of electrical interface nodes for the second device includes two unmorphed replicas of the first pattern arranged mutually rotated 180° on opposite sides of the median line as well as two second sets of electrical interface nodes formed by two smaller morphed replicas of the first set of electrical interface nodes arranged mutually rotated 180° on opposite sides of said median line.

Abstract: Various embodiments provide for routing a net of a circuit design using rule-based routing blockage extension, which may be part of electronic design automation (EDA). In particular, some embodiments route a net of a circuit design by determining a dimension extension value based on a design rule of the circuit design and applying the dimension extension value to at least one existing routing blockage.

Abstract: Methods of constructing a process model for simulating a characteristic of a product of lithography from patterns produced under different processing conditions. The methods use a deviation between the variation of the simulated characteristic and the variation of the measured characteristic to adjust a parameter of the process model.

Abstract: Predictive multi-stage modelling for complex semiconductor device manufacturing process control is provided. In one aspect, a method of predictive multi-stage modelling for controlling a complex semiconductor device manufacturing process includes: collecting geometrical data from metrology measurements made at select stages of the manufacturing process; and making an outcome probability prediction at each of the select stages using a multiplicative kernel Gaussian process, wherein the outcome probability prediction is a function of a current stage and all prior stages. Machine-learning models can be trained for each of the select stages of the manufacturing process using the multiplicative kernel Gaussian process. The machine-learning models can be used to provide probabilistic predictions for a final outcome in real-time for production wafers. The probabilistic predictions can then be used to select production wafers for rework, sort, scrap or disposition.

Abstract: The present invention refers to a method and an apparatus for determining positions of a plurality of pixels to be introduced into a substrate of a photolithographic mask by use of a laser system, wherein the pixels serve to at least partly correct one or more errors of the photolithographic mask. The method comprises the steps: (a) obtaining error data associated with the one or more errors; (b) obtaining first parameters of an illumination system, the first parameters determining an illumination of the photolithographic mask of the illumination system when processing a wafer by illuminating with the illumination system using the photolithographic mask; and (c) determining the positions of the plurality of pixels based on the error data and the first parameters.

Abstract: The present disclosure provides a method and a system for generating photomask patterns. The system obtains a design layout image, and generates a hotspot image corresponding to the design layout image based on a hotspot detection model. The system generates two photomask patterns based on the hotspot image. The at least two photomask patterns are transferred onto a semiconductor substrate.

Abstract: A system (including a processor and memory with computer program code) configured to execute a method which includes generating a layout diagram including: generating first and second active area patterns on opposite sides of (and having long axes parallel to) a first symmetry axis; generating non-overlapping first, second and third conductive patterns (having long axes perpendicular to the first symmetry axis) which overlap the first and second active area patterns; centering the first conductive pattern between the second and third conductive patterns; generating a first cut-pattern for, and which overlaps, central regions of the second and third conductive patterns; centering the first cut-pattern relative to the first symmetry axis; generating a fourth conductive pattern over an area bounded by the first cut-pattern; and expanding the fourth conductive pattern to substantially overlap a portion of the first conductive pattern and a portion of the second or third conductive patterns.

Abstract: A method of evaluating a focus control of an extreme ultraviolet (EUV) lithography apparatus includes preparing a wafer exposed by using the EUV lithography apparatus. The wafer includes test patterns formed of a photoresist and having circular islands or holes prepared by multiple exposures of EUV at different foci of exposure. The method further includes measuring a roughness parameter of the test patterns and estimating a function representing a dependence of the roughness parameter on the focus. A best focus is estimated based on an extremum of the function. Exposure wafers are then exposed to EUV with the best focus. The exposure wafers include the test patterns. The roughness parameter for the test patterns on the exposure wafers obtained by exposing the exposure wafers at the best focus is periodically measured. An abnormality in focus is then determined based on the measured roughness parameter and the function.

Abstract: Disclosed is a method of measuring a focus parameter relating to formation of a structure using a lithographic process, and associated metrology device. The method comprises obtaining measurement data relating to a cross-polarized measurement of said structure; and determining a value for said focus parameter based on the measurement data.

Abstract: A method of generating a plurality of photomasks includes generating a circuit graph. The circuit graph comprises a plurality of vertices and a plurality of edges. Each of the plurality of vertices is representative of one of a plurality of conductive lines. The plurality of edges are representative of a spacing between the conductive lines less than an acceptable minimum distance. Kn+1 graph comprising a first set of vertices selected from the plurality of vertices connected in series by a first set of edges selected from the plurality of edges and having at least one non-series edge connection between a first vertex and a second vertex selected from the first set of vertices is reduced by merging a third vertex into a fourth vertex selected from the first set of the plurality of vertices. An n-pattern conflict check is performed and the photomasks generated based on the result.

Abstract: A method is presented for layout decomposition including creating a first graph representative of an integrated circuit layout to be multiple-patterned, when a computer is invoked to decompose the layout, and decomposing each of a first subset of a multitude of sub-graphs into at least three sets when a valid coloring solution is returned for the layout. The multitude of sub-graphs is created from the first graph by dividing the first graph. The method further includes approximately decomposing each of the first subset into at least three sets using a hybrid evolutionary algorithm when the hybrid evolutionary algorithm does not return a valid coloring solution for the layout, and forming a colored graph representative of the layout by merging the at least three sets to generate one of at least three colors for each one of a multitude of vertices of the first graph.

Abstract: Disclosed is a method of generating a physical unclonable function (PUF) by causing unpredictable partial process failure for a semiconductor process. In a designing process, a second mask pattern may be printed by distorting a size and/or shape of at least one mask window included in a designed first mask pattern, without violating semiconductor design rules. A PUF may be generated using a photomask including the printed second mask pattern for photolithography.

Abstract: A system for stochastic reticle defect dispositioning is disclosed. The system includes a controller including one or more processors and memory. The one or more processors configured to acquire product metrology data of a product reticle. The one or more processors configured to perform one or more stochastic simulations based on the product metrology data to generate one or more simulated product samples including the pattern of elements. The one or more processors configured to generate a product model of the product reticle modeling the printing process of the pattern of elements by the product reticle. The one or more processors configured to identify at least one of a care area of the product reticle which is susceptible to printing stochastic defects on product samples, or a care area on the one or more simulated product samples which is susceptible to printed stochastic defects based on the product model.

Abstract: A technique relates to correcting an area of overlap between two films created by sequential shadow mask evaporations. At least one process is performed of: correcting design features in an original layout to generate a corrected layout using a software tool, such that the corrected layout modifies shapes of the design features and correcting the design features in the original layout to generate the corrected layout using a lithographic tool, such that the corrected layout modifies the shapes of the design features. The modified shapes of the design features are patterned at locations on a wafer according to the corrected layout using the lithographic tool. A first film is deposited by an initial shadow mask evaporation and a second film by a subsequent shadow mask evaporation to produce corrected junctions at the locations on the wafer, such that the first film and the second film have an overlap.

Abstract: An integrated circuit (IC) method is provided. The method includes building a mask model to simulate an aerial mask image of a mask, and a compound lithography computational (CLC) model to simulate a wafer pattern; calibrating the mask model using a measured aerial mask image of the mask; calibrating the CLC model using measured wafer data and the calibrated mask model; performing an optical proximity correction (OPC) process to a mask pattern using the calibrated CLC model, thereby generating a corrected mask pattern for mask fabrication. Alternatively, the method includes measuring a mask image of a mask optically projected on a wafer with an instrument; calibrating a mask model using the measured mask image; calibrating a CLC model using measured wafer data and the calibrated mask model; and performing an OPC process to a mask pattern using the calibrated CLC model, thereby generating a corrected mask pattern for mask fabrication.

Abstract: A physical verification tool for debugging ESD ground path resistance violations in ESD protection circuits. The ESD ground path is modeled and partitioned into component path structures (polygons) that are disposed in associated design layers. A total ESD ground path resistance is then calculated and compared with a maximum allowable resistance value defined by an ESD protection rule. When the ESD ground path is non-compliant, a resistance contribution ratio is determined for each polygon and/or for each layer, for example, by applying nodal analysis to the ESD ground path model. Resistance contribution ratios are then calculated for each polygon and/or for each layer, and most-problematic polygons and/or layers are identified by way of having the highest resistance contribution ratio values. A report (e.g., a table or graphical visualization) is then generated that prioritizes or emphasizes (e.g., by way of a bolder contrast or brighter color) the most-problematic layer and/or polygon.

Abstract: The present disclosure relates to a method of data preparation. The method, in some embodiments, performs a first data preparation process using a data preparation element. The first data preparation process modifies a plurality of shapes of an integrated chip (IC) design that comprises a graphical representation of a layout used to fabricate an integrated chip. A plurality of additional shapes are added to the IC design using an additional shape insertion element. The plurality of additional shapes are separated from the plurality of shapes by one or more non-zero distances. A second data preparation process is performed using the data preparation element, after performing the first data preparation process. The second data preparation process modifies the plurality of additional shapes.

Abstract: According to an aspect of this disclosure, a computer-implemented method of offsetting boundary curves includes providing a plurality of inputs for an identified boundary set, developing an offset distance, and creating an offset boundary curve for each boundary. The method of offsetting boundary curves further includes determining intersection points of each of the offset boundary curves, assigning a node to each of the intersection points, and determining sections between intersection points for each offset curve. Still further this method includes determining a minimum distance between sections, wherein when the sections are nearer one another than the minimum distance the sections are determined to belong to the same node and combining the offset boundary curves to define a set of offset boundary curves.

Abstract: A standard cell design system is provided. The standard cell design system includes at least one processor configured to implement: a control engine that determines planar parameters and vertical parameters of a target standard cell, a three-dimensional structure generating engine that generates a three-dimensional structure of the target standard cell based on the planar parameters and the vertical parameters, an extraction engine that extracts a standard cell model of the target standard cell from the three-dimensional structure, an assessment engine that performs a plurality of assessment operations based on the standard cell model, and an auto-optimizing engine that adjusts, based on a machine learning algorithm, the planar parameters and the vertical parameters based on results of the plurality of assessment operations.

Abstract: Methods of forming contacts for vertical-transport field-effect transistors and structures for a vertical-transport field-effect transistor and contact. An interlayer dielectric layer is deposited over a gate stack, and a first opening is formed in the interlayer dielectric layer and penetrates through the gate stack to cut the gate stack into a first section and a second section. A dielectric pillar is formed in the first opening and is arranged between the first section of the gate stack and the second section of the gate stack. Second and third openings are formed in the interlayer dielectric layer that penetrate to the gate stack and that are divided by the dielectric pillar. A first contact in the second opening is coupled with the first section of the gate stack, and a second contact in the third opening is coupled with the second section of the gate stack.

Abstract: System and methods for parasitic extraction of a layer of an integrated circuit are disclosed. In one example, geometric data for a conducting layer of an integrated circuit can be decomposed into homogeneous portions and nonhomogeneous portions. A shape analysis algorithm can be used to generate a shape descriptor including nodes within the nonhomogeneous portions. Parasitic values can be assigned to segments connecting the nodes of the shape descriptor. A circuit representation of the conducting layer can be generated based on the shape descriptor and the assigned parasitic values.

Abstract: A method for generating semiconductor device model parameters includes receiving semiconductor device performance data of statistical instances of semiconductor devices, for a plurality of coordinates in a process space with dimensions of process-dependent device parameters Model parameters are extracted to produce individual model instances, each corresponding to the respective statistical instances for the coordinates in the process space. Statistics of the extracted model parameters are modeled by processing the individual model instances to determine, for each coordinate in the process space, moments describing non-normal marginal distributions of the extracted model parameters and correlations between the extracted model parameters. Semiconductor device model parameters are generated for use in simulating a circuit using the determined moments and the determined correlations, for a selected coordinate in the process space.

Abstract: A method of generating a routing result to manufacture an integrated circuit using self-aligned double patterning includes generating an initial routing result that indicates a location and length of connections between components, and generating an initial constraint graph with trim shapes indicating gaps in the connections being represented as nodes and with arcs indicating relative position constraints between a pair of the nodes. The method also includes subdividing the initial constraint graph into two or more subgraphs, determining a final position of each of the nodes in the two or more subgraphs, and generating a routed design with the trim shapes having the final position of corresponding ones of the nodes relative to the connections and with extents filling in spaces between one or more of the trim shapes and associated connections. The routed design is provided for manufacture of the integrated circuit.

Abstract: A standard cell for a semiconductor device includes a plurality of features for performing the functionality of the standard cell. The standard cell further includes a first sensitivity region adjacent to a first edge of the standard cell. The standard cell further includes anchor nodes linked to corresponding features of the plurality of features, wherein a number of anchor nodes linked to each feature of the corresponding features is based on a position of an end of each feature of the corresponding features relative to the first sensitivity region.

Abstract: A method for generating semiconductor device model parameters includes receiving semiconductor device performance data of statistical instances of semiconductor devices, for a plurality of areal trapped charge densities Model parameters are extracted to produce individual model instances, each corresponding to the respective statistical instances for the areal trapped charge densities. Statistics of the extracted model parameters are modeled by processing the individual model instances to determine, for each areal trapped charge density, moments describing non-normal marginal distributions of the extracted model parameters and correlations between the extracted model parameters. Semiconductor device model parameters are generated for use in simulating a circuit using the determined moments and the determined correlations, for a selected areal trapped charge density.

Abstract: A method includes receiving a first list including a plurality of first curves defining a first boundary set and a second list including a plurality of second curves defining a second boundary set. The first and second curves are indicative of features in an integrated circuit based on parametric values. The method includes determining intersections between pairs of curves from the first and the second lists, assigning a node to each intersection point of a pair of curves, and determining curve sections between the intersection points for each intersected curve. The method includes determining a successor of each curve section, determining boundaries formed by the curve sections, performing the Boolean operation between the boundaries to obtain the one or more features in the integrated circuit from the two or more boundaries, and generating a layout of the integrated circuit including the features for manufacturing a mask for reproducing the features.

Abstract: Various examples of a technique for performing optical proximity correction and for forming a photomask are provided herein. In some examples, a layout is received that includes a shape to be formed on a photomask. A plurality of target lithographic contours are determined for the shape that includes a first target contour for a first set of process conditions and a second target contour that is different from the first target contour for a second set of process conditions. A lithographic simulation of the layout is performed to produce a first simulated contour at the first set of process conditions and a second simulated contour at the second set of process conditions. A modification to the layout is determined based on edge placement errors between the first simulated contour and the first target contour and between the second simulated contour and the second target contour.

Abstract: This disclosure describes methods and systems for building a spatial model to predict performance of processing chamber, and using the spatial model to converge faster to a desired process during the process development phase. Specifically, the method obtains virtual metrology (VM) data from sensors of the chamber and on-board metrology (OBM) data from devices on the wafers; obtains in-line metrology data from precision scanning electron microscope (SEM); and also obtains an empirical process model for a given process. The empirical process model is calibrated by using the in-line metrology data as reference. A predictive model is built by refining the empirical process model by a machine-learning engine that receives customized metrology data and outputs one or more spatial maps of the wafer for one or more dimensions of interest across the wafer without physically processing any further wafers, i.e. by performing spatial digital design of experiment (Spatial DoE).

Abstract: A two-dimensional representation of a polygon is converted to a parametric representation. A smoothing filter is applied to the parametric representation to produce corner rounding. In some embodiments, a polygon layout plus a model that specifies how much corner rounding should be applied are taken as inputs. The desired amount of rounding to the corners in the input polygons is applied and this produces a new polygon layout with corners that are properly rounded as its output. The process can be implemented so that it does not induce any pattern-size dependent bias. It also can be designed so that it does not induce line-end pullbacks. However, this feature can be turned off if line-end pullbacks are deemed appropriate for the specific application.

Abstract: A method including receiving a parametrized curve indicative of a feature in an integrated circuit is provided. The method includes selecting a first parameter value associated with a first point in the parametrized curve, determining a pre-selected number of derivative values in a Taylor series for the parametrized curve at the first point, and determining a second parameter value for a second point in the parametrized curve based on the pre-selected number of derivative values.

Abstract: The invention relates to a method and a device for generating a reference image in the characterization of a mask for microlithography, wherein the mask comprises a plurality of structures and wherein the reference image is generated by simulation of the imaging of said mask, said imaging being effected by a given optical system, both using a rigorous simulation and using a Kirchhoff simulation, wherein the method comprises the following steps: assigning each structure of said plurality of structures either to a first category or to a second category, calculating a plurality of first partial spectra for structures of the first category with implementation of rigorous simulations, calculating a second partial spectrum for structures of the second category with implementation of a Kirchhoff simulation, generating a hybrid spectrum on the basis of the first partial spectra and the second partial spectrum, and generating the reference image with implementation of an optical forward propagation of said hybrid spec

Abstract: A method of generating a plurality of photomasks includes generating a circuit graph. The circuit graph comprises a plurality of vertices and a plurality of edges. Each of the plurality of vertices is representative of one of a plurality of conductive lines. The plurality of edges are representative of a spacing between the conductive lines less than an acceptable minimum distance. Kn+1 graph comprising a first set of vertices selected from the plurality of vertices connected in series by a first set of edges selected from the plurality of edges and having at least one non-series edge connection between a first vertex and a second vertex selected from the first set of vertices is reduced by merging a third vertex into a fourth vertex selected from the first set of the plurality of vertices. An n-pattern conflict check is performed and the photomasks generated based on the result.

Abstract: A method for reducing an effect of flare produced by a lithographic apparatus for imaging a design layout onto a substrate is described. A flare map in an exposure field of the lithographic apparatus is simulated by mathematically combining a density map of the design layout at the exposure field with a point spread function (PSF), wherein system-specific effects on the flare map may be incorporated in the simulation. Location-dependent flare corrections for the design layout are calculated by using the determined flare map, thereby reducing the effect of flare.

Abstract: Source beam optimization (SBO) methods are disclosed herein for enhancing lithography printability. An exemplary method includes receiving an integrated circuit (IC) design layout and performing an SBO process using the IC design layout to generate a mask shot map and an illumination source map. The SBO process uses an SBO model that collectively simulates a mask making process using the mask shot map and a wafer making process using the illumination source map. A mask can be fabricated using the mask shot map, and a wafer can be fabricated using the illumination source map (and, in some implementations, using the mask fabricated using the mask shot map). The wafer includes a final wafer pattern that corresponds with a target wafer pattern defined by the IC design layout. The SBO methods disclosed herein can significantly reduce (or eliminate) variances between the final wafer pattern and the target wafer pattern.

Abstract: Disclosed is a method of measuring a target, an associated substrate, a metrology apparatus and a lithographic apparatus. In one arrangement the target comprises a layered structure. The layered structure has a first target structure in a first layer and a second target structure in a second layer. The method comprises illuminating the target with measurement radiation. Scattered radiation formed by interference between plural predetermined diffraction orders is detected. The predetermined diffraction orders are generated by diffraction of the measurement radiation from the first target structure and are subsequently diffracted from the second target structure. A characteristic of the lithographic process is calculated using the detected scattered radiation formed by the interference between the predetermined diffraction orders.

Abstract: Systems and methods are disclosed for storing dynamic layer content in a design file. A design file is received having design data corresponding to a plurality of process layers. A geometric operation formula is also received. A processor generates a polygon having dynamic layer content that is formed by applying the geometric operation formula on two or more of the plurality of process layers. The updated design file is stored, the design file now having a polygon having dynamic layer content.

Abstract: A method to improve a lithographic process for imaging a portion of a design layout onto a substrate using a lithographic projection apparatus, the method including: computing a multi-variable cost function of a plurality of design variables that are characteristics of the lithographic process, and reconfiguring the characteristics of the lithographic process by adjusting the design variables until a predefined termination condition is satisfied. The multi-variable cost function may be a function of one or more pattern shift errors. Reconfiguration of the characteristics may be under one or more constraints on the one or more pattern shift errors.

Abstract: According to one embodiment of the present invention, a computer-implemented method for validating a design includes generating, using the computer, a first graph representative of the design, when the computer is invoked to validate the design, and decompose, using the computer, the first graph into at least three sets using a hybrid evolutionary algorithm to form a colored graph.

Abstract: A method of generating an ECO-layout of an ECO base cell includes: generating first and second active area patterns and arranging them on opposite sides of a first axis; generating non-overlapping first, second and third conductive patterns and arranging each of them so as to correspondingly overlap the first and second active area patterns; locating the first conductive pattern between the second and third conductive patterns; generating a first cut-pattern which overlaps corresponding central regions of the second, and third conductive patterns; aligning the first cut-pattern relative to the first axis; generating a fourth conductive pattern; locating the fourth conductive pattern over an area bounded by the first cut-pattern; and expanding the fourth conductive pattern to occupy an area which substantially overlaps a first segment of the first conductive pattern and a first segment of one of the second and third conductive patterns, thereby resulting in the ECO-layout.

Abstract: Methods for designing and fabricating a current mirror. A first layout is received for a first back-end-of-line (BEOL) stack that is coupled with an emitter of a bipolar junction transistor in a current mirror that has a first current ratio. A second layout for a second back-end-of-line (BEOL) stack, which differs from the first BEOL stack, is determined such that, when the second BEOL stack is coupled with the emitter of the bipolar junction transistor, the first current ratio is changed to a second current ratio. The change from the first current ratio to the second current ratio, which is based on the change from the first layout for the first BEOL stack to the second layout for the second BEOL stack, is accomplished without changing a front-end-of-line (FEOL) layout of the bipolar junction transistor.

Abstract: A method of devising a target arrangement, and associated target and reticle. The target includes a plurality of gratings, each grating having a plurality of substructures. The method includes: defining a target area; locating the substructures within the target area so as to form the gratings; and locating assist features at the periphery of the gratings, the assist features being configured to reduce measured intensity peaks at the periphery of the gratings. The method may include an optimization process including modelling a resultant image obtained by inspection of the target using a metrology process; and evaluating whether the target arrangement is optimized for detection using a metrology process.

Abstract: A method includes operations below. A layout of a circuit is converted to a first conflict graph. A first vertex and a second vertex in the first conflict graph are adjusted based on first data indicating a color patterns assignment for the circuit, in order to generate a second conflict graph, in which the first vertex indicates a first pattern in the layout, and the second vertex indicates a second pattern in the layout. According to the second conflict graph, a first color pattern is assigned to both of the first pattern and the second pattern, or the first color pattern is assigned to the first pattern and a second color pattern is assigned to the second pattern, in order to generate second data for fabricating the circuit.

Abstract: Integrated circuits are manufactured using a direct write lithography step to at least partially form at least one layer within the integrated circuit. The performance characteristics of an at least partially formed integrated circuit are measured and then the layout design to be applied with a direct write lithography step is varied in dependence upon those performance characteristics. Accordingly, the performance of an individual integrated circuit, wafer of integrated circuits or batch of wafers may be altered.

Abstract: A method is disclosed that includes the operation below. Vertices in a conflict graph are sorted into a first clique and a second clique, in which the conflict graph corresponds to a layout of a circuit. A first vertex of the vertices is merged with a second vertex of the vertices, to generate a reduced graph, in which the first clique excludes the second vertex, and the second clique excludes the first vertex. A first color pattern of a plurality of color patterns is assigned to a first pattern, corresponding to the first vertex, and a second pattern, corresponding to the second vertex, in the layout according to the reduced graph.

Abstract: A method for rasterizing a mask layout includes driving an image converter to obtain a raster image of the mask layout. The raster image is obtained by providing a pattern from the mask layout on a grid, obtaining grid points surrounding an edge of the pattern, constructing a path on the pattern which extends from the edge toward adjacent edges of the pattern, and allocating a raster value to each of the grid points. The raster value corresponds to an overlap area between a pixel, having a center located on one of the grid points, and the pattern having a boundary limited by the path.

Abstract: A method and an apparatus for determining near field images for optical lithography include receiving a thin mask image indicative of a photomask feature, in which the thin mask image is determined without considering a mask topography effect associated with the photomask feature, and determining a near field image from the thin mask image by a processor using an artificial neural network (ANN), in which the ANN uses the thin mask image as input. The apparatus includes a processor and a memory coupled to the processor. The memory configured to store instructions executed by the processor to perform the method.

Abstract: A method, an apparatus, and a non-transitory computer readable medium for full chip mask pattern generation include: generating, by a processor, an initial mask image from target polygons, performing, by the processor, a global image based full chip optimization of the initial mask image to generate new mask pattern polygons, wherein the global image based full chip optimization co-optimizes main feature polygons and SRAF image pixels, determining performance index information based on the global image based full chip optimization, wherein the performance index information comprises data for assisting a global polygon optimization, generating a mask based on the global polygon optimization of the new mask pattern polygons using the performance index information, and generating optimized mask patterns based on a localized polygon optimization of the mask.

Abstract: In some embodiments, in a method performed by at least one processor, spaces among a plurality of layout segments is analyzed by the at least one processor to determine at least one first-type conflicted edge according to a first predetermined length. Spaces among the plurality of layout segments is analyzed by the at least one processor to determine a plurality of potential conflicted edges according to a second predetermined length different from the first predetermined length. At least one second-type conflicted edge is determined by the at least one processor according to the plurality of potential conflicted edges. If at least one odd-vertex loop is formed in the plurality of layout segments is checked by the at least one processor according to the at least one first-type conflicted edge and the at least one second-type conflicted edge to determine if a violation occurs in the plurality of layout segments.

Abstract: A method of designing a layout of an integrated circuit (IC) includes placing a first cell in the layout, placing a second cell in the layout adjacent to the first cell at a first boundary between the first and second cells, and generating a plurality of commands executable by a processor to form a semiconductor device based on the layout. The first cell includes a first pattern and a second pattern. The first and second patterns are adjacent to the first boundary, the first and second patterns have different colors, and a first boundary space between the first pattern and the first boundary is different from a second boundary space between the second pattern and the first boundary.