Abstract: Vectorization of program code by way of a method that includes obtaining program code to be compiled. The program code has a loop that includes a control-flow having divergent branch conditions. The method includes compiling the program code to produce compiled code. The compiling includes performing compile-time analysis of the loop based on an assumption of dynamic uniformity, and determining from the analysis a vectorizable access pattern of the loop. The compiling also includes vectorizing the loop as part of the compiling the program code, including compiling the loop. The vectorizing includes providing run-time checks in the compiled code. The run-time checks are configured for checking for dynamically uniform conditions for vector processing at run-time to control program execution flow based on a result of the checking. The method also includes outputting the compiled code for execution.

Abstract: The present application discloses a warp execution method used for SPs of an SM of a GPU and an associated GPU. The SPs share a scratchpad memory, and the warp execution method includes: when the predetermined time point for warp-loading is reached, checking a first indicator to obtain a size of a space with the status of blank in the scratchpad memory, to determining whether to load the warp, wherein the first indicator is used to indicate a starting position of a space with the status of data-in-use and an ending position of the space with the status of blank; and when the predetermined time point for computing is reached, checking a second indicator and a third indicator to obtain a size of a space with the status of data-not-in-use in the scratchpad memory, to determining whether to compute the warp.

Abstract: A collection of code fragments loaded in an interactive development platform for running on a first processor can be received. A candidate fragment in the collection of code fragments can be determined for migration to a second processor based on characterizing the collection of code fragments. Based on a location of the candidate fragment in the collection of code fragments, a spot can be identified in the collection of code fragments to inject a code for saving program context. The code for saving program context can be injected in the identified spot. Responsive to the code for saving program context having run on the first processor and based on a criterion, the program context can be migrated to the second processor.

Abstract: A system and method that provides fine grained parallelization to serial pipelines and serial data processing with one or more threading and synchronization models whereby data object or packet processing is orchestrated by a parser identifying the various layers of the input data object and dispatching worker threads to perform the processing of the various layers of the data object, wherein the worker threads may execute in parallel.

Abstract: A method according to an embodiment includes receiving, via a processor, (1) first data representing one or more coding requirements defined by a user, (2) an indication of one or more target computer programming languages, and (3) a first machine-readable code. The method also includes modifying the first machine-readable code to generate a second machine-readable code based, at least in part, on the first data. The method also includes generating target machine-readable code based, at least in part, on the one or more target computer programming languages and the second machine-readable code.

Abstract: A non-ontological hierarchy for language models is based on established psycholinguistic and neuro-linguistic evidences. By using non-ontological hierarchies, a more natural understanding of user's inputs and intents improve toward a better potential for producing intelligent responses in a conversational situation.

Abstract: Methods, systems, and apparatus for propagating reduced-precision on computation graphs are described. In one aspect, a method includes receiving data specifying a directed graph that includes operators for a program. The operators include first operators that each represent a numerical operation performed on numerical values having a first level of precision and second operators that each represent a numerical operation performed on numerical values having a second level of precision. One or more downstream operators are identified for a first operator. A determination is made whether each downstream operator represents a numerical operation that is performed on input values having the second level of precision. Whenever each downstream operator represents a numerical operation that is performed on input values having the second level of precision, a precision of numerical values output by the operation represented by the first operator is adjusted to the second level of precision.

Abstract: Methods, systems and computer program products for implementing a mere-parser are disclosed. Text data is processed to generate one or more parse items. A boundary based attribute associated with one of the parse items is identified, and the identified mere attribute is associated with one or more of the remaining parse items that is not blocked from associated with the boundary based attribute.

Abstract: Systems and methods described herein may relate to providing a dynamically configurable circuitry able to be programed using a microsector granularity. Furthermore, selective partial reconfiguration operations may be performed use write operations to write a new configuration over existing configurations to selectively reprogram a portion of programmable logic. A quasi-delay insensitive (QDI) shift register and/or control circuitry receiving data and commands from an access register disposed between portions of programmable logic may enable at least some of the operations described.

Abstract: Provided are a system for managing a calculation processing graph of an artificial neural network and a method of managing a calculation processing graph by using the system. A system for managing a calculation processing graph of an artificial neural network run by a plurality of heterogeneous resources includes: a task manager configured to allocate the plurality of heterogeneous resources to a first subgraph and a second subgraph that are to be run, the first subgraph and the second subgraph being included in the calculation processing graph; a first compiler configured to compile the first subgraph to be executable on a first resource among the plurality of heterogeneous resources; and a second compiler configured to compile the second subgraph to be executable on a second resource among the plurality of heterogeneous resources, wherein the first subgraph and the second subgraph are respectively managed through separate calculation paths.

Abstract: Techniques for specifying and implementing a software application targeted for execution on a multiprocessor array (MPA). The MPA may include a plurality of processing elements, supporting memory, and a high bandwidth interconnection network (IN), communicatively coupling the plurality of processing elements and supporting memory. In some embodiments, software code may specify one or more cell definitions that include: program instructions executable to perform a function and one or more language constructs. The software code may further instantiate first, second, and third cell instances, each of which is an instantiation of one of the one or more cell definitions, where the instantiation includes configuration of the one or more language constructs such that: the first and second cell instances communicate via respective communication ports and the first and second cell instances are included in the third cell instance.

Abstract: A job decomposition processing method for distributed computing, which comprises: analyzing a source program to be run by program static analysis to determine a function call graph contained in the source program; determining feature information of functions contained in the source program by program dynamics analysis or/and a program intelligent decomposition algorithm, wherein the feature information of the functions is used to characterize relevant information when each function is being running; decomposing the source program based on the feature information of the functions, a function relationship and available resource information of a computing platform to form an execution recommendation for each function on the computing platform, i.e., which hardware resources are used for computing each function; finally inserting a modifier in the source program and starting computation on the computing platform.

Abstract: An embodiment of a semiconductor package apparatus may include technology to manage one or more virtual graphic processor units, and co-schedule the one or more virtual graphic processor units based on both general processor instructions and graphics processor instructions. Other embodiments are disclosed and claimed.

Abstract: Systems, methods, and apparatuses are described that enable IC architectures to enable a single anchor to connect to and accept a variety of chiplets at any port by way of a programming model that enables the anchor or chiplet to dynamically adapt to configurations, requirements, or aspects of any coupled component and provide an interface for the coupled components.

Abstract: A method, system, and computer-readable medium for binary translation cause a binary translator to combine raw binary code and compiler-produced metadata associated with a compiled program module. The binary translator is caused to further reconcile, using the compiler-produced metadata, original compiler-produced control flow information with how lower-level machine instructions comprise a control flow in the raw binary code, and original compiler-produced aliasing information with how lower-level machine instructions access the memory locations described by the aliasing information according to predetermined criteria. The binary translator further caused to prevent, copy propagation of values in temporary variables for decimal computations beyond offsets in the machine instructions where the temporary variables are killed.

Abstract: A method for constructing behavioral software signatures. The method includes: embedding execution traces of a set of software in a vector space, an execution trace of a software agent including at least one event and being representative of the execution of the software, the embedding representing an event of the execution trace by a vector encoding a context for occurrence of the event; partitioning the vectors associated with the software of the set to generate a data group representative of a behavior, a behavioral label being associated with the data group; associating a behavioral label with a vector, which is representative of the data group to which the vector belongs, and associating a trace of behavioral labels with a trace of vectors, the trace of labels being representative of execution of a software agent, and extracting in the trace of labels at least one behavioral signature associated with the software.

Abstract: Mechanisms for resource isolation allow tenants executing in a multi-tenant software container to be isolated in order to prevent resource starvation by one or more of the tenants. Mechanisms for dependency isolation may be utilized to prevent one tenant executing in a multi-tenant software container from using another tenant in the same container in a manner that requires co-tenancy. Mechanisms for security isolation may be utilized to prevent one tenant in a multi-tenant software container from accessing protected data or functionality of another tenant. Mechanisms for fault isolation may be utilized to prevent tenants in a multi-tenant software container from causing faults or other types of errors that affect other tenants executing in the same software container.

Abstract: Disclosed in a processor chip configured to perform neural network processing. The processor chip includes a memory, a first processor configured to perform neural network processing on a data stored in the memory, a second processor and a third processor, and the second processor is configured to transmit a control signal to the first processor and the third processor to cause the first processor and the third processor to perform an operation.

Abstract: Disclosed are a method and a system for optimizing data storage of query statistics of a graph database. The method includes: periodically scanning, on storage servers in which partitions are located, all edges in the partitions; determining, according to all the edges in the partitions, partitions to which start points and end points belong, and calculating outgoing-edge correlation and incoming-edge correlation between partitions; calculating relevancies between partitions through a preset correlation matrix weight according to the outgoing-edge correlation and the incoming-edge correlation between partitions; and storing partitions with high relevancies on a same storage server.

Abstract: In one example, a method performed by a compiler comprises: receiving a dataflow graph of a neural network, the neural network comprising a neural network operator; receiving information of computation resources and memory resources of a neural network hardware accelerator intended to execute the neural network operator; determining, based on the dataflow graph, iterations of an operation on elements of a tensor included in the neural network operator; determining, based on the information, a mapping between the elements of the tensor to addresses in the portion of the local memory, and a number of the iterations of the operation to be included in a batch, wherein the number of the iterations in the batch are to be executed in parallel by the neural network hardware accelerator; and generating a schedule of execution of the batches of the iterations of the operations.

Abstract: In a system providing transactional memory support, a transaction nesting depth testing instruction is provided for triggering processing circuitry 4 to set at least one status value to one of a plurality of states depending on a transaction nesting depth indicative of a number of executed transaction start instructions of a given thread for which the corresponding transaction remains unaborted and uncommitted, the plurality of states including a first state selected when the transaction nesting depth is 1 and at least one further state selected when the transaction nesting depth is greater than or less than 1. The supported ISA enables the setting of the at least one status value and a conditional branch conditional on the at least one status value being in the first state to be performed in response to a single transaction nesting depth testing instruction and a single conditional branch instruction.

Abstract: The present disclosure relates to systems, methods, and computer readable media for diagnosing and mitigating memory impact events, such as memory leaks, high memory usage, or other memory issues causing a host node from performing as expected on a cloud computing system. The systems described herein involve receiving locally generated memory usage data from a plurality of host nodes. The systems described herein may aggregate the memory usage data and determine a memory impact diagnosis based on a subset of the aggregated memory usage data. The systems described herein may further apply a mitigation model for mitigating the memory impact event. The systems described herein provide an end-to-end solution for diagnosing and mitigating a variety of memory issues using a dynamic and scalable system that reduces a negative impact of memory leaks and other memory issues on a cloud computing system.

Abstract: An optimum combination of a loop unrolling number and a circuit parallel number in a high-level synthesis is determined. A circuit synthesis information generation unit sets, as parameter candidates, a plurality of combinations of a loop unrolling number and a circuit parallel number to generate circuit synthesis information indicating a synthesis circuit obtained by high-level synthesis processing for each of the combinations. An optimum parameter determination unit calculates, for each piece of the generated circuit synthesis information, an estimation processing performance related to the synthesis circuit indicated by the circuit synthesis information, and determines an optimum combination of the loop unrolling number and the circuit parallel number based on the circuit synthesis information based on which a maximum estimation processing performance is obtained.

Abstract: Systems, methods, and apparatuses relating to a matrix operations accelerator are described.

Abstract: Systems, methods, and software are disclosed herein for facilitating deployment of a decision service for sharing application data among multiple isolated applications executing on one or more application platforms. In an implementation, a method of deploying applications conforming to a platform schema for facilitating sharing of the application data among isolated applications executing on one or more application platforms is described. The method includes receiving a request to submit a third party application to an application deployment system, identifying a validation manifest associated with a platform schema responsive to receiving the request, and automatically verifying that the third party application to conforms to the platform schema by performing a set of pre-defined validation checks. The request identifies the platform schema and platform capability information associated with the third party application. The validation manifest includes the set of pre-defined validation checks.

Abstract: Parallelized computation by a real-time transaction scoring system that incorporates global behavior profiling of transacting entities includes dividing a global profile computing component of a transaction scoring model of a real-time behavioral analytics transaction scoring system into a plurality of global profile component instances. The transaction scoring model uses a plurality of global profile variables, each of the plurality of global profile component instances using its own global profile partition that contains the estimate of global profile variables and being configured for update by a dedicated thread of execution of the real-time transaction scoring system, each dedicated thread being configured for receiving and scoring a portion of input transactions.

Abstract: Systems and methods for automated systolic array design from a high-level program are disclosed. One implementation of a systolic array design supporting a convolutional neural network includes a two-dimensional array of reconfigurable processing elements arranged in rows and columns. Each processing element has an associated SIMD vector and is connected through a local connection to at least one other processing element. An input feature map buffer having a double buffer is configured to store input feature maps, and an interconnect system is configured to pass data to neighboring processing elements in accordance with a processing element scheduler. A CNN computation is mapped onto the two-dimensional array of reconfigurable processing elements using an automated system configured to determine suitable reconfigurable processing element parameters.

Abstract: System and method of compiling a program having a mixture of host code and device code to enable Profile Guided Optimization (PGO) for device code execution. An exemplary integrated compiler can compile source code programmed to be executed by a host processor (e.g., CPU) and a co-processor (e.g., a GPU) concurrently. The compilation can generate an instrumented executable code which includes: profile instrumentation counters for the device functions; and instructions for the host processor to allocate and initialize device memory for the counters and to retrieve collected profile information from the device memory to generate instrumentation output. The output is fed back to the compiler for compiling the source code a second time to generate optimized executable code for the device functions defined in the source code.

Abstract: Systems and methods are described for extending a live range for a virtual scalar register during compiling of a program, comprising: receiving an intermediate representation (IR) of a source code configured for implementing single-instruction-multiple-thread (SIMT) execution, the IR representing the source code as control flow graph including a plurality of basic blocks (BB); and when a virtual scalar register defined in a first BB of the IR is last used in a second BB of the IR that is a divergent BB, modifying the IR to extend the live range of the virtual scalar register.

Abstract: A system includes processor hardware and memory hardware that stores instructions. The instructions include, in response to receiving a request, determining a request type of the request, retrieving a first set of collected information, and selecting a first set of instructions corresponding to the request type. The instructions include constructing a first result by executing each instruction of the first set of instructions to create the first entry as a nested entry within the first result including data of the first set of collected information identified in the first set of instructions as nested or retrieve first data of the first set of collected information identified by the first instruction and add the first data to the first entry of the first result. The instructions include transforming a display of the operator device to complete a set of fields displayed on the display with corresponding entries of the first result.

Abstract: An apparatus to facilitate asynchronous execution at a processing unit. The apparatus includes one or more processors to detect independent task passes that may be executed out of order in a pipeline of the processing unit, schedule a first set of processing tasks to be executed at a first set of processing elements at the processing unit and schedule a second set of tasks to be executed at a second set of processing elements, wherein execution of the first set of tasks at the first set of processing elements is to be performed simultaneous and in parallel to execution of the second set of tasks at the second set of processing elements.

Abstract: A method and apparatus are disclosed for finding overlong source code segments (e.g., methods) by evaluating input source code segments for a plurality of predetermined code metric values in order to identify candidate source code segments (e.g., non-autogenerated methods) which do not meet a first code metric value and to assess each candidate source code segment against a second code metric value to identify different sets of candidate source code segments (e.g., test methods and normal methods) so that each set of candidate source code segments may be assessed against a tailored set of code length thresholds to identify any overlong source code segment having a code length which meets or exceeds at least two of the tailored set of code length thresholds.

Abstract: A code base is parsed to identify methods encapsulated therein. Thereafter, a call graph is generated based on the parsing using a graph generation technique. The call graph is a directed call graph comprising a plurality of nodes characterizing the identified methods. It can then be determined, based on one or more design patterns used to generate the code base, that at least a portion of the nodes generated call graph are disconnected nodes. At least two of the disconnected nodes are then connected using a stitching algorithm to result in a modified call graph. Data characterizing the modified call graph can then be provided (e.g., displayed in a graphical user interface, stored in a database, loaded into memory, transmitted to a remote computing device, etc.).

Abstract: Verifiable test case workflow is provided by creating a secure database for actions taken regarding a source file that is stored on a first computer; creating a test executable from one or more source files and storing it on the first computer; finalizing the source file for test on a second computer different from the first computer; hashing a test environment related to the source file and the second computer; and in response to determining that a version of the test executable provided to the second computer matches a version of the test executable provided to the secure database: executing the test executable on the second computer; hashing test results from testing the source file on the second computer; and adding the test executable as hashed and the test results as hashed to the secure database to actions already stored in the secure database.

Abstract: An analytics tool includes a network interface and an analytics engine. The network interface receives a request for job analytics of a job. The job comprises uploading a plurality of batches, each of the plurality batches comprising a subset of information of a data table. A network node of a plurality of network nodes uploads a batch of the plurality of batches. The analytics engine configured to determines the plurality of network nodes used to complete the job. The analytics engine retrieves network node data for each of the plurality of network nodes. The analytics engine generates the job analytics by aggregating the network node data for each of the plurality of network nodes.

Abstract: A method for using profiling to obtain application-specific, preferred parameter values for an application is disclosed. First, a parameter for which to obtain an application-specific value is identified. Code is then augmented for application-specific profiling of the parameter. The parameter is profiled and profile data is collected. The profile data is then analyzed to determine the application's preferred parameter value for the profile parameter.

Abstract: A system for fully integrated predictive decision-making and simulation having a high-volume deep web scraper system, a data retrieval engine, a directed computational graph module, and a decision and action path simulation engine.

Abstract: Techniques are provided for an automated method of adding out-of-bound access prevention in GPU kernels executed in a managed environment. In an embodiment, a system of computers compiles a GPU kernel code function that includes one or more array references that are memory address dependent. The system of computers compiles the kernel code function by generating a rewritten GPU kernel code module that includes, within the function signature of the rewritten GPU kernel code module, a respective array size parameter for each array reference of the one or more array references included in the GPU kernel code function. The system of computers further compiles the kernel code function by adding bounding protection instructions to the one or more potential out-of-bound access instructions in the rewritten GPU kernel code module. The potential out-of-bound access instructions comprise instructions that reference each respective array size parameter of the one or more array references.

Abstract: A non-transitory computer-readable recording medium is provided in which a port switching program for causing a computer to execute a process including: transmitting, in response to a mirror switching instruction that specifies a migration source port and a migration destination port, a first mirror switching notification to a virtual switch that has the migration destination port to request a change of mirror setting in the migration destination port; canceling mirror setting for a transmission packet to the migration destination port in the migration source port; and canceling mirror setting for a received packet from the migration destination port in the migration source port in response to a second mirror switching notification from the virtual switch, the second mirror switching notification indicating the change of the mirror setting in the migration destination port is stored.

Abstract: A scheduling method of a system on chip including a multi-core processor includes receiving a schedule-requested task, converting a priority assigned to the schedule-requested task into a linear priority weight, selecting a plurality of candidate cores, to which the schedule-requested task will be assigned, from among cores of the multi-core processor, calculating a preemption compare index indicating a current load state of each of the plurality of candidate cores, comparing the linear priority weight with the preemption compare index of the each of the plurality of candidate cores to generate a comparison result, and assigning the schedule-requested task to one candidate core of the plurality of candidate cores depending on the comparison result.

Abstract: In one example, a processor may receive a first request to process a first task, the first request including a first estimated central processing unit utilization for the first task and a first estimated memory utilization for the first task and receive central processing unit capacities and memory capacities of a plurality of sub-data routers including at least a first sub-data router. The processor may further determine that the first sub-data router has a lowest central processing unit capacity from among the plurality of sub-data routers that is sufficient to accommodate the first estimated central processing unit utilization for the first task and determine that the first sub-data router has a memory capacity that is sufficient to accommodate the first estimated memory utilization for the first task. The processor may then assign the first task to the first sub-data router.

Abstract: With the success of programming models such as OpenCL and CUDA, heterogeneous computing platforms are becoming mainstream. However, these heterogeneous systems are low-level, not composable, and their behavior is often implementation defined even for standardized programming models. In contrast, the method and system embodiments for the heterogeneous parallel primitives (HPP) programming model disclosed herein provide a flexible and composable programming platform that guarantees behavior even in the case of developing high-performance code.

Abstract: A graph database management system includes a computing system in communication with a distributed computing environment comprising a plurality of elements and a database that stores element records associated with corresponding elements of the distributed computing environment. The computing system generates a graph database having a plurality of vertices representing the element records of the distributed computing environment and at least one edge representing a specified relationship between at least one pair of the element records. Thereafter, the computing system may receive a request to view the vertices associated with the at least one pair of element records and their associated edge, and facilitate the display of the vertices and their associated edge on a display in response to the request.

Abstract: An approach is provided for completing a decision logic. For statements in a syntax tree of the decision logic and using a symbolic execution technique, path expression(s) that refer to respective input object(s) are identified. A statement in the decision logic is detected that modifies an attribute value of a path expression included in the path expression(s) and that refers to an input object included in the input object(s). A copy instruction is inserted as a new node in the syntax tree so that the attribute value of the path expression is a copy of the input object. Responsive to inserting the copy instruction, the path expression is prevented from modifying the input object.

Abstract: A processor core receives a request to execute application code including a trigger instruction and an instruction block that reads a row of data values from a data structure and outputs a data value from a function using the row as input. The data structure is divided into multiple portions and the trigger instruction indicates that multiple instances of the instruction block are to be executed concurrently. In response to the request and to identification of the instruction block and trigger instruction, the processor core generates multiple instances of a support block that causes independent repetitive execution of each instance of the instruction block until all rows of the corresponding portion of the data structure are used as input. The processor core assigns instances of the instruction and support blocks to multiple processor cores, and provides each instance of the instruction block with the corresponding portion of the data structure.

Abstract: A system includes a database client, and a distributed database comprising database nodes. The distributed database may receive a database query from the client, determine that the query comprises a range of hash values of a table partition stored by a node of the distributed database, and determine that the range of hash values is not stored by other nodes of the distributed database. Responsive to determining that the range of hash values of the query is stored by the node and not by the other nodes, the database may generate an optimized distributed execution plan that includes the node that stores the range of hash values and excludes the nodes that do not include the range of hash values.

Abstract: An information processing apparatus determines computer resources to be allocated to each task execution entity, based on upper limit value information and processing amount information. The upper limit value information indicates an upper limit value of the total amount of computer resources to be allocated to all task execution entities. The processing amount information indicates an amount of tasks to be processed by each task execution entity.

Abstract: A system and method of storing and analyzing information is disclosed. The system includes a compiler layer to convert user queries to data parallel executable code. The system further includes a library of multithreaded algorithms, processes, and data structures. The system also includes a multithreaded runtime library for implementing compiled code at runtime. The executable code is dynamically loaded on computing elements and contains calls to the library of multithreaded algorithms, processes, and data structures and the multithreaded runtime library.

Abstract: The present invention provides a joint compilation method and system for a heterogeneous hardware architecture. The method comprises steps of: determining, according to calculation characteristics of heterogeneous units in the hardware architecture, a strategy for dividing an overall calculation task graph into a plurality of subtasks, and allocating the plurality of divided subtasks to corresponding heterogeneous unit compilers for compilation to generate corresponding target machine instruction codes; and, linking the generated target machine instruction codes to form a set of machine instruction codes oriented to the heterogeneous hardware architecture. With the joint compilation method and system of the present invention, an executable program body, which can run on a heterogeneous hardware architecture system and be mixed with hardware machine instruction codes of various heterogeneous units at different levels, can be automatically compiled, optimized and generated by activating one compilation.

Abstract: Systems and methods generate code from a source program where the generated code may be compiled and executed on a Graphics Processing Unit (GPU). A parallel loop analysis check may be performed on regions of the source program identified for parallelization. One or more optimizations also may be applied to the source program that convert mathematical operations into a parallel form. The source program may be partitioned into segments for execution on a host and a device. Kernels may be created for the segments to be executed on the device. The size of the kernels may be determined, and memory transfers between the host and device may be optimized.