For A Parallel Or Multiprocessor System Patents (Class 717/149)
  • Patent number: 10311025
    Abstract: A cache management system for managing a plurality of intermediate data includes a processor, and a memory having stored thereon the plurality of intermediate data and instructions that when executed by the processor, cause the processor to perform identifying a new intermediate data to be accessed, loading the intermediate data from the memory in response to identifying the new intermediate data as one of the plurality of intermediate data, and in response to not identifying the new intermediate data as one of the plurality of intermediate data identifying a reusable intermediate data having a longest duplicate generating logic chain that is at least in part the same as a generating logic chain of the new intermediate data, and generating the new intermediate data from the reusable intermediate data and a portion of the generating logic chain of the new intermediate data not in common with the reusable intermediate data.
    Type: Grant
    Filed: January 11, 2017
    Date of Patent: June 4, 2019
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Zhengyu Yang, Jiayin Wang, Thomas David Evans
  • Patent number: 10303522
    Abstract: A system and method for distributed graphics processing unit (GPU) computation are disclosed. A particular embodiment includes: receiving a user task service request from a user node; querying resource availability from a plurality of slave nodes having a plurality of graphics processing units (GPUs) thereon; assigning the user task service request to a plurality of available GPUs based on the resource availability and resource requirements of the user task service request, the assigning including starting a service on a GPU using a distributed processing container and creating a corresponding uniform resource locator (URL); and retaining a list of URLs corresponding to the resources assigned to the user task service request.
    Type: Grant
    Filed: July 1, 2017
    Date of Patent: May 28, 2019
    Assignee: TUSIMPLE
    Inventors: Kai Zhou, Siyuan Liu
  • Patent number: 10284457
    Abstract: A method, an information handling system (IHS), and a virtual link trunking (VLT) system for determining VLT ports to block and unblock in an IHS. The method includes calculating a forwarding table index for a local switch of currently active and inactive switch peers for a VLT port. A pre-determined forwarding table is retrieved from a memory containing a plurality of port blocking and unblocking actions for the switch peers. Current port blocking and unblocking actions are identified in the pre-determined forwarding table corresponding to the forwarding table index. Changes are determined between the previous port blocking and unblocking actions and the current port blocking and unblocking actions. The input/output (I/O) ports are configured for the local switch based on the determined changes in the port blocking and unblocking actions.
    Type: Grant
    Filed: July 12, 2016
    Date of Patent: May 7, 2019
    Assignee: Dell Products, L.P.
    Inventors: Senthil Nathan Muthukaruppan, Shankara Ramamurthy, Pugalendran Rajendran
  • Patent number: 10255115
    Abstract: An apparatus including a processor to: parse comments of multiple task routines to identify I/O parameters; generate a visualization of a DAG to include a visual representation of each task routine, wherein each representation includes a task graph object of the task routine, at least one input data graph object that represents an input to the task routine and that includes a visual indication of at least one characteristic of the input; and at least one output data graph object that represents an output of the task routine and that includes a visual indication of at least one characteristic of the output; in the I/O parameters, identify each dependency between an output of one task routine and an input of another; for each identified dependency, augment the visualization with a dependency marker that visually links the visual representations of each associated pair of task routines; and visually output the visualization.
    Type: Grant
    Filed: February 15, 2018
    Date of Patent: April 9, 2019
    Assignee: SAS INSTITUTE INC.
    Inventors: Henry Gabriel Victor Bequet, Chaowang “Ricky” Zhang
  • Patent number: 10228923
    Abstract: A parallelization compiling method for generating a segmented program from a sequential program, in which multiple macro tasks are included and at least two of the macro tasks have a data dependency relationship with one another, includes determining an existence of invalidation information for invalidating at least a part of the data dependency relationship between the at least two of the plurality of macro tasks before compiling the sequential program into the segmented program, and generating the segmented program by compiling the sequential program into the segmented program with reference to a determination result of the existence of the invalidation information. When the invalidation information is determined to exist, the at least a part of the data dependency relationship is invalidated before the compiling of the sequential program into the segmented program.
    Type: Grant
    Filed: March 29, 2016
    Date of Patent: March 12, 2019
    Assignees: DENSO CORPORATION, WASEDA UNIVERSITY
    Inventors: Yoshihiro Yatou, Noriyuki Suzuki, Kenichi Mineda, Hironori Kasahara, Keiji Kimura, Hiroki Mikami, Dan Umeda
  • Patent number: 10210025
    Abstract: An apparatus including a processor to: parse comments of multiple task routines to identify I/O parameters; generate a visualization of a DAG to include a visual representation of each task routine, wherein each representation includes a task graph object of the task routine, at least one input data graph object that represents an input to the task routine and that includes a visual indication of at least one characteristic of the input; and at least one output data graph object that represents an output of the task routine and that includes a visual indication of at least one characteristic of the output; in the I/O parameters, identify each dependency between an output of one task routine and an input of another; for each identified dependency, augment the visualization with a dependency marker that visually links the visual representations of each associated pair of task routines; and visually output the visualization.
    Type: Grant
    Filed: February 15, 2018
    Date of Patent: February 19, 2019
    Assignee: SAS INSTITUTE INC.
    Inventors: Henry Gabriel Victor Bequet, Chaowang “Ricky” Zhang
  • Patent number: 10169012
    Abstract: An optimizing compiler includes a vector optimization mechanism that optimizes vector operations that are reformatting-resistant, such as source instructions that do not have a corresponding reformatting operation, sink instructions that do not have a corresponding reformatting operation, a source instruction that is a scalar value, a sink instruction that may produce a scalar value, and an internal operation that depends on lanes being in a specified order. The ability to optimize vector instructions that are reformatting-resistant reduces the number of operations to improve the run-time performance of the code.
    Type: Grant
    Filed: November 1, 2017
    Date of Patent: January 1, 2019
    Assignee: International Business Machines Corporation
    Inventors: Michael Karl Gschwind, William J. Schmidt
  • Patent number: 10157466
    Abstract: A method to segment images that contain multiple objects in a nested structure including acquiring an image; defining the multiple objects by layers, each layer corresponding to one region, where a region contains an innermost object and all the objects nested within the innermost object; stacking the layers in an order of the nested structure of the multiple objects, the stack of layers having at least a top layer and a bottom layer; extending each layer with padded nodes; connecting the top layer to a sink and the bottom layer to a source, wherein each intermediate layer between the top layer and the bottom layer are connected only to the adjacent layer by undirected links; and measuring a boundary length for each layer.
    Type: Grant
    Filed: January 23, 2017
    Date of Patent: December 18, 2018
    Assignees: Riverside Research Institute, New York University
    Inventors: Jen-wei Kuo, Jonathan Mamou, Xuan Zhao, Jeffrey A. Ketterling, Orlando Aristizabal, Daniel H. Turnbull, Yao Wang
  • Patent number: 10157055
    Abstract: Methods, systems, apparatuses, and computer program products are provided for transforming asynchronous code into more efficient, logically equivalent asynchronous code; Program code is converted into a first syntax tree. A dependency graph is generated from the first syntax tree with each node of the dependency graph corresponding to a code statement and having an assigned weight. Weighted topological sorting of the dependency graph is performed to generate a sorted dependency graph. A second syntax tree is generated from the sorted dependency graph. In another implementation, the program code is transformed into await-relaxed and/or loop-relaxed program code prior to being transformed into the first syntax tree.
    Type: Grant
    Filed: September 29, 2016
    Date of Patent: December 18, 2018
    Assignee: Microsoft Technology Licensing, LLC
    Inventors: Gal Tamir, Elad Iwanir, Eli Koreh
  • Patent number: 10157086
    Abstract: An apparatus including a processor to: parse comments of multiple task routines to identify I/O parameters; for each task routine, generate a macro including its I/O parameters; transmit the macros to a requesting device to enable it to generate a visualization of a DAG to include visual representations of the task routines; wherein each representation includes a task graph object, an input data graph object representing an input and indicating a characteristic of the input, and an output data graph object representing an output and indicating a characteristic of the output; and wherein the requesting device is to: identify, in the I/O parameters, each dependency between an output and an input of a pair of task routines; augment the visualization, for each identified dependency, with a dependency marker that visually links the visual representations of the pair of task routines; and visually output the visualization.
    Type: Grant
    Filed: February 16, 2018
    Date of Patent: December 18, 2018
    Assignee: SAS INSTITUTE INC.
    Inventors: Henry Gabriel Victor Bequet, Chaowang “Ricky” Zhang
  • Patent number: 10146849
    Abstract: Methods, systems, and apparatus, including computer programs encoded on a computer storage medium, for enhancing search results. In one aspect, a method includes receiving a query. A plurality of search results responsive to the query are identified. The search results are analyzed to determine that at least a first search result is associated with a first answer box topic. The search results are provided along with an answer box precursor for the first answer box topic.
    Type: Grant
    Filed: October 25, 2017
    Date of Patent: December 4, 2018
    Assignee: Google LLC
    Inventors: Tal Cohen, Ziv Bar-Yossef, Igor Tsvetkov, Adi Mano, Oren Naim, Nitsan Oz, Nir Andelman, Pravir Kumar Gupta
  • Patent number: 10067910
    Abstract: A method and system performing a general matrix-matrix multiplication (GEMM) operation using a kernel compiled with optimal maximum register count (MRC). During operation, the system may generate the kernel compiled with optimal MRC. This may involve determining a fastest compiled kernel among a set of compiled kernels by comparing the speeds of the compiled kernels. Each kernel may be compiled with a different MRC value between zero and a predetermined maximum number of registers per thread. The fastest compiled kernel is determined to be the kernel with optimal MRC. The system may receive data representing at least two matrices. The system may select the kernel compiled with optimal MRC, and perform the GEMM operation on the two matrices using the selected kernel. Some embodiments may also perform general matrix-vector multiplication (GEMV), sparse matrix-vector multiplication (SpMV), or k-means clustering operations using kernels compiled with optimal MRC.
    Type: Grant
    Filed: July 1, 2016
    Date of Patent: September 4, 2018
    Assignee: PALO ALTO RESEARCH CENTER INCORPORATED
    Inventor: Rong Zhou
  • Patent number: 10002161
    Abstract: The subject matter disclosed herein provides methods and apparatus, including computer program products for rules-based processing. In one aspect there is provided a method. The method may include, for example, evaluating rules to determine whether to enable or disable one or more actions in a ready set of actions. Moreover, the method may include scheduling the ready set of actions, each of which is scheduled for execution and executed, the execution of each of the ready set of actions using a separate, concurrent thread, the concurrency of the actions controlled using a control mechanism. Related systems, apparatus, methods, and/or articles are also described.
    Type: Grant
    Filed: December 3, 2008
    Date of Patent: June 19, 2018
    Assignee: SAP SE
    Inventors: Sören Balko, Matthias Miltz
  • Patent number: 9898288
    Abstract: A computer-implemented method of executing an instruction sequence with a recursive function call of a plurality of threads within a thread group in a Single-Instruction-Multiple-Threads (SIMT) system is provided. Each thread is provided with a function call counter (FCC), an active mask, an execution mask and a per-thread program counter (PTPC). The instruction sequence with the recursive function call is executed by the threads in the thread group according to a program counter (PC) indicating a target. Upon executing the recursive function call, for each thread, the active mask is set according to the PTPC and the target indicated by the PC, the FCC is determined when entering or returning from the recursive function call, the execution mask is determined according to the FCC and the active mask. It is determined whether an execution result of the recursive function call takes effects according to the execution mask.
    Type: Grant
    Filed: December 29, 2015
    Date of Patent: February 20, 2018
    Assignee: MEDIATEK INC.
    Inventors: Yan-Hong Lu, Jia-Yang Chang, Pao-Hung Kuo, Chia-Chi Chang, Pei-Kuei Tsung
  • Patent number: 9891924
    Abstract: A method for implementing a reduced size register view data structure in a microprocessor. The method includes receiving an incoming instruction sequence using a global front end; grouping the instructions to form instruction blocks; using a plurality of multiplexers to access ports of a scheduling array to store the instruction blocks as a series of chunks.
    Type: Grant
    Filed: March 14, 2014
    Date of Patent: February 13, 2018
    Assignee: Intel Corporation
    Inventor: Mohammad A. Abdallah
  • Patent number: 9886252
    Abstract: An optimizing compiler includes a vector optimization mechanism that optimizes vector operations that are reformatting-resistant, such as source instructions that do not have a corresponding reformatting operation, sink instructions that do not have a corresponding reformatting operation, a source instruction that is a scalar value, a sink instruction that may produce a scalar value, and an internal operation that depends on lanes being in a specified order. The ability to optimize vector instructions that are reformatting-resistant reduces the number of operations to improve the run-time performance of the code.
    Type: Grant
    Filed: August 31, 2015
    Date of Patent: February 6, 2018
    Assignee: International Business Machines Corporation
    Inventors: Michael Karl Gschwind, William J. Schmidt
  • Patent number: 9880821
    Abstract: An optimizing compiler includes a vector optimization mechanism that optimizes vector operations that are reformatting-resistant, such as source instructions that do not have a corresponding reformatting operation, sink instructions that do not have a corresponding reformatting operation, a source instruction that is a scalar value, a sink instruction that may produce a scalar value, and an internal operation that depends on lanes being in a specified order. The ability to optimize vector instructions that are reformatting-resistant reduces the number of operations to improve the run-time performance of the code.
    Type: Grant
    Filed: August 17, 2015
    Date of Patent: January 30, 2018
    Assignee: International Business Machines Corporation
    Inventors: Michael Karl Gschwind, William J. Schmidt
  • Patent number: 9823927
    Abstract: According to some embodiments, the workgroup divisibility requirement may be dispensed with on a selective or permanent basis, i.e. in all cases, particular cases or at particular times and/or under particular conditions. An application programming interface implementation may be allowed to launch workgroups with non-uniform local sizes. Two different local sizes may be used in a case of a one-dimensional workload.
    Type: Grant
    Filed: November 30, 2012
    Date of Patent: November 21, 2017
    Assignee: Intel Corporation
    Inventors: Aaron R. Kunze, Dillon Sharlet, Andrew E. Brownsword
  • Patent number: 9805110
    Abstract: Methods, systems, and apparatus, including computer programs encoded on a computer storage medium, for enhancing search results. In one aspect, a method includes receiving a query. A plurality of search results responsive to the query are identified. The search results are analyzed to determine that at least a first search result is associated with a first answer box topic. The search results are provided along with an answer box precursor for the first answer box topic.
    Type: Grant
    Filed: May 2, 2016
    Date of Patent: October 31, 2017
    Assignee: Google Inc.
    Inventors: Tal Cohen, Ziv Bar-Yossef, Igor Tsvetkov, Adi Mano, Oren Naim, Nitsan Oz, Nir Andelman, Pravir Kumar Gupta
  • Patent number: 9799087
    Abstract: Systems, methods, and computer readable media to improve the development of image processing intensive programs are described. In general, techniques are disclosed to non-intrusively monitor the run-time performance of shader programs on a graphics processing unit (GPU)—that is, to profile shader program execution. More particularly, GPU-based hardware threads may be configured to run in parallel too, and not interfere with, the execution environment of a GPU during shader program execution. When so configured, GPU hardware threads may be used to accurately characterize the run-time behavior of an application program's shader operations.
    Type: Grant
    Filed: September 9, 2013
    Date of Patent: October 24, 2017
    Assignee: Apple Inc.
    Inventors: Sun Tjen Fam, Andrew Sowerby
  • Patent number: 9798587
    Abstract: An embodiment of the invention includes applying a first partition to a plurality of LPs, wherein a particular LP is assigned to a first set of LPs. A second partition is applied to the LPs, wherein the particular LP is assigned to an LP set different from the first set. For both the first and second partitions, lookahead values and transit times are determined for each of the LPs and related links. For the first partition, a first system progression rate is computed using a specified function with the lookahead values and transit times determined for the first partition. For the second partition, a second system progression rate is computed using the specified function with the lookahead values and transit times determined for the second partition. The first and second system progression rates are compared to determine which is the lowest.
    Type: Grant
    Filed: May 13, 2011
    Date of Patent: October 24, 2017
    Assignee: International Business Machines Corporation
    Inventors: Cheng-Hong Li, Alfred J. Park, Eugen Schenfeld
  • Patent number: 9785700
    Abstract: The invention relates to electronic indexing, and more particularly, to the parallelization of indexing. Systems and methods of the invention index data archives by breaking a job into work items and sending the work items to multiple processors that can each determine whether to index data associated with the work item or to create a new work item and have a different processor index the data. This gives the system an internal load-balancing that results in indexing jobs during which no processor stands idle while another processor indexes data of unexpected complexity.
    Type: Grant
    Filed: August 7, 2013
    Date of Patent: October 10, 2017
    Assignee: Nuix Pty Ltd
    Inventors: David Sitsky, Eddie Sheehy
  • Patent number: 9720743
    Abstract: General-purpose distributed data-parallel computing using a high-level language is disclosed. Data parallel portions of a sequential program that is written by a developer in a high-level language are automatically translated into a distributed execution plan. The distributed execution plan is then executed on large compute clusters. Thus, the developer is allowed to write the program using familiar programming constructs in the high level language. Moreover, developers without experience with distributed compute systems are able to take advantage of such systems.
    Type: Grant
    Filed: July 23, 2015
    Date of Patent: August 1, 2017
    Assignee: Microsoft Technology Licensing, LLC
    Inventors: Yuan Yu, Dennis Fetterly, Michael Isard, Ulfar Erlingsson, Mihai Budiu
  • Patent number: 9652286
    Abstract: Embodiments include systems and methods for handling task dependencies in a runtime environment using dependence graphs. For example, a computer-implemented runtime engine includes runtime libraries configured to handle tasks and task dependencies. The task dependencies can be converted into data dependencies. At runtime, as the runtime engine encounters tasks and associated data dependencies, it can add those identified tasks as nodes of a dependence graph, and can add edges between the nodes that correspond to the data dependencies without deadlock. The runtime engine can schedule the tasks for execution according to a topological traversal of the dependence graph in a manner that preserves task dependencies substantially as defined by the source code.
    Type: Grant
    Filed: March 21, 2014
    Date of Patent: May 16, 2017
    Assignee: Oracle International Corporation
    Inventor: Bin Fan
  • Patent number: 9577869
    Abstract: A method, system and program product for balanced workload distribution in a plurality of networked computing nodes. The networked computing nodes may be arranged as a connected graph defining at least one direct neighbor to each networked computing node. The method comprises determining a first workload indicator of the i-th computing node, at a first stage before a new task may be started by the i-th computing node, determining an estimated workload indicator of the i-th computing node, assuming that the new task is performed at a second stage on the i-th computing node, determining estimated workload indicators of each direct neighbor assuming that the new task is performed at the second stage, deciding whether to move the new task to another computing node, and moving the new task to one of the direct neighboring computing nodes of the i-th computing node such that workloads are balanced.
    Type: Grant
    Filed: August 28, 2013
    Date of Patent: February 21, 2017
    Assignee: International Business Machines Corporation
    Inventors: Gianluca Della Corte, Alessandro Donatelli, Antonio M. Sgro
  • Patent number: 9569272
    Abstract: A method and device for digital data processing based on a data flow processing model is suitable for the execution, in a distributed manner on multiple calculation nodes, of multiple data processing operations modelled by directed graphs, where two different processing operations include at least one common calculation node. The device includes an identification processor configured to, from a valued directed multi-graph made up of the union of several distinct processing graphs and divided into several valued directed sub-multi-graphs, called chunks, and whose input and output nodes are buffer memory nodes of the multi-graph, identify a coordination module for each chunk. Furthermore each identified coordination module is configured to synchronize portions of processing operations that are to be executed in the chunk with which the respective coordination module is associated, independently of portions of processing operations that are to be executed in other chunks.
    Type: Grant
    Filed: July 9, 2010
    Date of Patent: February 14, 2017
    Assignee: Commissariat a l'energie atomique et aux alternatives
    Inventor: Yvain Thonnart
  • Patent number: 9552197
    Abstract: A non-transitory computer-readable recording medium stores therein a program for causing an information processing apparatus to execute a process including analyzing a source program with respect to the information processing apparatus that starts hardware prefetching upon detecting an access to a consecutive area on a main storage device and stops the hardware prefetching upon detecting an end of the access to the consecutive area, specifying an array structure in a loop process as a hardware prefetching target, and generating, from the source program, a machine language program in which the array structure is changed so that a second access occurring next to a first access to the array structure refers to an area being consecutive from the area being referred to by the first access.
    Type: Grant
    Filed: August 31, 2015
    Date of Patent: January 24, 2017
    Assignee: FUJITSU LIMITED
    Inventor: Shigeru Kimura
  • Patent number: 9467532
    Abstract: A computing method is provided which includes calling a general purpose graphics processing subroutine for execution of a target program by a client; sending a program code and resource data for execution of the target program to a server by the client; and executing the program code using a general purpose graphics processing unit by the server.
    Type: Grant
    Filed: January 22, 2013
    Date of Patent: October 11, 2016
    Assignee: INDUSTRY-ACADEMIC COOPERATION FOUNDATION, YONSEI UNIVERSITY
    Inventors: Won Woo Ro, Keunsoo Kim, Seung Hun Kim
  • Patent number: 9448778
    Abstract: A computer-implemented method, system, and computer program product for performing object collocation on a computer system are provided. The method includes analyzing a sequence of computer instructions for object allocations and uses of the allocated objects. The method further includes creating an allocation interference graph of object allocation nodes with edges indicating pairs of allocations to be omitted from collocation. The method also includes coloring the allocation interference graph such that adjacent nodes are assigned different colors, and creating an object allocation at a program point prior to allocations of a selected color from the allocation interference graph. The method additionally includes storing an address associated with the created object allocation in a collocation pointer, and replacing a use of each allocation of the selected color with a use of the collocation pointer to collocate multiple objects.
    Type: Grant
    Filed: July 30, 2014
    Date of Patent: September 20, 2016
    Assignee: International Business Machines Corporation
    Inventors: Patrick Doyle, Pramod Ramarao, Vijay Sundaresan
  • Patent number: 9436589
    Abstract: An analysis system may perform network analysis on data gathered from an executing application. The analysis system may identify relationships between code elements and use tracer data to quantify and classify various code elements. In some cases, the analysis system may operate with only data gathered while tracing an application, while other cases may combine static analysis data with tracing data. The network analysis may identify groups of related code elements through cluster analysis, as well as identify bottlenecks from one to many and many to one relationships. The analysis system may generate visualizations showing the interconnections or relationships within the executing code, along with highlighted elements that may be limiting performance.
    Type: Grant
    Filed: March 29, 2013
    Date of Patent: September 6, 2016
    Assignee: Microsoft Technology Licensing, LLC
    Inventors: Ying Li, Alexander G. Gounares, Charles D. Garrett, Russell S. Krajec
  • Patent number: 9424103
    Abstract: A method for operating a lock in a computing system having plural processing units and running under multiple runtime environments is provided. When a requester thread attempts to acquire the lock while the lock is held by a holder thread, determine whether the holder thread is suspendable or non-suspendable. If the holder thread is non-suspendable, put the requester thread in a spin state regardless of whether the requester thread is suspendable or non-suspendable; otherwise determines whether the requester thread is suspendable or non-suspendable unless the requester thread quits acquiring the lock. If the requester thread is non-suspendable, arrange the requester thread to attempt acquiring the lock again; otherwise add the requester thread to a wait queue as an additional suspended thread. Suspended threads stored in the wait queue are allowable to be resumed later for lock acquisition. The method is applicable for the computing system with a multicore processor.
    Type: Grant
    Filed: September 30, 2014
    Date of Patent: August 23, 2016
    Assignee: Hong Kong Applied Science and Technology Research Institute Company Limited
    Inventors: Yi Al, Lin Xu, Jianchao Lu, Shaohua Zhang
  • Patent number: 9395957
    Abstract: A high level programming language provides an agile communication operator that generates a segmented computational space based on a resource map for distributing the computational space across compute nodes. The agile communication operator decomposes the computational space into segments, causes the segments to be assigned to compute nodes, and allows the user to centrally manage and automate movement of the segments between the compute nodes. The segment movement may be managed using either a full global-view representation or a local-global-view representation of the segments.
    Type: Grant
    Filed: December 22, 2010
    Date of Patent: July 19, 2016
    Assignee: Microsoft Technology Licensing, LLC
    Inventor: Paul F. Ringseth
  • Patent number: 9367291
    Abstract: An apparatus and method for generating vector code are provided. The apparatus and method generate vector code using scalar-type kernel code, without user's changing a code type or modifying data layout, thereby enhancing user's convenience of use and retaining the portability of OpenCL.
    Type: Grant
    Filed: March 28, 2014
    Date of Patent: June 14, 2016
    Assignees: Samsung Electronics Co., Ltd., Seoul National University R&DB Foundation
    Inventors: Jin-Seok Lee, Seong-Gun Kim, Dong-Hoon Yoo, Seok-Joong Hwang, Jeongho Nah, Jaejin Lee, Jun Lee
  • Patent number: 9354629
    Abstract: Example methods and apparatus to configure a process control system using an electronic description language (EDL) script are disclosed. A disclosed example method comprises loading a first script representative of a process plant, the first script comprising an interpretive system-level script structured in accordance with an electronic description language, and compiling the first script to form a second script, the second script structured in accordance with a vendor-specific configuration language associated with a particular process control system for the process plant.
    Type: Grant
    Filed: February 19, 2009
    Date of Patent: May 31, 2016
    Assignee: Fisher-Rosemount Systems, Inc.
    Inventors: James Randall Balentine, Gary Keith Law, Mark Nixon
  • Patent number: 9311065
    Abstract: Embodiments relate to data splitting for multi-instantiated objects. An aspect includes receiving a portion of source code for compilation having a dynamic object to split using object size array data splitting. Another aspect includes replacing all memory allocations for the dynamic object with a total size of an object size array and object field arrays including a predetermined padding. Another aspect includes inserting statements in the source code after the memory allocations to populate the object size array with a value of a number of elements of the object size array. Another aspect includes updating a stride for load and store operations using dynamic pointers. Yet another aspect includes modifying field references by adding a distance between the object size array and the object field array to respective address operations.
    Type: Grant
    Filed: June 19, 2014
    Date of Patent: April 12, 2016
    Assignee: International Business Machines Corporation
    Inventors: Shimin Cui, Yan Zhang
  • Patent number: 9292341
    Abstract: Techniques for acceleration of remote procedure calls are disclosed. Such techniques include steps of receiving a content request, the content request including at least one data request for information from a database; analyzing the received content request; and determining whether the analyzed content request includes at least one data request that can be separately executed in parallel with execution of the received content request. In response to a determination that at least one data request that can be separately executed in parallel, initiating the execution of the parallel data request; receiving the requested data in response to that data request; locally storing the received requested data; and providing the stored received requested data in response to execution of the received content request.
    Type: Grant
    Filed: October 16, 2013
    Date of Patent: March 22, 2016
    Assignee: GOOGLE INC.
    Inventors: Noah Fiedel, Jeremy Nelson
  • Patent number: 9286044
    Abstract: Hybrid parallelization strategies for machine learning programs on top of MapReduce are provided. In one embodiment, a method of and computer program product for parallel execution of machine learning programs are provided. Program code is received. The program code contains at least one parallel for statement having a plurality of iterations. A parallel execution plan is determined for the program code. According to the parallel execution plan, the plurality of iterations is partitioned into a plurality of tasks. Each task comprises at least one iteration. The iterations of each task are independent.
    Type: Grant
    Filed: June 27, 2014
    Date of Patent: March 15, 2016
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Matthias Boehm, Douglas Burdick, Berthold Reinwald, Prithviraj Sen, Shirish Tatikonda, Yuanyuan Tian, Shivakumar Vaithyanathan
  • Patent number: 9286196
    Abstract: A method, apparatus and computer program, each for optimizing execution of a computer program is disclosed in which a topology-based control flow analysis of basic blocks of the computer program is performed and a data flow analysis of the instructions within the basic blocks is performed to determine if each instruction of said computer program is uniform or non-uniform (variant or invariant). Subsequently, when the computer program is executed, storage of a copy of a variable dependent on a uniform instruction is suppressed.
    Type: Grant
    Filed: January 8, 2015
    Date of Patent: March 15, 2016
    Assignee: ARM Limited
    Inventors: Jiangning Liu, Zhenqiang Chen
  • Patent number: 9280330
    Abstract: An apparatus and method for executing code are provided. The apparatus includes a memory manager that allocates a stack in memory to store processed data that needs to be retained; a loop generator that divides program code programmed to be processed in parallel into regions based on a barrier function, transforms a region that includes the processed data that needs to be retained in the stack into a first coalescing loop, and transforms a region that uses the processed data stored in the stack into a second coalescing loop such that the transformed program code may be serially processed; and a loop changer that reverses a processing order of the second coalescing loop in comparison to a processing order of the first coalescing loop.
    Type: Grant
    Filed: March 31, 2014
    Date of Patent: March 8, 2016
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Jin-Seok Lee, Seong-Gun Kim, Dong-Hoon Yoo, Seok-Joong Hwang
  • Patent number: 9262141
    Abstract: In one embodiment, a computer-implemented method for concurrently processing at least a portion of a graphical model is provided. The method may include obtaining the graphical model; recognizing a pattern in the graphical model, the pattern suitable for concurrent processing; and employing concurrent processing using multi-thread, multi-core, or multi-processor computing device when executing the pattern in the graphical model.
    Type: Grant
    Filed: September 10, 2007
    Date of Patent: February 16, 2016
    Assignee: The MathWorks, Inc.
    Inventors: Donald Paul Orofino, II, Ramamurthy Mani, Michael James Longfritz
  • Patent number: 9250867
    Abstract: A computer-implemented method for creating a program for a multi-processor system comprising a plurality of interspersed processors and memories. A user may specify or create source code using a programming language. The source code specifies a plurality of tasks and communication of data among the plurality of tasks. However, the source code may not (and preferably is not required to) 1) explicitly specify which physical processor will execute each task and 2) explicitly specify which communication mechanism to use among the plurality of tasks. The method then creates machine language instructions based on the source code, wherein the machine language instructions are designed to execute on the plurality of processors. Creation of the machine language instructions comprises assigning tasks for execution on respective processors and selecting communication mechanisms between the processors based on location of the respective processors and required data communication to satisfy system requirements.
    Type: Grant
    Filed: May 22, 2014
    Date of Patent: February 2, 2016
    Assignee: Coherent Logix, Incorporated
    Inventors: John Mark Beardslee, Michael B. Doerr, Tommy K. Eng
  • Patent number: 9213570
    Abstract: A method for conveying a data packet received from a network to a virtual machine instantiated on a computer system coupled to the network, and a medium and system for carrying out the method, is described. In the method, a guest receive pointer queue of a component executing in the virtual machine is inspected in order to identify a location in a guest receive packet data buffer that is available to receive packet data. Data from the data packet received from the network is copied into the guest receive packet data buffer at the identified location, and a standard receive interrupt is raised in the virtual machine.
    Type: Grant
    Filed: January 29, 2015
    Date of Patent: December 15, 2015
    Assignee: VMware, Inc.
    Inventor: Michael Nelson
  • Patent number: 9207946
    Abstract: An approach is provided in which a distributed runtime environment executes a software application that includes isolated runtime constructs corresponding to an isolated runtime environment. During the execution, the distributed runtime environment identifies isolated runtime constructs included in the software application and selects distributed runtime constructs corresponding to the isolated runtime constructs. In turn, the distributed runtime environment executes the distributed runtime constructs in lieu of executing the isolated runtime constructs.
    Type: Grant
    Filed: August 27, 2013
    Date of Patent: December 8, 2015
    Assignee: International Business Machines Corporation
    Inventor: Douglas Davis
  • Patent number: 9170846
    Abstract: A distributed data-parallel execution (DDPE) system splits a computational problem into a plurality of sub-problems using a branch-and-bound algorithm, designates a synchronous stop time for a “plurality of processors” (for example, a cluster) for each round of execution, processes the search tree by recursively using a branch-and-bound algorithm in multiple rounds (without inter-processor communications), determines if further processing is required based on the processing round state data, and terminates processing on the processors when processing is completed.
    Type: Grant
    Filed: March 29, 2011
    Date of Patent: October 27, 2015
    Inventors: Daniel Delling, Mihai Budiu, Renato F. Werneck
  • Patent number: 9146834
    Abstract: Various arrangements for debugging code are presented. A computer system, such as a web server, may compile code into compiled code. The code may contain one or more subsections, include a first taskflow. A selection of the first taskflow may be received from a remote, developer computer system via a network. The selection of the first taskflow may indicate that the first taskflow is to be debugged. Execution of the first taskflow of the compiled code may occur by the computer system. While the computer system is executing the first taskflow of the compiled code, debugging functionality of the first taskflow may be provided to the developer computer system.
    Type: Grant
    Filed: May 1, 2014
    Date of Patent: September 29, 2015
    Assignee: Oracle International Corporation
    Inventor: John Smiljanic
  • Patent number: 9148669
    Abstract: A method and system for encoding a digital video signal using a plurality of parallel processors. A digital picture is received that is composed of one or more GOPs. The CPU then determines the number of GOPs that need to be encoded and divides them into groups. The number of GOPs in a group may equal the number of parallel processors in the multi-core platform available to encode. The CPU transfers in a single batch to the multi-core platform, a frame of equal rank from each GOP contained in the first group. The multi-core platform encodes the frames in parallel, rearranges the encoded byte stream chunk into normal display order sequence and stores the encoded byte stream. The process may repeat until all the GOPs in the first group have been encoded. Upon completion the multi-core platform outputs the encoded byte stream in normal display order sequence.
    Type: Grant
    Filed: March 10, 2011
    Date of Patent: September 29, 2015
    Assignee: Sony Corporation
    Inventors: Jonathan Huang, Tsaifa Yu
  • Patent number: 9146732
    Abstract: The invention provides a method and system to execute applications on a mobile device. The applications may be compiled on a remote server and sent to the mobile device before execution. The applications may be updated by the remote server without interaction by the mobile device user.
    Type: Grant
    Filed: May 9, 2014
    Date of Patent: September 29, 2015
    Assignee: MFOUNDRY, INC.
    Inventor: Rodney Aiglstorfer
  • Patent number: 9128747
    Abstract: Systems and method for optimizing the performance of software applications are described. Embodiments include computer implemented steps for identifying at least two constituent software components for parallel execution, executing the identified software components, profiling the performance of the one or more software components at an execution time, creating an optimization model with the set of data gathered from profiling the execution of the one or more software components, and marking at least two software components for execution in parallel in a subsequent execution on the basis of the optimization model. In additional embodiments, the optimization model may be reconfigured on the basis of a cost-benefit analysis of parallelization, and the software components involved marked for sequential execution if the resource overhead associated with parallelization exceeds the corresponding resource or throughput benefit.
    Type: Grant
    Filed: June 25, 2012
    Date of Patent: September 8, 2015
    Assignee: Infosys Limited
    Inventor: Prasanna Rajaraman
  • Patent number: 9110872
    Abstract: Genetic sequence data occurring in genome sequences is represented for efficient access of the sequence information in a defined storage scheme. A described replet-sequence matrix data structure allows the compression and efficient access of sequence information. The data structure allows the dynamic change of ontology: the replet-information table can evolve by adding, updating, removing replets, and the set of replets present in the table represent the ontology at the moment. The data structure enables the sequence information to be processed in parallel, and also enables multiple views of the sequence data to exist along with replet specific information.
    Type: Grant
    Filed: October 31, 2003
    Date of Patent: August 18, 2015
    Assignee: International Business Machines Corporation
    Inventor: Jagir Razak Jainul Abdeen Hussan
  • Patent number: 9098709
    Abstract: A method of converting an original application into a cloud-hosted application includes splitting the original application into a plurality of application components along security relevant boundaries, mapping the application components to hosting infrastructure boundaries, and using a mechanism to enforce a privacy policy of a user. The mapping may include assigning each application component to a distinct virtual machine, which acts as a container for its assigned component.
    Type: Grant
    Filed: November 13, 2012
    Date of Patent: August 4, 2015
    Assignee: International Business Machines Corporation
    Inventors: Mihai Christodorescu, Dimitrios Pendarakis, Kapil K. Singh