Compiling Code Patents (Class 717/140)
  • Patent number: 10810065
    Abstract: Disclosed are systems, methods, and non-transitory computer-readable media for a self-learning and self-healing API platform. The API platform receives messages transmitted between computing systems according to an API designed to facilitate communications between the computing systems. The API includes a message sequence and schema for communications between the computing systems. If the API platform detects an occurrence of a modification trigger associated with the API, the API platform determines a modification to be performed to the API. The modification includes a change to the message sequence and schema of the API. The API platform automatically executes the modification, resulting in a revised API. Accordingly, subsequent messages transmitted between the computing systems are transmitted according to the revised API.
    Type: Grant
    Filed: June 3, 2019
    Date of Patent: October 20, 2020
    Assignee: SAP SE
    Inventor: Debashis Banerjee
  • Patent number: 10795653
    Abstract: Examples of the present disclosure provide apparatuses and methods for target architecture determination. An example method comprises receiving an indication of a type of target architecture in a portion of source code and creating compiled code for the type of target architecture based on the indication.
    Type: Grant
    Filed: November 26, 2018
    Date of Patent: October 6, 2020
    Assignee: Micron Technology, Inc.
    Inventor: John D. Leidel
  • Patent number: 10789252
    Abstract: Techniques related to efficient evaluation of aggregate functions are disclosed. Computing device(s) may perform a method for aggregating results of performing a multiplication on a first column and a second column of a database table. A first vector stores a subset of values of the first column. A second vector stores a corresponding subset of values of the second column. When it is determined that the first vector has a lower cardinality than the second vector, a third vector stores at least a first distinct value and a second distinct value of the first vector. A first set of one or more values of the second vector is determined, wherein each value of the first set of one or more values corresponds to the first distinct value in the first vector. A first multiplicand is generated based on performing a summation over the first set of one or more values.
    Type: Grant
    Filed: September 12, 2017
    Date of Patent: September 29, 2020
    Assignee: Oracle International Corporation
    Inventors: Shasank K. Chavan, Dennis Lui, Allison L Holloway, Sheldon A. K. Lewis
  • Patent number: 10785346
    Abstract: A thread of a client process may become blocked awaiting a reply to a message sent to a server process. Unblocking the client may include determining by the operating system that a timeout has expired without the server having replied to the message and then sending a request to the server process reply to the message to unblock the client. After sending the request for the server to reply to the message, the operating system may determine that the server has still not replied to the message after a further period has elapsed. If so, one or more actions related to the server process may be triggered. For example, a signal may be sent to the server process or the computer system may be rebooted.
    Type: Grant
    Filed: April 8, 2019
    Date of Patent: September 22, 2020
    Assignee: 2236008 Ontario Inc.
    Inventors: Brian John Stecher, Kaushik Thirukonda
  • Patent number: 10776143
    Abstract: A technique for assigning physical resources of a data processing system to a virtual machine (VM) includes reading, by a hypervisor executing on the data processing system, a fold factor attribute for the VM. The fold factor attribute defines an anticipated usage of physical resources of the data processing system by the VM. The technique also includes mapping based on a value of the fold factor attribute, by the hypervisor, allocated virtual processors of the VM to the physical resources to maximize processor core access to local memory for ones of the allocated virtual processors that are anticipated to be utilized.
    Type: Grant
    Filed: June 17, 2014
    Date of Patent: September 15, 2020
    Assignee: International Business Machines Corporation
    Inventors: Peter Joseph Heyrman, Bret Ronald Olszewski, Sergio Reyes
  • Patent number: 10776412
    Abstract: A method comprises defining a machine learning model corresponding to a plurality of layouts for content based on a plurality of target user types, processing the content to identify a theme of the content, generating at least one electronic document for the content based on the theme and at least one of the plurality layouts, analyzing a plurality of interactions of a user with the electronic document, wherein the plurality of interactions include one or more searches performed by the user to retrieve the electronic document, and/or one or more steps taken by the user to consume the content in the electronic document, identifying at least one pattern of the user corresponding to the retrieval and/or consumption of the content, and training the machine learning model based on the at least one pattern by applying one or more machine learning algorithms to data from the plurality of interactions.
    Type: Grant
    Filed: July 11, 2018
    Date of Patent: September 15, 2020
    Assignee: EMC IP Holding Company LLC
    Inventors: Mainak Roy, Chitrak Gupta, Rathi Babu
  • Patent number: 10740127
    Abstract: A technique for assigning physical resources of a data processing system to a virtual machine (VM) includes reading, by a hypervisor executing on the data processing system, a fold factor attribute for the VM. The fold factor attribute defines an anticipated usage of physical resources of the data processing system by the VM. The technique also includes mapping based on a value of the fold factor attribute, by the hypervisor, allocated virtual processors of the VM to the physical resources to maximize processor core access to local memory for ones of the allocated virtual processors that are anticipated to be utilized.
    Type: Grant
    Filed: September 19, 2014
    Date of Patent: August 11, 2020
    Assignee: International Business Machines Corporation
    Inventors: Peter Joseph Heyrman, Bret Ronald Olszewski, Sergio Reyes
  • Patent number: 10732669
    Abstract: Serial peripheral interfaces and methods of operating the same are provided. An apparatus can have a serial peripheral interface (SPI) including a first command state machine (CSM), and a second CSM.
    Type: Grant
    Filed: August 3, 2017
    Date of Patent: August 4, 2020
    Assignee: Micron Technology, Inc.
    Inventor: Paolo E. Mangalindan
  • Patent number: 10721791
    Abstract: A system recommends the refactoring of microservices. The system generates a graph of connected nodes including a first node, which represents a first atomic part of code in a microservice in an application, and a second node, which represents a second atomic part of code in the microservice. The system determines a nodes connection score based on any connections between the first node and the second node. If the nodes connection score satisfies a nodes connection threshold, the system determines a relative code size based on comparing a size associated with the first atomic part of code against a size of the microservice. If the relative code size satisfies a code size threshold, the system outputs a recommendation to disconnect the first atomic part of code from the microservice, create another microservice in the application, and connect the first atomic part of code to the other microservice.
    Type: Grant
    Filed: April 17, 2019
    Date of Patent: July 21, 2020
    Assignee: EMC IP HOLDING COMPANY LLC
    Inventors: Roi Gamliel, Amihai Savir, Avitan Gefen
  • Patent number: 10705967
    Abstract: The present disclosure is directed to systems and methods of implementing a neural network using in-memory mathematical operations performed by pipelined SRAM architecture (PISA) circuitry disposed in on-chip processor memory circuitry. A high-level compiler may be provided to compile data representative of a multi-layer neural network model and one or more neural network data inputs from a first high-level programming language to an intermediate domain-specific language (DSL). A low-level compiler may be provided to compile the representative data from the intermediate DSL to multiple instruction sets in accordance with an instruction set architecture (ISA), such that each of the multiple instruction sets corresponds to a single respective layer of the multi-layer neural network model. Each of the multiple instruction sets may be assigned to a respective SRAM array of the PISA circuitry for in-memory execution.
    Type: Grant
    Filed: October 15, 2018
    Date of Patent: July 7, 2020
    Assignee: Intel Corporation
    Inventors: Amrita Mathuriya, Sasikanth Manipatruni, Victor Lee, Huseyin Sumbul, Gregory Chen, Raghavan Kumar, Phil Knag, Ram Krishnamurthy, Ian Young, Abhishek Sharma
  • Patent number: 10705846
    Abstract: Embodiments are disclosed for inserting profiling instructions into graphics processing unit (GPU) kernels. An example apparatus includes an entry point detector to detect a first entry point address and a second entry point address of an original GPU kernel. An instruction inserter is to create a corresponding instrumented GPU kernel from the original GPU kernel by adding instructions of the original GPU kernel and one or more profiling instructions to the instrumented GPU kernel. The instruction inserter is to insert, at the first entry point address of the instrumented GPU kernel, a first jump instruction to jump to first profiling initialization instructions, the instruction inserter to insert, at the second entry point address of the instrumented GPU kernel, a second jump instruction to jump to second profiling initialization instructions. The instruction inserter is to insert profiling measurement instructions of the profiling instructions into the instrumented GPU kernel.
    Type: Grant
    Filed: August 15, 2018
    Date of Patent: July 7, 2020
    Assignee: Intel Corporation
    Inventors: Konstantin Levit-Gurevich, Orr Goldman
  • Patent number: 10705804
    Abstract: Type safety is important property of any type system. Modern programming languages support different mechanisms to work in type safe manner, e.g., properties, methods, events, attributes (annotations) and other structures, but none of the existing, general purpose, programming languages which support reflection provide type safe type (class/structure) member metadata access. Existing solutions provide no or limited type safety which are complex and processed at runtime which by definition is not built-in type-safe metadata access, but only more or less type safe workarounds called “best practices”. Problem can be solved by introducing method for type safe type member metadata access which could be processed at compile time.
    Type: Grant
    Filed: February 22, 2013
    Date of Patent: July 7, 2020
    Assignee: Logistics Research Centre SIA
    Inventors: Mikus Vanags, Arturs Licis, Janis Justs
  • Patent number: 10698791
    Abstract: Method and system are provided for handling request data with type safety in a remote service. The method includes providing a data structure, the data structure comprising a set of entries, each entry matching an incoming request type with a function for handling the request, the function defining a set of parameters. The method includes receiving an incoming request for a service from a remote client, wherein the request includes request data. The method includes using the data structure and identifying an entry for the incoming request by matching the request data to an incoming request type of an entry. The method includes converting the incoming request into a set of parameters using a software construct of the matching function identified in the entry, wherein the software construct comprises the matching function and associated in-scope local variables; and running the function using the converted parameters.
    Type: Grant
    Filed: July 28, 2018
    Date of Patent: June 30, 2020
    Assignee: International Business Machines Corporation
    Inventors: Michael J. Tunnicliffe, Christopher N. Bailey
  • Patent number: 10691435
    Abstract: Systems and methods for binary translation of executable code.
    Type: Grant
    Filed: November 26, 2018
    Date of Patent: June 23, 2020
    Assignee: Parallels International GmbH
    Inventors: Alexey Koryakin, Nikolay Dobrovolskiy, Serguei M. Beloussov
  • Patent number: 10678562
    Abstract: Provided herein are methods, systems, and computer-program products for providing a library of base classes to be used by applications to facilitate real-time analytics. In some examples, the library may be a C++ Library that provides a set of primitive operators (e.g., spout base class, tube base class, and sink base class) for user derivation. In some examples, the spout base class may relate to receiving data from a data source, the tube base class may relate to performing one or more operations on the received data, and the sink base class may relate to sending the processed data to a data target. The spout, tube, sink together provide a real-time streaming framework interface that may be extended by the user.
    Type: Grant
    Filed: November 15, 2017
    Date of Patent: June 9, 2020
    Assignee: K&M Systems, Inc.
    Inventors: Alexander Hurd, Kurtis Cahill
  • Patent number: 10668378
    Abstract: Client machines are configured to compile shaders during execution of a program (e.g., a video game) that renders graphics on a display. These client machines may upload information—including a hardware configuration of the client machine, an application identifier (ID) of the program, and a set of shader IDs for compiled shaders—to a remote computing system, which catalogues the shader IDs, selectively requests compiled shader code from one or more of the client machines, and selectively prepares the compiled shader code for redistribution. Thereafter, a requesting client machine with a matching hardware configuration may receive compiled shader code from the remote system for a particular program, and may precache the compiled shader code for use during program execution.
    Type: Grant
    Filed: January 26, 2018
    Date of Patent: June 2, 2020
    Assignee: Valve Corporation
    Inventor: Pierre-Loup Miguel Griffais
  • Patent number: 10671386
    Abstract: Setting or updating of floating point controls is managed. Floating point controls include controls used for floating point operations, such as rounding mode and/or other controls. Further, floating point controls include status associated with floating point operations, such as floating point exceptions and/or others. The management of the floating point controls includes efficiently updating the controls, while reducing costs associated therewith.
    Type: Grant
    Filed: April 30, 2019
    Date of Patent: June 2, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Michael K. Gschwind, Valentina Salapura
  • Patent number: 10664943
    Abstract: The disclosed concepts provide a method to generate and use a compound shader object. A compound shader object includes a shader's intermediate representation (IR) and one or more binary modules; each binary module configured to execute on one type of graphics processing unit (GPU) with a specific input state. One method includes receiving, through a public application programming interface (API), a request to execute a shader from an user-level application. At the framework level, if the request corresponds to one of the prior compiled binary modules, that module may be passed to a GPU for immediate execution via a system private interface. If the request does not correspond to one of the binary modules, the shader's IR module may returned to the requesting user-level application (which module would then have to be compiled before it may be sent to the GPU).
    Type: Grant
    Filed: May 25, 2018
    Date of Patent: May 26, 2020
    Assignee: Apple Inc.
    Inventors: Kelvin C. Chiu, Charles Brissart, Gokhan Avkarogullari, Lloyd A. Cunningham, Rahul U. Joshi
  • Patent number: 10664766
    Abstract: Provided herein in some embodiments is an artificial intelligence (“AI”) engine configured to work with a graphical user interface (“GUI”). The AI engine can include an architect module, instructor module, and learner module AI-engine modules. The GUI can be configured with a text editor and a mental-model editor to enable an author to define a mental model to be learned by an AI model, the mental model including an input, one or more concept nodes, and an output. The architect module can be configured to propose a neural-network layout from an assembly code compiled from a source code in a pedagogical programming language, the learner module can be configured to build the AI model from the neural-network layout, and the instructor module can be configured to train the AI model on the one or more concept nodes.
    Type: Grant
    Filed: January 26, 2017
    Date of Patent: May 26, 2020
    Assignee: Bonsai AI, Inc.
    Inventors: Mark Isaac Hammond, Keen McEwan Browne, Mike Estee, Clara Kliman-Silver
  • Patent number: 10652040
    Abstract: Methods, systems, and computer program products for interfacing system controls are provided. Aspects include receiving, by a processor, object data for a plurality of objects. An object profile is generated for each of the plurality of objects based at least in part on the object data and one or more communication platforms are accessed. The object profiles for each of the plurality of objects are registered with the one or more communication platforms.
    Type: Grant
    Filed: January 12, 2018
    Date of Patent: May 12, 2020
    Assignee: CARRIER CORPORATION
    Inventors: Balaji Kaliappan, Michael Ramoutar, Hector O. Colon
  • Patent number: 10635418
    Abstract: State recovery methods and apparatus for computing platforms are disclosed. An example method includes inserting, with a processor, a first instruction into optimized code to cause a first portion of a register in a first state to be saved to memory before execution of a region of the optimized code, maintaining, with the processor, a first indication of a first manner in which the first portion of the register is to be restored in connection with a state recovery after execution of the region of the optimized code, and maintaining, with the processor, a second indication of a second manner in which a second portion of the register is to be restored in connection with the state recovery after execution of the region of the optimized code.
    Type: Grant
    Filed: October 27, 2016
    Date of Patent: April 28, 2020
    Assignee: Intel Corporation
    Inventors: Abhay S. Kanhere, Saurabh Shukla, Suriya Subramanian, Paul Caprioli
  • Patent number: 10628139
    Abstract: An analysis apparatus, includes: a memory; and a processor coupled to the memory, wherein the processor: acquires two source codes of a comparison target; generates two abstract syntax trees of the two source codes by analyzing the two source codes; graphs, based on the two abstract syntax trees, a flow of processing and a flow of data in methods and between methods in the two source codes, reduces, based on a given rule, one or more redundant portions of the respective graphs of the two graphed source codes; and compares the two reduced graphs and outputs a difference between the two source codes.
    Type: Grant
    Filed: June 8, 2018
    Date of Patent: April 21, 2020
    Assignee: FUJITSU LIMITED
    Inventor: Koji Yamamoto
  • Patent number: 10628162
    Abstract: Enabling parallel memory accesses by providing explicit affine instructions in vector-processor-based devices is disclosed. In this regard, a vector-processor-based device implementing a block-based dataflow instruction set architecture (ISA) includes a decoder circuit configured to provide an affine instruction that specifies a base parameter indicating a base value B, a stride parameter indicating a stride interval value S, and a count parameter indicating a count value C. The decoder circuit of the vector-processor-based device decodes the affine instruction, and generates an output stream comprising one or more output values, wherein a count of the output values of the output stream equals the count value C. Using an index X where 0?X<C, each Xth output value in the output stream is generated as a sum of the base value B and a product of the stride interval value S and the index X.
    Type: Grant
    Filed: June 19, 2018
    Date of Patent: April 21, 2020
    Assignee: Qualcomm Incorporated
    Inventors: Amrit Panda, Eric Rotenberg, Hadi Parandeh Afshar, Gregory Michael Wright
  • Patent number: 10620980
    Abstract: Examples described herein generally relate to natively rendering hypertext markup language (HTML) graphics content associated with source code at a computer device. Specifically, the computer device receives, at a compiler, the source code associated with graphics based content. The computer device further compiles at least a portion of the source code into native code including at least one graphics application program interface (API). Moreover, the computer device further determines, at a native bridge translator, that at least one native API associated with a graphics processing unit of the computer device corresponds to the graphics API. The computer device further transmits the at least one native API to the graphics processing unit for native rendering of the HTML graphics content at the computer device.
    Type: Grant
    Filed: March 28, 2018
    Date of Patent: April 14, 2020
    Assignee: Microsoft Technology Licensing, LLC
    Inventor: Aravindan Elango
  • Patent number: 10606582
    Abstract: Systems, methods, devices and non-transitory, computer-readable storage mediums are disclosed for automated mobile app integration.
    Type: Grant
    Filed: October 17, 2018
    Date of Patent: March 31, 2020
    Assignee: APPDOME LTD.
    Inventors: Avner Yehuda, Gil Hartman, Tomas Tovar
  • Patent number: 10599852
    Abstract: This invention teaches a system and methods of detecting software vulnerabilities in a computer program by analyzing the compiled code and optionally the source code of the computer program. The invention models compiled software to examine both control flow and data flow properties of the target program. A comprehensive instruction model is used for each instruction of the compiled code, and is complemented by a control flow graph that includes all potential control flow paths of the instruction. A data flow model is used to record the flow of unsafe data during the execution of the program. The system analyzes the data flow model and creates a security finding corresponding to each instruction that calls an unsafe function on unsafe data. The security findings are aggregated in a security report. To improve performance, the system further uses data flow merging, and caching of 1-to-many data flow maps for each basic block in the code.
    Type: Grant
    Filed: March 1, 2016
    Date of Patent: March 24, 2020
    Assignee: SECURISEA, INC.
    Inventor: Joshua M. Daymont
  • Patent number: 10592500
    Abstract: The method can include receiving the first stream of tuples to be processed by the stream operator hosted by one or more computer processors, the stream operator having at least one input port and a condition input port. The method can also include receiving, at runtime, a customized condition at the condition input port of the stream operator. The method can also include monitoring a first group of one or more tuples from the first stream of tuples at a first window of the stream operator. The method can also include determining whether the first group of one or more tuples at the first window fulfills the customized condition. The method can also include deleting, in response to the first group of one or more tuples fulfilling the customized condition, the first group of one or more tuples.
    Type: Grant
    Filed: January 27, 2015
    Date of Patent: March 17, 2020
    Assignee: International Business Machines Corporation
    Inventors: Michael J. Branson, Bradford L. Cobb, John M. Santosuosso
  • Patent number: 10587521
    Abstract: The disclosure is directed to a system for hierarchically orchestrating network traffic including a network orchestration module and multiple device orchestration modules. The device orchestration module is configured to receive network traffic. The device orchestration module may transmit device data to the network orchestration module. The network orchestration module is configured to perform a network level orchestration to coordinate network traffic across multiple device orchestration modules based on the device data received by the device orchestration modules. The device orchestration module comprises a routing layer configured to forward network traffic to downstream computing devices. The device orchestration module includes a compute node configured to perform a device level orchestration of the network traffic between the routing nodes of the device orchestration module.
    Type: Grant
    Filed: November 7, 2017
    Date of Patent: March 10, 2020
    Assignee: Facebook, Inc.
    Inventors: Naader Hasani, Hans-Juergen Schmidtke, Najam Ahmad
  • Patent number: 10579736
    Abstract: Embodiments of the present disclosure provide a method and a device for determining a comment, a server and a storage medium. The method includes: obtaining text content of an event; determining an event tag of the event according to the text content; comparing the event tag with comment tags in a comment graph, to determine candidate comments, the comment graph being generated according to other events and corresponding comments, and the comment graph including comments and corresponding comment tags; and screening the candidate comments, to determine a candidate comment satisfying a preset condition as the comment of the event.
    Type: Grant
    Filed: December 27, 2017
    Date of Patent: March 3, 2020
    Assignee: BEIJING BAIDU NETCOM SCIENCE AND TECHNOLOGY CO., LTD.
    Inventors: Yingchao Shi, Wei He, Qiaoqiao She, Jianqing Cui, Xiangyang Zhou, Junqiang Zheng
  • Patent number: 10574541
    Abstract: A computer-implemented method comprising capturing measurement data via a first sensor suite, broadcasting the measurement data via short-range communication, receiving, via the short-range communication, a broadcast including a quality control analysis result corresponding to the measurement data and determined by a second sensor suite, acting on the quality control analysis result, and performing quality control analysis for a third sensor suite.
    Type: Grant
    Filed: November 6, 2017
    Date of Patent: February 25, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Eric J. Barkie, Benjamin Fletcher, Timothy P. Roche, Shawn Stedman
  • Patent number: 10565104
    Abstract: A method and system for self-regulating memory of a JAVA virtual machine optimizes memory use by the JVM and by an operating system. A computer running a garbage collector extension monitors and records free committed memory of the JVM at predetermined intervals over time to define a historical record. The computer calculates an average allocation of the free committed memory in the historical record over predetermined intervals. An allocation rate is determined, wherein the allocation rate is based on the average allocation over the predetermined intervals. The computer calculates an estimated time to exhaust committed memory based on free committed heap memory and the allocation rate. Memory is recovered from the operating system if the time to exhaust committed memory is below a first predetermined threshold value and is released to the operating system when said time to exhaust committed memory is above a second predetermined threshold value.
    Type: Grant
    Filed: August 1, 2017
    Date of Patent: February 18, 2020
    Assignee: International Business Machines Corporation
    Inventors: Dinakar Guniguntala, Ashutosh Mehra, Parameswaran Selvam
  • Patent number: 10565019
    Abstract: The present disclosure relates to a multicore processor. In order to select one of a multiplicity of cores in a multicore processor, an execution time of tasks which are performed multiple times is determined. Based on the determined execution time on the individual cores, an appropriate core for further executions of a task is selected. Additionally, the present disclosure further provides a code generator and code generating method for providing appropriate machine code for a multicore processor.
    Type: Grant
    Filed: June 26, 2015
    Date of Patent: February 18, 2020
    Assignee: Huawei Technologies Co., Ltd.
    Inventors: Mikhail Levin, Alexander Filippov, Youliang Yan
  • Patent number: 10558444
    Abstract: An apparatus is provided for building an application. The apparatus may include at least one memory and at least one processor configured to generate a build of an application in a C Object-Oriented Programming Language. The processor is also configured to generate a unity file including a plurality of source files having references to one or more header files. At least two of the source files include references to a same header file. The processor is also configured to compile the unity file including the plurality of source files to obtain an object file. The processor is also configured to link the object file to generate an executable of the application. Corresponding computer program products and methods are also provided.
    Type: Grant
    Filed: May 2, 2019
    Date of Patent: February 11, 2020
    Assignee: UNITED PARCEL SERVICE OF AMERICA, INC.
    Inventor: Michael Liberant
  • Patent number: 10558642
    Abstract: Techniques are described to allow the deprecation of classes in an object-oriented data model, such as a CDM for a CMDB. When a class is deprecated and replaced by another existing or new class, data associated with instances of the deprecated class may be migrated to the replacement class. A mapping between the deprecated class and its replacement class may be provided to allow existing applications to continue to access data using the deprecated class without change until the deprecated class is finally deleted or the application is updated to use the replacement class. New applications written to use the object-oriented data model after the deprecation may use the replacement class to access data instances created using the original data model.
    Type: Grant
    Filed: September 11, 2017
    Date of Patent: February 11, 2020
    Assignee: BMC Software, Inc.
    Inventors: Govindarajan Rangarajan, Narayan Kumar
  • Patent number: 10558440
    Abstract: In an example, there is disclosed a computing system, including: a processor; a memory; a configuration interface to a logic configuration unit; and a system compiler including: a first block compiler to compile logic for a first logical block in a first language, the first language being a domain-specific language (DSL) and the first logical block being switching logic for a network switch; a second block compiler to compile logic for a second logical block in a second language, the second language being a non-DSL and providing an external accelerator method not supported by the first language; and an interface compiler to define input/output channels for encapsulated data interchange between the first logical block and the second logical block, wherein the encapsulated data interchange is to target a resident instance of the external accelerator method.
    Type: Grant
    Filed: May 26, 2017
    Date of Patent: February 11, 2020
    Assignee: Cisco Technology, Inc.
    Inventors: John W. Marshall, Earl Hardin Booth, III, Andrew William Keep, Robert Leroy King
  • Patent number: 10552127
    Abstract: Some embodiments described herein provide a system to run a source program. The system receives a source program with derived variables and/or derived functions. The system first performs syntax and semantic analysis on the received source program, and subsequently generates executable code. When the source program has a derived variable, the system generates executable code for: creating an object that includes the derived variable, assigning a value to the derived variable, and searching for a value of the derived variable at runtime. When the source code has a derived function, the system generates executable code for searching for a value of the derived function at runtime. Finally the system runs the generated executable code at runtime.
    Type: Grant
    Filed: August 8, 2018
    Date of Patent: February 4, 2020
    Inventor: Raju Pandey
  • Patent number: 10545706
    Abstract: Disclosed is a control method for an image forming apparatus including firmware and an application operating on the firmware, the control method including registering a size of a defined sheet in a storage unit in accordance with a user operation under control of the firmware, accepting a selection instruction of the registered size of the defined sheet in accordance with the user operation under control of the application, and control printing using the defined sheet having the size according to the selection instruction under the control of the firmware.
    Type: Grant
    Filed: August 29, 2018
    Date of Patent: January 28, 2020
    Assignee: CANON KABUSHIKI KAISHA
    Inventor: Atsushi Ikeda
  • Patent number: 10534604
    Abstract: A computer-implemented method includes creating, by a computing device, an abstract syntax tree based on a source code file of a software application, the source code file including source code defining operations of the software application. The method also includes traversing, by the computing device, the abstract syntax tree. The method further includes identifying, by the computing device and based on the traversing of the abstract syntax tree, one or more code violations present in the source code. The method also includes generating, by the computing device, at least one refactoring option for the one or more code violations, each refactoring option of the at least one refactoring option representing a change to the source code file that is configured to remediate the associated code violation.
    Type: Grant
    Filed: March 20, 2018
    Date of Patent: January 14, 2020
    Assignee: ARCHITECTURE TECHNOLOGY CORPORATION
    Inventors: Colleen Kimball, Katey Huddleston, Paul Nicotera
  • Patent number: 10521204
    Abstract: A compiler may perform type checking as part of analyzing source code. The type checking may include existential type packing for structurally-restricted existential types. At compile time, the compiler may need to use an existential type that does not conform to the language's structural rules. The compiler may apply the “pack” operation described herein to produce a supertype of the desired existential type that does conform to the language's structural rules, and thus can be used as an approximation of the desired type. The compiler may then perform additional type checking using the resulting type.
    Type: Grant
    Filed: May 23, 2016
    Date of Patent: December 31, 2019
    Assignee: Oracle International Corporation
    Inventor: Daniel L. Smith
  • Patent number: 10503490
    Abstract: Embodiments of the present application relate to a method, apparatus, and system for processing an app. The method includes obtaining a plugin identifier, obtaining an app plugin installation package from a server, wherein the app plugin installation package is associated with the plugin identifier, installing the app plugin installation package, obtaining an app plugin lookup instruction associated with an app plugin, and determining the app plugin according to the app plugin lookup instruction, wherein the app plugin implements a specific function of a corresponding app in response to the app plugin being invoked.
    Type: Grant
    Filed: October 30, 2018
    Date of Patent: December 10, 2019
    Assignee: Alibaba Group Holding Limited
    Inventors: Chao Xi, Yue Zhang, Huan Zeng
  • Patent number: 10481893
    Abstract: Technologies are disclosed herein for identifying and resolving firmware component dependencies within a firmware project. Dependency information is generated and stored for firmware components that can be used to create a firmware project. The dependency information may define one or more mandatory dependencies, optional dependencies, and/or incompatible dependencies. The dependency information for the firmware components in the firmware project is evaluated to identify any unsatisfied dependencies when a firmware project is opened, when a firmware component is added to a firmware project, when a firmware component in a firmware project is updated, or when the firmware project is built. If any unsatisfied dependencies are identified, the dependencies can be satisfied by adding a firmware component to the firmware project, updating a firmware component in the firmware project, or by removing a firmware component from the firmware project.
    Type: Grant
    Filed: August 10, 2015
    Date of Patent: November 19, 2019
    Assignee: American Megatrends International, LLC
    Inventors: Stefano Righi, Presanna Raman
  • Patent number: 10467390
    Abstract: Embodiments of the present disclosure relate to anti-tamper computer systems, in particular to methods and systems which can embed protection code into software. Among other things, the protection code helps prevent (and make it more costly) to reverse engineer to tamper with the protected software with malicious intent, such as, but not restricted to: the removal of a license protection mechanism; the removal of code displaying advertisements; the injection of a malicious thread into the program memory space; illicit usage; or any other kind of unauthorized modification of the software.
    Type: Grant
    Filed: August 18, 2017
    Date of Patent: November 5, 2019
    Assignee: Snap Inc.
    Inventors: Johan Wehrli, Julien Rinaldini
  • Patent number: 10467410
    Abstract: An apparatus and method for monitoring the confidentiality and integrity of a target system. The apparatus for monitoring the confidentiality and integrity of a target system includes a target area information reception unit for receiving target area information about a target area of the target system and storing the target area information, a monitoring unit for extracting attack information by monitoring at least one of confidentiality, corresponding to a data load instruction, and integrity, corresponding to a data store instruction, based on the target area information, and an attack-handling unit for determining whether an attack is occurring based on the extracted attack information and for handling the attack when it is determined that an attack is occurring.
    Type: Grant
    Filed: January 12, 2017
    Date of Patent: November 5, 2019
    Assignee: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTE
    Inventors: Sangrok Lee, Junghee Lee
  • Patent number: 10423779
    Abstract: Software self-checking mechanisms are described for improving software tamper resistance and/or reliability. Redundant tests are performed to detect modifications to a program while it is running. Modifications are recorded or reported. Embodiments of the software self-checking mechanisms can be implemented such that they are relatively stealthy and robust, and so that they are compatible with copy-specific static watermarking and other tamper-resistance techniques.
    Type: Grant
    Filed: March 14, 2018
    Date of Patent: September 24, 2019
    Assignee: Intertrust Technologies Corporation
    Inventors: William G. Horne, Lesley R. Matheson, Casey Sheehan, Robert E. Tarjan
  • Patent number: 10416973
    Abstract: A method comprises receiving a source code having a data set with a processor, opening the data set and identifying compile stage dependencies and run stage dependencies in the data set, determining whether a compile stage dependency has been identified, determining whether the identified compile stage dependency is accessible responsive to determining that the compile stage dependency has been identified, retrieving the compile stage dependency responsive to determining that the identified compile stage dependency is accessible, and compiling the source code and saving the compiled source code in a memory using the retrieved compile stage dependency responsive to determining that no run stage dependencies have been identified.
    Type: Grant
    Filed: November 8, 2017
    Date of Patent: September 17, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINE CORPORATION
    Inventors: Eli M. Dow, Thomas D. Fitzsimmons, Emily M. Metruck, Charles J. Stocker, IV
  • Patent number: 10416972
    Abstract: A device may receive source code and identify, based on the source code, an abstract syntax tree representing an abstract syntactic structure of the source code. Based on the abstract syntax tree, the device may identify a closure, the closure implementing a function based on at least a portion of the abstract syntax tree. In addition, the device may perform an action based on the closure.
    Type: Grant
    Filed: March 16, 2018
    Date of Patent: September 17, 2019
    Assignee: Capital One Services, LLC
    Inventor: Behdad Forghani
  • Patent number: 10394687
    Abstract: The present invention relates to a method for classifying alarm types in detecting source code errors, a computer program therefor, and a recording medium thereof. The method for classifying alarm types in detecting source code errors includes: receiving input of alarm path information about an occurring error detection alarm and source code information that is an object associated with the occurring alarm, the alarm path information being information about an execution path related to the error detection; converting the source code into an abstract syntax tree (AST); removing, from the AST, an unnecessary sub-tree that is not related to the error detection alarm; obtaining a feature vector of the AST having the unnecessary sub-tree removed therefrom based on a preset feature pattern set; and classifying, by types, the error detection alarm associated with the feature vector by clustering the obtained feature vector using a preset method.
    Type: Grant
    Filed: November 26, 2015
    Date of Patent: August 27, 2019
    Assignee: SPARROW CO., LTD.
    Inventors: Jongwon Yoon, Minsik Jin
  • Patent number: 10387153
    Abstract: Techniques for synchronizing a set of code branches are disclosed. A synchronization process is triggered by an event and/or a schedule. The synchronization process includes traversing each code branch, such that parent branches of a particular branch are “in sync” prior to being merged into the particular branch. In an embodiment, a hierarchical order for a set of branches is determined. The branch represented by the top node of the hierarchical order does not have any parents. A branch that is a child of the branch represented by the top node is in the second level of the hierarchical order. The branch in the second level is updated by incorporating the current state of the branch represented by the top node. Thereafter, each branch is iteratively updated by incorporating the current state of the branch's parent branch. Hence, changes to any parent branch are propagated through all its descendant branches.
    Type: Grant
    Filed: November 27, 2017
    Date of Patent: August 20, 2019
    Assignee: Oracle International Corporation
    Inventors: Maurizio Cimadamore, Brian Goetz
  • Patent number: 10346055
    Abstract: Systems, apparatuses, and methods for performing run-time checking of access uniformity of vector memory access instructions are disclosed. A system includes a vector unit, a scalar unit, and a memory. The system performs a run-time check to determine if two or more threads of a wave have access uniformity to the memory prior to executing a vector memory access instruction for the wave on the vector unit. The system replaces the vector memory access instruction with a group of instructions responsive to determining that two or more threads of the wave have access uniformity to the memory. The group of instructions includes a scalar access instruction to memory followed by a cross-thread data sharing instruction. The scalar access instruction is executed on the scalar unit. Alternatively, the group of instructions can include a vector memory access instruction by only a single thread in each group having access uniformity.
    Type: Grant
    Filed: July 28, 2017
    Date of Patent: July 9, 2019
    Assignee: Advanced Micro Devices, Inc.
    Inventor: Guohua Jin
  • Patent number: 10346157
    Abstract: Various aspects include methods for implementing a firmware patch infrastructure. Various aspects may include identifying a patchable object from a firmware source code image based on a symbol in the patchable object's name, generating a patchable firmware source code file by injecting a first call to the patchable object configured to call to an indirection table and a second call to the patchable object configure to execute the patchable object, building a patchable firmware source code image from a plurality of patchable firmware source code files including the patchable firmware source code file having the first call to the patchable object and the second call to the patchable object, and creating the indirection table including an entry for the first call from the patchable firmware source code image having an indication to implement the second call in the patchable firmware source code image.
    Type: Grant
    Filed: July 31, 2017
    Date of Patent: July 9, 2019
    Assignee: QUALCOMM Incorporated
    Inventors: Eugen Pirvu, Dhaval Patel, Dhamim Packer Ali, Bhargav Gurappadi