Abstract: An apparatus, program product and method optimize the operation of a parallel computer system by, in part, collecting performance data for a set of implementations of a function capable of being executed on the parallel computer system based upon the execution of the set of implementations under varying input parameters in a plurality of input dimensions. The collected performance data may be used to generate selection program code that is configured to call selected implementations of the function in response to a call to the function under varying input parameters. The collected performance data may be used to perform more detailed analysis to ascertain the comparative performance of the set of implementations of the function under the varying input parameters.

Abstract: A method and a medium are disclosed for executing a technical computing program in parallel in multiple execution environments. A program is invoked for execution in a first execution environment and from the invocation the program is executed in the first execution environment and one or more additional execution environments to provide for parallel execution of the program. New constructs in a technical computing programming language are disclosed for parallel programming of a technical computing program for execution in multiple execution environments. It is also further disclosed a system and method for changing the mode of operation of an execution environment from a sequential mode to a parallel mode of operation and vice-versa.

Abstract: A method and medium are disclosed for executing a technical computing program in parallel in multiple execution environments. A program is invoked for execution in a first execution environment and from the invocation the program is executed in the first execution environment and one or more additional execution environments to provide for parallel execution of the program. New constructs in a technical computing programming language are disclosed for parallel programming of a technical computing program for execution in multiple execution environments. It is also further disclosed a system and method for changing the mode of operation of an execution environment from a sequential mode to a parallel mode of operation and vice-versa.

Abstract: A program conversion apparatus according to the present invention includes: a thread creation unit which creates a plurality of threads equivalent to a program part included in a program, based on path information on a plurality of execution paths, each of the execution paths going from a start to an end of the program part, each of the threads being equivalent to at least one of the execution paths; a replacement unit which performs variable replacement on the threads so that a variable shared by the threads is accessed by only to one of the threads in order to avoid an access conflict among the threads; and a thread parallelization unit which generates a program which causes the threads to be speculatively executed in parallel after the variable replacement.

Abstract: The embodiments provide schemes for micro parallelization.

Abstract: Provided are techniques for compilation of hierarchical data processing. A data flow diagram including one or more operators, wherein each operator includes at least one of an incoming arc and an outgoing arc, is received. For each operator, for each incoming arc, it is validated that an arc input formal schema is compatible with a schema rooted in a context node in an arc input actual schema, and, for each outgoing arc, an arc output formal schema is computed based on operator logic and operator inputs and an arc output actual schema is computed from the arc input actual schema by replacing the context node of the arc input actual schema with the arc output formal schema.

Abstract: A method and apparatus is disclosed for compilation of an original Cobol program and building an executable program with support for improved performance by increased parallelism during execution using multiple threads of processing. The approach includes a compilation (or translation) step utilizing a first compiler or translating program which is a parallel aware translating first compiler. The parallel aware first compiler is a specialized compiler/translator which takes as input a Cobol source program, and produces as output an intermediate computer program in a second computer programming language, the intermediate program including parallelization directives, the intermediate program intended for further compilation utilizing an existing selected second compiler, the second compiler providing support for parallelism for programs described in the second programming language.

Abstract: Technologies are generally described for parallel dynamic optimization using multicore processors. A runtime compiler may be adapted to generate multiple instances of executable code from a portable intermediate software module. The various instances of executable code may be generated with variations of optimization parameters such that the code instances each express different optimization attempts. A multicore processor may be leveraged to simultaneously execute some, or all, of the various code instances. Preferred optimization parameters may be determined from the executable code instances that may correctly complete in the least time, or may use the least amount of memory, or that may prove superior according to some other fitness metric. Preferred optimization parameters may be used to seed future optimization attempts. Output generated from the preferred instances may be used as soon as the first instance correctly completes block.

Abstract: An optimizing compiler device, a method, a computer program product which are capable of performing parallelization of irregular reductions. The method for performing parallelization of irregular reductions includes receiving, at a compiler, a program and selecting, at compile time, at least one unit of work (UW) from the program, each UW configured to operate on at least one reduction operation, where at least one reduction operation in the UW operates on a reduction variable whose address is determinable when running the program at a run-time. At run time, for each successive current UW, a list of reduction operations accessed by that unit of work is recorded. Further, it is determined at run time whether reduction operations accessed by a current UW conflict with any reduction operations recorded as having been accessed by prior selected units of work, and assigning the unit of work as a conflict free unit of work (CFUW) when no conflicts are found.

Abstract: This invention describes a compilation method of extracting and implementing an accelerator control program from an application source code in a processor based system. The application source code comprises arrays and loops. The input application source code is sequential, with loop, branch and call control structures, while the generated output of this invention has parallel execution semantics. The compilation method comprises the step of performing loop nest analysis, transformations and backend processes. The step of loop nest analysis consists of dependence analysis and pointer analysis. Dependence analysis determines the conflicts between the various references to arrays in the loop, and pointer analysis determines if two pointer references in a loop are in conflict. Transformations convert the loops from their original sequential execution semantics to parallel execution semantics. The back-end process determines the parameters and memory map of the accelerator and the hardware dependent software.

Abstract: Testing multithreaded application programs for errors can be carried out in an efficient and productive manner at least in part by prioritizing thread schedules based on numbers of context switches between threads therein. In particular, each thread schedule in a multithreaded application program can be prioritized based on whether a given thread schedule has the same as or less than some maximum value. A model checker module can then iteratively execute thread schedules that fit within a given context switch maximum value, or a progressively higher value up to some limit. In one implementation, for example, the model checker module executes all thread schedules that have zero preempting context switches, then all thread schedules that have only one preempting context switch, etc. Most errors in an application program can be identified by executing only those thread schedule with relatively few preempting context switches.

Abstract: A unified parallelization table is formed by describing a process, to be executed, with a plurality of control blocks and edges connecting the control blocks; selecting highly predictable edges from the edges; identifying strongly-connected clusters; creating a parallelization table, having the entries of the number of processors, the costs thereof and corresponding clusters, for each node in the strongly-connected clusters and a non-strongly connected cluster between the strongly-connected clusters; creating a graph consisting of parallelization tables; converting the graph consisting of the parallelization tables into a series-parallel graph; and merging the parallelization tables for each serial path merging the parallelization tables for each parallel section. Then, based on the number of processors and the cost value in the unified parallelization table, a best entry is selected and an executable code to be allocated to each processor is generated.

Abstract: A method for developing parallel programs comprises creating a file in the memory facilities of a terminal; recording of source code in the file by a user using the input facilities and display facilities of the terminal, the source code being a combination of imperative code, algebraic code, and reference elements; checking of all reference elements included in the source code, during compilation, by an analysis module stored in the memory facilities of the terminal till all the reference elements included in the source code are confirmed as correct or missing by the compiler; if all the reference elements are found to be correct during checking, generating the parallel program; and if one or more reference elements are found to be incorrect or missing during checking, displaying information to the user using the display facilities of the terminal so that the user can carry out corrections.

Abstract: A parallel programming adjusting apparatus and method are provided. Parameter sets are made by grouping parameters of a parallel programming model influencing the system performance, the parameter sets are combined among the groups, generating parameter combinations. Execution files are executed for the individual parameter combinations and a runtime of a parallel region for respective parameter combination is measured. An optimum parameter combination is selected based on the measured runtime.

Abstract: A computing method includes accepting a definition of a computing task (68), which includes multiple atomic Processing Elements (PEs—76) having execution dependencies (80). Each execution dependency specifies that a respective first PE is to be executed before a respective second PE. The computing task is compiled for concurrent execution on a multiprocessor device (32), which includes multiple processors (44) that are capable of executing a first number of the PEs simultaneously, by arranging the PEs, without violating the execution dependencies, in an invocation data structure (90) including a second number of execution sequences (98) that is greater than one but does not exceed the first number. The multiprocessor device is invoked to run software code that executes the execution sequences in parallel responsively to the invocation data structure, so as to produce a result of the computing task.

Abstract: A system and method for automatically parallelizing a computer program for multi-threaded execution. A compiler identifies and parallelizes non-DOALL parallel regions, such as loops, within a computer program. The compiler determines enhanced helper thread instructions based upon the main body instructions of the non-DOALL region. These helper thread instructions are inserted ahead of the main body instructions within each of the plurality of threads, rather than within a single main thread. Next, synchronization instructions are inserted in one or more threads such that the main body of work of each thread is performed in a pipelined manner. The helper thread instructions within each thread may reduce the total execution time of each thread.

Abstract: A program parallelization apparatus which generates a parallelized program of shorter parallel execution time is provided. The program parallelization apparatus inputs a sequential processing intermediate program and outputs a parallelized intermediate program. In the apparatus, a thread start time limitation analysis part analyzes an instruction-allocatable time based on a limitation on an instruction execution start time of each thread. A thread end time limitation analysis part analyzes an instruction-allocatable time based on a limitation on an instruction execution end time of each thread. An occupancy status analysis part analyzes a time not occupied by already-scheduled instructions. A dependence delay analysis part analyzes an instruction-allocatable time based on a delay resulting from dependence between instructions. A schedule candidate instruction select part selects a next instruction to schedule. An instruction arrangement part allocates a processor and time to execute to an instruction.

Abstract: A device receives, via a technical computing environment, a program that includes a parallel construct and a command to be executed by graphical processing units, and analyzes the program. The device also creates, based on the parallel construct and the analysis, one or more instances of the command to be executed in parallel by the graphical processing units, and transforms, via the technical computing environment, the one or more command instances into one or more command instances that are executable by the graphical processing units. The device further allocates the one or more transformed command instances to the graphical processing units for parallel execution, and receives, from the graphical processing units, one or more results associated with parallel execution of the one or more transformed command instances by the graphical processing units.

Abstract: A device initiates a technical computing environment (TCE), and receives, via the TCE, a program command that permits the TCE to access a graphical processing unit that is remote to the device, where the program command permits the TCE to seamlessly transfer data to the remote GPU. The device transforms, via the TCE, the program command into a program command that is executable by the remote GPU, and provides the transformed program command to the remote GPU for execution. The device also receives, from the remote GPU, one or more results associated with execution of the transformed program command by the remote GPU, and utilizes the one or more results via the TCE.

Abstract: Provided are a method, system, and program for parallelizing source code with a compiler. Source code including source code statements is received. The source code statements are processed to determine a dependency of the statements. Multiple groups of statements are determined from the determined dependency of the statements, wherein statements in one group are dependent on one another. At least one directive is inserted in the source code, wherein each directive is associated with one group of statements. Resulting threaded code is generated including the inserted at least one directive. The group of statements to which the directive in the resulting threaded code applies are processed as a separate task. Each group of statements designated by the directive to be processed as a separate task may be processed concurrently with respect to other groups of statements.

Abstract: System and method for measurement, DAQ, and control operations which uses small form-factor measurement modules or cartridges with a re-configurable carrier unit, sensors, and a computer system to provide modular, efficient, cost-effective measurement solutions. The measurement module includes measurement circuitry, e.g., signal conditioner and/or signal conversion circuitry, and interface circuitry for communicating with the carrier unit. The module communicates interface information to the carrier unit, which informs the computer system how to program or configure a functional unit on the carrier unit to implement the communicated interface, or sends the information directly to the computer system. The computer system programs the carrier unit with the interface, and the programmed carrier unit and measurement module together function as a DAQ, measurement, and/or control device.

Abstract: The operation of an electronic system comprising a plurality of integrated circuits or other circuit elements is simulated using a software-based development tool that provides a generic framework for simultaneous simulation of multiple circuit elements having potentially different clock speeds, latencies or other characteristics. One or more interfaces provided in the software-based development tool permit registration of processing events associated with one or more of the circuit elements. The software-based development tool is further operative to determine a system clock for a given simulation, and to schedule execution of the associated processing events in a manner that takes into account differences between the system clock and one or more circuit element clocks, so as to maintain consistency in the execution of the processing events relative to the determined system clock.

Abstract: A method is provided for comparing malware or other types of computer programs, and for optionally using such a comparison method for (a) searching for matching programs in a collection of programs, (b) classifying programs, and (c) constructing a classification or a partitioning within a collection of programs. In general, there are three steps to the comparison portion: selecting and extracting tokens from a pair of programs for comparison, building features from these tokens, and comparing the programs based on the frequency of feature occurrences to produce a similarity measure. Pairwise similarity is then used for optionally searching, classifying, or constructing classification systems.

Abstract: A data processing system includes a host computer, an additional computer, an application module including a first executable code, a module for analyzing said first executable code and a module for generating a second executable code segmented notably into code blocks which are executed in a preferential manner on one of the two computers. The second executable code includes a sub-module for managing the distribution of the processing operations between the host computer and the additional computer and a sub-module for managing the additional computer as a virtual machine which executes the blocks allocated to the additional computer.

Abstract: A system and method is provided for performing processing in a test system. A flexible platform may be provided for developing test programs for performing automated testing. In one such platform, the tester and its instruments are isolated from the tester operating system, permitting any tester operating system to be used. In another example implementation, a user layer of the platform is isolated from the physical layer of the architecture, permitting hardware-independent test programs that can be created and used among different testers having different test hardware and software. In yet another implementation, execution of a test program is isolated from a tester platform operating system, permitting the test program to function independent from the tester platform.

Abstract: A program conversion device for converting a program source is provided. The program conversion device comprises: a section and index acquisition device for acquiring a section code for indicating a section embedded in the program and performance index information embedded in the program in association with the section code; a task code conversion device for separating the acquired section code into task codes and adding a code to indicate the beginning of the task and a code to indicate the end of the task; and a task index attachment device for attaching a performance index, to input to the scheduler, to the task.

Abstract: This invention relates to architecture and synchronization of multi-processor computing hardware. It establishes a new method of programming, process synchronization, and of computer construction, named stress-flow by the inventor, allowing benefits of both opposing legacy concepts of programming (namely of both data-flow and control flow) within one cohesive, powerful, object-oriented scheme. This invention also relates to construction of object-oriented, parallel computer languages, script and visual, together with compiler construction and method to write programs to be executed in fully parallel (or multi-processor) architectures, virtually parallel, and single-processor multitasking computer systems.

Abstract: System and method for automatically parallelizing iterative functionality in a data flow program. A data flow program is stored that includes a first data flow program portion, where the first data flow program portion is iterative. Program code implementing a plurality of second data flow program portions is automatically generated based on the first data flow program portion, where each of the second data flow program portions is configured to execute a respective one or more iterations. The plurality of second data flow program portions are configured to execute at least a portion of iterations concurrently during execution of the data flow program. Execution of the plurality of second data flow program portions is functionally equivalent to sequential execution of the iterations of the first data flow program portion.

Abstract: A method for producing parallel computer programs by using a compilation method that produces executable computer programs having an undefined execution order. The execution order is defined during execution of the program depending on the execution architecture. This allows the best possible level of concurrent execution in different architectures. The compilation method includes producing data dependency and data flow graphs that are used for executable code generation.

Abstract: System and method for automatically parallelizing iterative functionality in a data flow program. A data flow program is stored that includes a first data flow program portion, where the first data flow program portion is iterative. Program code implementing a plurality of second data flow program portions is automatically generated based on the first data flow program portion, where each of the second data flow program portions is configured to execute a respective one or more iterations. The plurality of second data flow program portions are configured to execute at least a portion of iterations concurrently during execution of the data flow program. Execution of the plurality of second data flow program portions is functionally equivalent to sequential execution of the iterations of the first data flow program portion.

Abstract: System and method for automatically parallelizing iterative functionality in a data flow program. A data flow program is stored that includes a first data flow program portion, where the first data flow program portion is iterative. Program code implementing a plurality of second data flow program portions is automatically generated based on the first data flow program portion, where each of the second data flow program portions is configured to execute a respective one or more iterations. The plurality of second data flow program portions are configured to execute at least a portion of iterations concurrently during execution of the data flow program. Execution of the plurality of second data flow program portions is functionally equivalent to sequential execution of the iterations of the first data flow program portion.

Abstract: A general purpose high-performance distributed execution engine for coarse-grained data-parallel applications is proposed that allows developers to easily create large-scale distributed applications without requiring them to master concurrency techniques beyond being able to draw a graph of the data-dependencies of their algorithms. Based on the graph, a job manager intelligently distributes the work load so that the resources of the execution engine are used efficiently. During runtime, the job manager (or other entity) can automatically modify the graph to improve efficiency. The modifications are based on runtime information, topology of the distributed execution engine, and/or the distributed application represented by the graph.

Abstract: Ordering instructions for specifying the execution order of other instructions improve throughput in a pipelined multiprocessor. Memory write operations local to a CPU are allowed to occur in an arbitrary order, and constraints are placed on shared memory operations. Multiple sets of instructions are provided in which order of execution of the instructions is maintained through the use of CPU registers, write buffers in conjunction with assignment of sequence numbers to the instruction, or a hierarchical ordering system. The system ensures that an earlier designated instruction has reach a specified state of execution prior to a latter instruction reaching a specified state of execution. The ordering of operations allows memory operations local to a CPU to occur in conjunction with other memory operations that are not affected by such execution.

Abstract: Methods and an apparatus for forming a transaction object instruction construct are provided. An example method translates a source instruction construct to form a transactional objective instruction construct, executes the transactional objective instruction construct, intercepts an aborted transaction associated with the transactional objective instruction construct during execution, maintains a graph of nodes and edges associated with the executed transactional objective instruction construct to predict a deadlock situation, and resolves the deadlock situation associated with the transactional objective instruction construct based on the graph.

Abstract: Transactional programming promises to substantially simplify the development and maintenance of correct, scalable, and efficient concurrent programs. Designs for supporting transactional programming using transactional memory implemented in hardware, software, and a mixture of the two have emerged recently. Unfortunately, conventional debugging programs are often inadequate when employed in relation to code that employs transactional memory and new or modified techniques are needed. Implementations of delayed breakpoints are described that provide programmers with the benefits of breakpoints in transactional code, while minimizing the side-effects of breakpoints placed inside atomic block.

Abstract: A system and method for managing data, such as in a data warehousing, analysis, or similar applications, where dataflow graphs are expressed as reusable map components, at least some of which are selected from a library of components, and map components are assembled to create an integrated dataflow application. Composite map components encapsulate a dataflow pattern using other maps as subcomponents. Ports are used as link points to assemble map components and are hierarchical and composite allowing ports to contain other ports. The dataflow application may be executed in a parallel processing environment by recognizing the linked data processes within the map components and assigning threads to the linked data processes.

Abstract: A method and a computer system are disclosed for administration of medical applications running in parallel. At least one embodiment of the method includes creation of a number of application components as a result a beginning of a number of user actions; provision of a module for parallel execution and/or for coordination of the previously created application components, provision of a least one communication interface for exchanging messages and/or data between an application component and a command which is of interest to the application component which has been initiated by one of the user actions, and removal of the application component created by a user action after the user action has ended.

Abstract: Mark stack overflow list. A method may be practiced in a computing environment including application code that implements garbage collection functionality. The garbage collection functionality includes pushing object references onto a mark stack, such that objects referenced on the mark stack can be marked so as to prevent memory for the objects from being recycled for use with other objects instances. The method includes acts for handling overflows of a mark stack. The method includes accessing a reference to an object. The object is processed by attempting to enumerate references to other objects from the object onto a mark stack. An overflow condition of the mark stack is detected for a referenced other object. A reference to the referenced other object is placed on an overflow list. References from the overflow list are processed.

Abstract: A method of converting a program code of a program running in multi-thread to a program code which causes fewer lock collisions. The method includes reading the program code into a memory and searching the program code for a first conditional statement making a branch to a path, which is in a synchronized block and has no side effect on the synchronized block; duplicating the path having no side effect to which the branch is made by the searched first conditional statement into the outside of the synchronized block; and adding a second conditional statement into the program code in response to the duplication, wherein the second conditional statement is a conditional statement making a branch to the duplicated path having no side effect. Also provided is a system and an article of manufacture which causes a computer to carry out the steps of the above method.

Abstract: A code generator and multi-core framework are executable in a computer system to implement methods as disclosed herein, including a method for the code generator to automatically generate multi-threaded source code from functional specifications, and for the multi-core framework, which is a run time component, to generate multi-threaded task object code from the multi-threaded source code and to execute the multi-threaded task object code on respective processor cores. The methods provide transparency to the programmer, and during execution, provide automatic identification of processing parallelisms. The methods implement Consume-Simplify-Produce and Normalize-Transpose-Distribute operations to reduce complex expression sets in a functional specification to simplified expression sets operable in parallel processing environments through the generated multi-threaded task object code.

Abstract: A method for executing a loop in an application that includes executing iterations in a first segment of the loop by a base thread, logging memory transactions that occur during execution of iterations in the first segment by a co-inspector thread to obtain a co-inspector log, executing iterations in a second segment of the loop by a co-thread to obtain temporary results, logging memory transactions that occur during execution of iterations in the second segment to obtain a co-thread log, and comparing the co-inspector log and the co-thread log to determine whether a thread interdependency exists.

Abstract: The adaptation of at least a portion of an object provided by a previous script component to a subsequent script component, despite the subsequent component being incapable of recognizing a format of the at least a portion of the object as provided by the previous component. The previous component generates an object having a property. Adaptation script identifies adaptation(s) to perform on the property prior to being used by the subsequent component. The adaptation is performed, and the adapted property is then used by the subsequent component.

Abstract: Methods and apparatus provide for translating a software program page by page from a first instruction set architecture (ISA) into a second ISA using one or more of a set of processors of a multi-processor system; and executing the translated software program using a dedicated other processor of the multi-processor system.

Abstract: The latencies associated with retrieving instruction information for a main thread are decreased through the use of a simultaneous helper thread. The helper thread is a speculative prefetch thread to perform instruction prefetch and/or trace pre-build for the main thread.

Abstract: Computer-implemented methods, computer systems and computer program products are provided for parallel processing a plurality of data objects with a plurality of processors. As disclosed herein, the data objects to be assembled for further processing may be in bundles, the bundles obeying first predefined criteria, which is dynamically controlled by using a bundle specific master table. The methods and systems may generate pipelines of data objects by pre-selecting and grouping the data objects according to second predefined criteria by a first group of the plurality of processors, and create the bundles from each pipeline of the pre-selected data objects by a second group of the plurality of processors.

Abstract: Method, apparatus and system embodiments to provide user-level creation, control and synchronization of OS-invisible “shreds” of execution via an abstraction layer for a system that includes one or more sequencers that are sequestered from operating system control. For at least one embodiment, the abstraction layer provides sequestration logic, proxy execution logic, transition detection and shred suspension logic, and sequencer arithmetic logic. Other embodiments are also described and claimed.

Abstract: A method for resolving a type in a programming language to a resolve stage is provided. The method includes determining whether a version at the resolve stage of the type exists. The method further includes, if the version at the resolve stage does not exist, allowing a thread exclusive access to the type, resolving the type from an original resolve stage to the resolve stage, by the thread, by adding resolution information for the resolve stage to the type, and creating the version of the type based on the resolving by creating a copy of the type, where the copy of the type is at the resolve stage. Two or more versions are associated with the type, and the two or more versions are at different resolve stages.

Abstract: A program stored in a storage device is read. Partial compression, in the element in an array in a loop nest in the program, is performed by replacing an element local only in the loop nest in the entire program with a scalar variable. Access to an original array is inserted into a program for an non-local element.

Abstract: A method for committing memory transactions in an application that includes executing a plurality of sections of the application in parallel, logging a plurality of memory transactions that occur while executing the plurality of sections to obtain a plurality of logs and a plurality of temporary results, wherein the plurality of memory transactions that includes a plurality of writes to at least one memory location, comparing the plurality of logs to identify an optimal list of writes from the plurality of writes, and committing memory transactions corresponding to a subset of the plurality of temporary results, wherein the subset of the plurality of temporary results is identified by the optimal list of writes.

Abstract: Systems and methods are described for automatically transforming essentially sequential code into a plurality of codes which are to be executed in parallel to achieve the same or equivalent result to the sequential code. User-defined task boundaries are determined in the input code to thereby define a plurality of tasks. It is then determined if the essentially sequential application code can be separated at at least one of said user-defined tasks boundaries and if so at least one code of the plurality of codes for at least one of said tasks is automatically generated.