On An Electrically Conducting, Semi-conducting, Or Semi-insulating Substrate Patents (Class 977/720)
  • Patent number: 8853526
    Abstract: Photovoltaic devices are driven by intense photoemission of “hot” electrons from a suitable nanostructured metal. The metal should be an electron source with surface plasmon resonance within the visible and near-visible spectrum range (near IR to near UV (about 300 to 1000 nm)). Suitable metals include silver, gold, copper and alloys of silver, gold and copper with each other. Silver is particularly preferred for its advantageous opto-electronic properties in the near UV and visible spectrum range, relatively low cost, and simplicity of processing.
    Type: Grant
    Filed: July 17, 2008
    Date of Patent: October 7, 2014
    Assignee: The Regents of The University of California
    Inventors: Robert Kostecki, Samuel Mao
  • Patent number: 8846530
    Abstract: To provide a method for manufacturing a power storage device which enables improvement in performance of the power storage device, such as an increase in discharge capacity. To provide a method for forming a semiconductor region which is used for a power storage device or the like so as to improve performance. A method for forming a crystalline semiconductor region includes the steps of: forming, over a conductive layer, a crystalline semiconductor region that includes a plurality of whiskers including a crystalline semiconductor by an LPCVD method; and performing heat treatment on the crystalline semiconductor region after supply of a source gas containing a deposition gas including silicon is stopped. A method for manufacturing a power storage device includes the step of using the crystalline semiconductor region as an active material layer of the power storage device.
    Type: Grant
    Filed: June 13, 2011
    Date of Patent: September 30, 2014
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Makoto Furuno, Takashi Shimazu
  • Patent number: 8809672
    Abstract: The present disclosure provides a catalyst-free growth mode of defect-free Gallium Arsenide (GaAs)-based nanoneedles on silicon (Si) substrates with a complementary metal-oxide-semiconductor (CMOS)-compatible growth temperature of around 400° C. Each nanoneedle has a sharp 2 to 5 nanometer (nm) tip, a 600 nm wide base and a 4 micrometer (?m) length. Thus, the disclosed nanoneedles are substantially hexagonal needle-like crystal structures that assume a 6° to 9° tapered shape. The 600 nm wide base allows the typical micro-fabrication processes, such as optical lithography, to be applied. Therefore, nanoneedles are an ideal platform for the integration of optoelectronic devices on Si substrates. A nanoneedle avalanche photodiode (APD) grown on silicon is presented in this disclosure as a device application example. The APD attains a high current gain of 265 with only 8V bias.
    Type: Grant
    Filed: May 27, 2010
    Date of Patent: August 19, 2014
    Assignee: The Regents of the University of California
    Inventors: Chih-Wei Chuang, Connie Chang-Hasnain, Forrest Grant Sedgwick, Wai Son Ko
  • Patent number: 8779411
    Abstract: The present disclosure provides a light emitting diode and a method of manufacturing the same. The light emitting diode includes a graphene layer on a second conductive semiconductor layer and a plurality of metal nanoparticles formed on some region of the graphene layer, whereby adhesion between the second conductive semiconductor layer comprised of an inorganic material and the graphene layer is enhanced, thereby securing stability and reliability of the light emitting diode. In addition, the light emitting diode allows uniform spreading of electric current, thereby allowing stable emission of light through a surface area of the light emitting diode.
    Type: Grant
    Filed: November 16, 2012
    Date of Patent: July 15, 2014
    Assignee: Gwanju Institute of Science and Technology
    Inventors: Dong Seon Lee, Jae Phil Shim, Seong Ju Park, Min Hyeok Choe, Do Hyung Kim, Tak Hee Lee
  • Patent number: 8771405
    Abstract: A gas filter comprises a housing (30) having a gas inlet (55), a gas outlet (65) and at least one chamber (70) therebetween containing carbon nanotubes (110). The chamber (70) has a port (90) and is configured for simultaneous gas ingress to and gas egress from the carbon nanotubes (110) through the port (90).
    Type: Grant
    Filed: March 29, 2011
    Date of Patent: July 8, 2014
    Inventor: Dimitris Drikakis
  • Patent number: 8699206
    Abstract: Methods and apparatus for storing information or energy. An array of nano vacuum tubes is evacuated to a pressure below 10?6 Torr, where each nano vacuum tube has an anodic electrode, a cathodic electrode spaced apart from the anodic electrode, and an intervening evacuated region. An excess of electrons is stored on the cathodic electrode.
    Type: Grant
    Filed: October 20, 2010
    Date of Patent: April 15, 2014
    Assignee: The Board of Trustees of the University of Illinois
    Inventors: Alfred W. Hubler, Onyeama Osuagwu
  • Patent number: 8691672
    Abstract: A method is provided for consuming oxides in a silicon (Si) nanoparticle film. The method forms a colloidal solution film of Si nanoparticles overlying a substrate. The Si nanoparticle colloidal solution film is annealed at a high temperature in the presence of titanium (Ti). In response to the annealing, Si oxide is consumed in a resultant Si nanoparticle film. In one aspect, the consuming the Si oxide in the Si nanoparticle film includes forming Ti oxide in the Si nanoparticle film. Also in response to a low temperature annealing, solvents are evaporated in the colloidal solution film of Si nanoparticles. Si and Ti oxide molecules are sintered in the Si nanoparticle film in response to the high temperature annealing.
    Type: Grant
    Filed: March 28, 2012
    Date of Patent: April 8, 2014
    Assignee: Sharp Laboratories of America, Inc.
    Inventors: Themistokles Afentakis, Karen Yuri Nishimura
  • Patent number: 8666547
    Abstract: Cellular automotion digital material is useable for rapid prototyping and fabrication of continuous string conformations and two- or three-dimensional shapes through actuation of a string, surface, or volume composed of identical discrete units. Each unit is an actuated joint having a single degree of freedom. The actuated joint includes a two-part actuator having an inner active portion and an outer passive portion that are controllably rotatable relative to each other, the outer portion being configured to fit within the housing of an adjacent cellular automotion unit, and a linkage element that includes a main strut and a housing and is connected to the actuator by a pin connector.
    Type: Grant
    Filed: March 25, 2010
    Date of Patent: March 4, 2014
    Assignee: Massachusetts Institute of Technology
    Inventors: Kenneth C. Cheung, Ara Knaian, Neil Gershenfeld
  • Patent number: 8580586
    Abstract: A memory array includes a plurality of memory cells, each of which receives a bit line, a first word line, and a second word line. Each memory cell includes a cell selection circuit, which allows the memory cell to be selected. Each memory cell also includes a two-terminal switching device, which includes first and second conductive terminals in electrical communication with a nanotube article. The memory array also includes a memory operation circuit, which is operably coupled to the bit line, the first word line, and the second word line of each cell. The circuit can select the cell by activating an appropriate line, and can apply appropriate electrical stimuli to an appropriate line to reprogrammably change the relative resistance of the nanotube article between the first and second terminals. The relative resistance corresponds to an informational state of the memory cell.
    Type: Grant
    Filed: January 15, 2009
    Date of Patent: November 12, 2013
    Assignee: Nantero Inc.
    Inventors: Claude L. Bertin, Frank Guo, Thomas Rueckes, Steven L. Konsek, Mitchell Meinhold, Max Strasburg, Ramesh Sivarajan, X. M. Henry Huang
  • Patent number: 8569615
    Abstract: Provided are solar cells and methods of forming the same. The solar cell includes an anti-reflection layer on a substrate, a first electrode on the anti-reflection layer, a photo-electro conversion layer on the first electrode, and a second electrode on the photo-electro conversion layer.
    Type: Grant
    Filed: January 27, 2011
    Date of Patent: October 29, 2013
    Assignee: Electronics and Telecommunications Research Institute
    Inventors: Mi Hee Jung, Mangu Kang
  • Patent number: 8541810
    Abstract: A semiconductor nanocrystal includes a core including a first semiconductor material and an overcoating including a second semiconductor material. A monodisperse population of the nanocrystals emits blue light over a narrow range of wavelengths with a high quantum efficiency.
    Type: Grant
    Filed: November 16, 2011
    Date of Patent: September 24, 2013
    Assignee: Massachusettts Institute of Technology
    Inventors: Jonathan S. Steckel, John P. Zimmer, Seth Coe-Sullivan, Nathan E. Stott, Vladimir Bulović, Moungi G. Bawendi
  • Patent number: 8536015
    Abstract: In accordance with aspects of the invention, a method of forming a metal-insulator-metal stack is provided. The method includes forming a first conducting layer, forming a resistivity-switching carbon-based material above the first conducting layer, and forming a second conducting layer above the carbon-based material, wherein the carbon-based material has a thickness of not more than ten atomic layers. Other aspects are also described.
    Type: Grant
    Filed: January 17, 2012
    Date of Patent: September 17, 2013
    Assignee: SanDisk 3D LLC
    Inventors: Roy E. Scheuerlein, Alper Ilkbahar, April D. Schricker
  • Patent number: 8450724
    Abstract: A device is provided by use of a helical substituted polyacetylene. The device comprises a structure comprised of a helical substituted polyacetylene having a helical main chain, and a pair of electrodes for applying a voltage or electric current to the structure, wherein the molecule of the helical substituted polyacetylene has a length larger than the distance between the pair of the electrodes.
    Type: Grant
    Filed: September 21, 2007
    Date of Patent: May 28, 2013
    Assignee: Canon Kabushiki Kaisha
    Inventors: Takeyuki Sone, Akira Kuriyama, Koji Yano, Otto Albrecht, Masayoshi Tabata
  • Patent number: 8445895
    Abstract: An organic electroluminescence element having a cathode as a top electrode, and excelling in luminance efficiency, drive voltage, and operational life is provided. The organic electroluminescence element includes an anode over a substrate and a luminescent layer over the anode. The luminescent layer comprises an organic material. An electron injection layer is over the luminescent layer for injecting electrons into the luminescent layer. The electron injection layer is a metal including at least one of an alkaline metal and an alkaline earth metal. A fullerene layer is over the electron injection layer and includes fullerenes and at least one of an alkaline metal and an alkaline earth metal. The at least one of the alkaline metal and the alkaline earth metal included in the fullerene layer has a lower work function than a lowest unoccupied molecular orbit energy level of the fullerenes. A cathode is over the fullerene layer.
    Type: Grant
    Filed: June 1, 2010
    Date of Patent: May 21, 2013
    Assignees: Panasonic Corporation, Cambridge Display Technology Ltd.
    Inventors: Kenji Okumoto, Jeremy Burroughes, Julian Carter
  • Patent number: 8431817
    Abstract: Nanostructure array optoelectronic devices are disclosed. The optoelectronic device may be a multi junction solar cell. The optoelectronic device may have a bi-layer electrical interconnect that is physically and electrically connected to sidewalls of the array of nanostructures. The optoelectronic device may be operated as a multi junction solar cell, wherein each junction is associated with one portion of the device. The bi-layer electrical interconnect allows current to pass from one portion to the next. Thus, the bi-layer electrical interconnect may serve as a replacement for a tunnel junction, which is used in some conventional multi junction solar cells.
    Type: Grant
    Filed: June 8, 2010
    Date of Patent: April 30, 2013
    Assignee: Sundiode Inc.
    Inventors: James C. Kim, Sungsoo Yi, Danny E. Mars
  • Patent number: 8426722
    Abstract: Photovoltaic structures for the conversion of solar irradiance into electrical free energy. In a particular implementation, a photovoltaic cell includes a granular semiconductor and oxide layer with nanometer-size absorber semiconductor grains surrounded by a matrix of oxide. The semiconductor and oxide layer is disposed between electron and hole conducting layers. In some implementations, multiple semiconductor and oxide layers can be deposited.
    Type: Grant
    Filed: October 24, 2007
    Date of Patent: April 23, 2013
    Assignee: Zetta Research and Development LLC—AQT Series
    Inventors: Mariana R. Munteanu, Erol Girt
  • Patent number: 8414831
    Abstract: A chlorine gas sensor system includes carbon nanotubes at least partially coated with a metal oxide deposited on a substrate, and a source of infra-red light positioned to illuminate at least a portion of the coated nanotubes.
    Type: Grant
    Filed: June 10, 2009
    Date of Patent: April 9, 2013
    Assignee: The University of Toledo
    Inventor: Ahalapitiya H. Jayatissa
  • Patent number: 8405063
    Abstract: A component including a substrate, at least one layer including a color conversion material including quantum dots disposed over the substrate, and a layer including a conductive material (e.g., indium-tin-oxide) disposed over the at least one layer. (Embodiments of such component are also referred to herein as a QD light-enhancement substrate (QD-LES).) In certain preferred embodiments, the substrate is transparent to light, for example, visible light, ultraviolet light, and/or infrared radiation. In certain embodiments, the substrate is flexible. In certain embodiments, the substrate includes an outcoupling element (e.g., a microlens array). A film including a color conversion material including quantum dots and a conductive material is also provided. In certain embodiments, a component includes a film described herein. Lighting devices are also provided. In certain embodiments, a lighting device includes a film described herein.
    Type: Grant
    Filed: January 20, 2010
    Date of Patent: March 26, 2013
    Assignee: QD Vision, Inc.
    Inventors: Peter T. Kazlas, Seth Coe-Sullivan
  • Patent number: 8373060
    Abstract: Photovoltaic structures for the conversion of solar irradiance into electrical free energy. In particular implementations, the novel photovoltaic structures can be fabricated using low cost and scalable processes, such as magnetron sputtering. In a particular implementation, a photovoltaic cell includes a photoactive conversion layer comprising one or more granular semiconductor and oxide layers with nanometer-size semiconductor grains surrounded by a matrix of oxide. The semiconductor and oxide layer can be a disposed between electrode layers. In some implementations, multiple semiconductor and oxide layers can be deposited. These so-called semiconductor and oxide layers absorb sun light and convert solar irradiance into electrical free energy.
    Type: Grant
    Filed: October 24, 2007
    Date of Patent: February 12, 2013
    Assignee: Zetta Research and Development LLC—AQT Series
    Inventors: Mariana R. Munteanu, Erol Girt
  • Patent number: 8358010
    Abstract: A method for realizing a nanometric circuit architecture includes: realizing plural active areas on a semiconductor substrate; realizing on the substrate a seed layer of a first material; realizing a mask-spacer of a second material on the seed layer in a region comprised between the active areas; realizing a mask overlapping the mask-spacer and extending in a substantially perpendicular direction thereto; selectively removing the seed layer exposed on the substrate; selectively removing the mask and the mask-spacer obtaining a seed-spacer comprising a linear portion extending in that region and a portion substantially orthogonal thereto; realizing by MSPT from the seed-spacer an insulating spacer reproducing at least part of the profile of the seed-spacer; realizing by MSPT a nano-wire of conductive material from the seed-spacer or insulating spacer, the nano-wire comprising a first portion at least partially extending in the region and a second portion contacting a respective active area.
    Type: Grant
    Filed: February 28, 2005
    Date of Patent: January 22, 2013
    Assignee: STMicroelectronics S.r.l.
    Inventors: Danilo Mascolo, Gianfranco Cerofolini
  • Patent number: 8323488
    Abstract: Embodiments in accordance with the present invention relate to packed-column nano-liquid chromatography (nano-LC) systems integrated on-chip, and methods for producing and using same. The microfabricated chip includes a column, flits/filters, an injector, and a detector, fabricated in a process compatible with those conventionally utilized to form integrated circuits. The column can be packed with supports for various different stationary phases to allow performance of different forms of nano-LC, including but not limited to reversed-phase, normal-phase, adsorption, size-exclusion, affinity, and ion chromatography. A cross-channel injector injects a nanolitre/picolitre-volume sample plug at the column inlet. An electrochemical/conductivity sensor integrated at the column outlet measures separation signals.
    Type: Grant
    Filed: February 28, 2011
    Date of Patent: December 4, 2012
    Assignees: California Institute of Technology, City of Hope
    Inventors: Yu-Chong Tai, Qing He, Jun Xie, Changlin Pang, Terry D. Lee, Damien Rodger, Matthieu Liger
  • Publication number: 20120258445
    Abstract: Methods for using nanowire sensors are described. In one embodiment, the nanowire sensor may be field effect transistor having a nanowire and a functionalized control electrode. One method of using such a nanowire sensor includes exposing the functionalized control electrode to a test sample and an enhancing reagent. In another embodiment, the nanowire sensor may be a field effect transistor having a gate electrode and a functionalized nanowire. One method of using such a nanowire sensor includes exposing the functionalized nanowire to a test sample and an enhancing reagent. The use of an enhancing reagent increases the sensitivity of the nanowire sensor to a substance to be detected or quantified.
    Type: Application
    Filed: April 12, 2012
    Publication date: October 11, 2012
    Applicant: NanolVD, Inc.
    Inventors: Sunnie Park KIM, Young Shik SHIN, Changgeng LIU
  • Patent number: 8241939
    Abstract: A method for manufacturing a biosensor includes forming a silicon nanowire channel, etching a first conductivity-type single crystalline silicon layer which is a top layer of a Silicon-On-Insulator (SOI) substrate to form a first conductivity-type single crystalline silicon line pattern, doping both sidewalls of the first conductivity-type single crystalline silicon line pattern with impurities of a second conductivity-type opposite to the first conductivity-type to form a second conductivity-type channel, forming second conductivity-type pads for forming electrodes at both ends of the first conductivity-type single crystalline silicon line pattern, forming, in an undoped region of the first conductivity-type single crystalline silicon line pattern, a first electrode for applying a reverse-bias voltage to insulate the first conductivity-type single crystalline silicon line pattern and the second conductivity-type channel from each other, and forming second electrodes for applying a bias voltage across the sec
    Type: Grant
    Filed: July 24, 2008
    Date of Patent: August 14, 2012
    Assignee: Electronics and Telecommunications Research Institute
    Inventors: Chan Woo Park, Chang Geun Ahn, Jong Heon Yang, In Bok Baek, Chil Seong Ah, Han Young Yu, An Soon Kim, Tae Youb Kim, Moon Gyu Jang, Myung Sim Jun
  • Publication number: 20120181507
    Abstract: A semiconductor structure including an ordered array of parallel graphene nanoribbons located on a surface of a semiconductor substrate is provided using a deterministically assembled parallel set of nanowires as an etch mask. The deterministically assembled parallel set of nanowires is formed across a gap present in a patterned graphene layer utilizing an electric field assisted assembly process. A semiconductor device, such as a field effect transistor, can be formed on the ordered array of parallel graphene nanoribbons.
    Type: Application
    Filed: January 19, 2011
    Publication date: July 19, 2012
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Christos D. Dimitrakopoulos, Alfred Grill, Timothy J. McArdle
  • Patent number: 8216364
    Abstract: Direct resistive heating is used to grow nanotubes out of carbon and other materials. A growth-initiated array of nanotubes is provided using a CVD or ion implantation process. These processes use indirect heating to heat the catalysts to initiate growth. Once growth is initiated, an electrical source is connected between the substrate and a plate above the nanotubes to source electrical current through and resistively heat the nanotubes and their catalysts. A material source supplies the heated catalysts with carbon or another material to continue growth of the array of nanotubes. Once direct heating has commenced, the source of indirect heating can be removed or at least reduced. Because direct resistive heating is more efficient than indirect heating the total power consumption is reduced significantly.
    Type: Grant
    Filed: April 14, 2008
    Date of Patent: July 10, 2012
    Assignee: Raytheon Company
    Inventors: Delmar L. Barker, Mead M. Jordan, William R. Owens
  • Patent number: 8206505
    Abstract: The inventive method for forming nano-dimensional clusters consists in introducing a solution containing a cluster-forming material into nano-pores of natural or artificial origin contained in a substrate material and in subsequently exposing said solution to a laser radiation pulse in such a way that a low-temperature plasma producing a gaseous medium in the domain of the existence thereof, wherein a cluster material is returned to a pure material by the crystallization thereof on a liquid substrate while the plasma is cooling, occurs, thereby forming mono-crystal quantum dots spliced with the substrate material. Said method makes it possible to form two- or three-dimensional cluster lattices and clusters spliced with each other from different materials. The invention also makes it possible to produce wires from different materials in the substrate nano-cavities and the quantum dots from the solution micro-drops distributed through an organic material applied to a glass.
    Type: Grant
    Filed: November 29, 2005
    Date of Patent: June 26, 2012
    Inventors: Sergei Nikolaevich Maximovsky, Grigory Avramovich Radutsky
  • Patent number: 8193055
    Abstract: Techniques are provided for fabricating memory with metal nanodots as charge-storing elements. In an example approach, metal salt ions are added to a core of a copolymer solution. A metal salt reduction causes the metal atoms to aggregate in the core, forming a metal nanodot. The copolymer solution is applied to a gate oxide on a substrate using spin coating or dip coating. Due to the copolymer configuration, the nanodots are held in a uniform 2D grid on the gate oxide. The polymers are selected to provide a desired nanodot size and spacing between nanodots. A polymer cure and removal process leaves the nanodots on the gate oxide. In a configuration using a control gate over a high-k dielectric floating gate which includes the nanodots, the control gates may be separated by etching while the floating gate dielectric extends uninterrupted since the nanodots are electrically isolated from one another.
    Type: Grant
    Filed: December 18, 2007
    Date of Patent: June 5, 2012
    Assignee: SanDisk Technologies Inc.
    Inventors: Vinod Robert Purayath, George Matamis, Takashi Orimoto, James Kai, Tuan D. Pham
  • Patent number: 8193455
    Abstract: An electrical circuit structure employing graphene as a charge carrier transport layer. The structure includes a plurality of graphene layers. Electrical contact is made with one of the layer of the plurality of graphene layers, so that charge carriers travel only through that one layer. By constructing the active graphene layer within or on a plurality of graphene layers, the active graphene layer maintains the necessary planarity and crystalline integrity to ensure that the high charge carrier mobility properties of the active graphene layer remain intact.
    Type: Grant
    Filed: December 30, 2008
    Date of Patent: June 5, 2012
    Assignee: Hitachi Global Storage Technologies Netherlands B.V.
    Inventor: Ernesto E. Marinero
  • Patent number: 8189635
    Abstract: A laser diode having nano patterns is disposed on a substrate. A first conductive-type clad layer is disposed on the substrate, and a second conductive-type clad layer is disposed on the first conductive-type clad layer. An active layer is interposed between the first conductive-type clad layer and the second conductive-type clad layer. Column-shaped nano patterns are arranged at a surface of the second conductive-type clad layer to form a laser diode such as a distributed feedback laser diode.
    Type: Grant
    Filed: April 27, 2010
    Date of Patent: May 29, 2012
    Assignees: Seoul Opto Device Co., Ltd., The University of Tokushima
    Inventor: Shiro Sakai
  • Patent number: 8183576
    Abstract: Light-emitting diodes, and methods of manufacturing the light-emitting diode, are provided wherein a plurality of nano-rods may be formed on a reflection electrode. The plurality of nano-rods extend perpendicularly from an upper surface of the reflection electrode. Each of the nano-rods includes a first region doped with a first type dopant, a second region doped with a second type dopant that is an opposite type to the first type dopant, and an active region between the first region and the second region. A transparent insulating layer may be formed between the plurality of nano-rods. A transparent electrode may be formed on the plurality of nano-rods and the transparent insulating layer.
    Type: Grant
    Filed: April 14, 2009
    Date of Patent: May 22, 2012
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Bokki Min, Youngsoo Park, Taek Kim, Junyoun Kim
  • Patent number: 8169085
    Abstract: A semiconductor device according to one embodiment includes: a substrate; a wiring provided above the substrate and including a graphene nanoribbon layer comprising a plurality of laminated graphene nanoribbon sheets; and a wiring connecting member penetrating at least one of the plurality of graphene nanoribbon sheets for connecting the wiring and a conductive member above or below the wiring.
    Type: Grant
    Filed: January 29, 2010
    Date of Patent: May 1, 2012
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Yousuke Akimoto, Makoto Wada
  • Patent number: 8158880
    Abstract: Photovoltaic structures for the conversion of solar irradiance into electrical free energy. In a particular implementation, a photovoltaic cell includes a granular semiconductor and oxide layer with nanometer-size absorber semiconductor grains surrounded by a matrix of oxide. The semiconductor and oxide layer may be disposed between electron and hole conducting layers. In some implementations, multiple semiconductor and oxide layers can be deposited.
    Type: Grant
    Filed: January 17, 2008
    Date of Patent: April 17, 2012
    Assignee: AQT Solar, Inc.
    Inventors: Erol Girt, Mariana Rodica Munteanu
  • Patent number: 8125075
    Abstract: A method, apparatus and system with a semiconductor package including a microchimney or thermosiphon using carbon nanotubes to modify the effective thermal conductivity of an integrated circuit die.
    Type: Grant
    Filed: January 15, 2008
    Date of Patent: February 28, 2012
    Assignee: Intel Corporation
    Inventors: James G. Maveety, Gregory M. Chrysler, Unnikrishnan Vadakkanmaruveedu
  • Patent number: 8110476
    Abstract: In accordance with aspects of the invention, a method of forming a memory cell is provided, the method including forming a steering element above a substrate, and forming a memory element coupled to the steering element, wherein the memory element comprises a carbon-based material having a thickness of not more than ten atomic layers. The memory element may be formed by repeatedly performing the following steps: forming a layer of a carbon-based material, the layer having a thickness of about one monolayer, and subjecting the layer of carbon-based material to a thermal anneal. Other aspects are also described.
    Type: Grant
    Filed: April 6, 2009
    Date of Patent: February 7, 2012
    Assignee: SanDisk 3D LLC
    Inventors: Roy E. Scheuerlein, Alper Ilkbahar, April D. Shricker
  • Patent number: 8106510
    Abstract: A semiconductor structure having: an electrically and thermally conductive layer disposed on one surface of the semiconductor structure; an electrically and thermally conductive heat sink; a electrically and thermally conductive carrier layer; a plurality of electrically and thermally nano-tubes, a first portion of the plurality of nano-tubes having proximal ends disposed on a first surface of the carrier layer and a second portion of the plurality of nano-tubes having proximal ends disposed on an opposite surface of the carrier layer; and a plurality of electrically and thermally conductive heat conductive tips disposed on distal ends of the plurality of nano-tubes, the plurality of heat conductive tips on the first portion of the plurality of nano-tubes being attached to the conductive layer, the plurality of heat conductive tips on the second portion of the plurality of nano-tubes being attached to the heat sink.
    Type: Grant
    Filed: August 4, 2009
    Date of Patent: January 31, 2012
    Assignee: Raytheon Company
    Inventors: David H. Altman, Erik F. Nordhausen, Steven D. Bernstein, Robert P. Molfino, Steven B. Wakefield
  • Patent number: 8088282
    Abstract: Disclosed herein are an apparatus and a method for separating molecules on the basis of size and or structure, and to a method of making the apparatus. Generally, the separation method includes passing a fluid comprising particles having different effective molecular diameters through a plurality of open, nanoscale channels disposed in surfaces of substrates. The method also includes obtaining a plurality of fractions of the passed fluid such that each of the fractions includes a major portion containing particles having similar size and shape and substantially free of particles having larger size and shape. The apparatus includes first and second substrates each of which has a surface containing a plurality of open, nanoscale channels disposed therein. The surfaces are bonded together such that each of the channels of the first substrate is in fluid communication with at least two of the channels of the second substrate and is misaligned relative to the channels of the second substrate.
    Type: Grant
    Filed: February 9, 2011
    Date of Patent: January 3, 2012
    Assignee: Intel Corporation
    Inventor: Scott Sibbett
  • Patent number: 8044382
    Abstract: A light-emitting device includes an n-type silicon thin film (2), a silicon thin film (3), and a p-type silicon thin film (4). The silicon thin film (3) is formed on the n-type silicon thin film (2) and the p-type silicon thin film (4) is formed on the silicon thin film (3). The n-type silicon thin film (2), the silicon thin film (3), and the p-type silicon thin film (4) form a pin junction. The n-type silicon thin film (2) includes a plurality of quantum dots (21) composed of n-type Si. The silicon thin film (3) includes a plurality of quantum dots (31) composed of p-type Si. The p-type silicon thin film (4) includes a plurality of quantum dots (41) composed of p-type Si. Electrons are injected from the n-type silicon thin film (2) side and holes are injected from the p-type silicon thin film (4) side, whereby light is emitted at a silicon nitride film (3).
    Type: Grant
    Filed: March 26, 2008
    Date of Patent: October 25, 2011
    Assignee: Hiroshima University
    Inventors: Shin Yokoyama, Yoshiteru Amemiya
  • Patent number: 8044750
    Abstract: A nano-resonator including a beam having a composite structure may include a silicon carbide beam and/or a metal conductor. The metal conductor may be vapor-deposited on the silicon carbide beam. The metal conductor may have a density lower than a density of the silicon carbide beam.
    Type: Grant
    Filed: February 28, 2008
    Date of Patent: October 25, 2011
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Seong Chan Jun, Sun Il Kim, Chan Wook Baik
  • Patent number: 8003883
    Abstract: A photovoltaic device that includes a substrate and a nanowall structure disposed on the substrate surface. The device also includes at least one layer conformally deposited over the nanowall structure. The conformal layer(s) is at least a portion of a photoactive junction. A method for making a photovoltaic device includes generating a nanowall structure on a substrate surface and conformally depositing at least one layer over the nanowall structure thereby forming at least one photoactive junction. A solar panel includes at least one photovoltaic device based on a nanowall structure. The solar panel isolates such devices from its surrounding atmospheric environment and permits the generation of electrical power. Optoelectronic device may also incorporate a photovoltaic device based on a nanowall structure.
    Type: Grant
    Filed: January 11, 2007
    Date of Patent: August 23, 2011
    Assignee: General Electric Company
    Inventors: Bastiaan Arie Korevaar, Loucas Tsakalakos, Joleyn Balch
  • Patent number: 7977568
    Abstract: A photovoltaic device includes a substrate having at least two surfaces and a multilayered film disposed on at least a portion of at least one surface of the substrate. Elongated nanostructures are disposed on the multilayered film. The device incorporates a top layer of the multilayered film contacting the elongated nanostructures that is a tunnel junction. The device has at least one layer deposited over the elongated nanostructures defining a portion of a photoactive junction. A solar panel includes at least one photovoltaic device. The solar panel isolates each such devices from its surrounding atmospheric environment and permits the generation of electrical power.
    Type: Grant
    Filed: January 11, 2007
    Date of Patent: July 12, 2011
    Assignee: General Electric Company
    Inventors: Bastiaan Arie Korevaar, Loucas Tsakalakos
  • Patent number: 7964143
    Abstract: A nanotube device and a method of depositing nanotubes for device fabrication are disclosed. The method relates to electrophoretic deposition of nanotubes, and allows a control of the number of deposited nanotubes and positioning within a defined region.
    Type: Grant
    Filed: June 20, 2007
    Date of Patent: June 21, 2011
    Assignee: New Jersey Institute of Technology
    Inventors: Reginald Conway Farrow, Amit Goyal, Zafar Iqbal, Sheng Liu
  • Patent number: 7947542
    Abstract: A method for making a thin film transistor, the method comprising the steps of: (a) providing a carbon nanotube array and an insulating substrate; (b) pulling out a carbon nanotube film from the carbon nanotube array by using a tool; (c) placing at least one carbon nanotube film on a surface of the insulating substrate, to form a carbon nanotube layer thereon; (d) forming a source electrode and a drain electrode; wherein the source electrode and the drain electrode being spaced therebetween, and electrically connected to the carbon nanotube layer; and (e) covering the carbon nanotube layer with an insulating layer, and a gate electrode being located on the insulating layer.
    Type: Grant
    Filed: April 2, 2009
    Date of Patent: May 24, 2011
    Assignees: Tsinghua University, Hon Hai Precision Industry Co., Ltd.
    Inventors: Kai Liu, Kai-Li Jiang, Shou-Shan Fan
  • Publication number: 20110080006
    Abstract: A method for generating power from water by pressure retarded osmosis comprises the steps of: pumping sea water into a first pathway which is at least partially defined by a first face of a membrane, said membrane comprising a distinct electrically conductive porous nanotube layer; pumping fresh water into a second pathway which is at least partially defined by a second face of the membrane to generate an osmotic pressure gradient across the membrane; and harnessing the power generated from the osmotic pressure gradient.
    Type: Application
    Filed: October 5, 2010
    Publication date: April 7, 2011
    Inventors: Werner Blau, Ramesh Padamati, Anna Drury
  • Patent number: 7906026
    Abstract: Disclosed herein are an apparatus and a method for separating molecules on the basis of size and or structure, and to a method of making the apparatus. Generally, the separation method includes passing a fluid comprising particles having different effective molecular diameters through a plurality of open, nanoscale channels disposed in surfaces of substrates. The method also includes obtaining a plurality of fractions of the passed fluid such that each of the fractions includes a major portion containing particles having similar size and shape and substantially free of particles having larger size and shape. The apparatus includes first and second substrates each of which has a surface containing a plurality of open, nanoscale channels disposed therein. The surfaces are bonded together such that each of the channels of the first substrate is in fluid communication with at least two of the channels of the second substrate and is misaligned relative to the channels of the second substrate.
    Type: Grant
    Filed: December 1, 2008
    Date of Patent: March 15, 2011
    Assignee: Intel Corporation
    Inventor: Scott Sibbett
  • Patent number: 7906316
    Abstract: A molecular sensor includes a membrane layer having parallel pores extending through the membrane layer and incorporating therein probe molecules that bind with corresponding target molecules when present in the pores, electrodes, and an ionic solution in contact with the electrodes and the pores, wherein the electrodes are energized to induce an electrical current in the solution through the pores, wherein the electrical current induces an electrical parameter in the electrodes that is indicative of a through-pore electrical impedance of the pores, wherein the through-pore electrical impedance is increased when there is probe-to-target molecule binding in the pores relative to when there is an absence of such binding.
    Type: Grant
    Filed: July 7, 2008
    Date of Patent: March 15, 2011
    Assignee: The Johns Hopkins University
    Inventor: Stergios Papadakis
  • Publication number: 20110042683
    Abstract: Disclosed herein is an article comprising a substrate; an interlayer comprising aluminum nitride, gallium nitride, boron nitride, indium nitride or a solid solution of aluminum nitride, gallium nitride, boron nitride and/or indium nitride; the interlayer being directly disposed upon the substrate and in contact with the substrate; where the interlayer comprises a columnar film and/or nanorods and/or nanotubes; and a group-III nitride layer disposed upon the interlayer; where the group-III nitride layer completely covers a surface of the interlayer that is opposed to a surface in contact with the substrate; the group-III nitride layer being free from cracks.
    Type: Application
    Filed: August 23, 2010
    Publication date: February 24, 2011
    Applicant: UNIVERSITY OF FLORIDA RESEARCH FOUNDATION, INC.
    Inventors: Olga Kryliouk, Timothy J. Anderson
  • Patent number: 7893348
    Abstract: In some embodiments, the present invention is directed to photovoltaic (PV) devices comprising silicon (Si) nanowires as active PV elements, wherein such devices are typically thin film Si solar cells. Generally, such solar cells are of the p-i-n type and can be fabricated for front and/or backside (i.e., top and/or bottom) illumination. Additionally, the present invention is also directed at methods of making and using such devices, and to systems and modules (e.g., solar panels) employing such devices.
    Type: Grant
    Filed: August 25, 2006
    Date of Patent: February 22, 2011
    Assignee: General Electric Company
    Inventors: Bastiaan Arie Korevaar, Loucas Tsakalakos
  • Patent number: 7893492
    Abstract: A semiconductor structure is provided that includes a plurality of vertically stacked and vertically spaced apart semiconductor nanowires (e.g., a semiconductor nanowire mesh) located on a surface of a substrate. One end segment of each vertically stacked and vertically spaced apart semiconductor nanowires is connected to a source region and another end segment of each vertically stacked and vertically spaced apart semiconductor nanowires is connected to a drain region. A gate region including a gate dielectric and a gate conductor abuts the plurality of vertically stacked and vertically spaced apart semiconductor nanowires, and the source regions and the drain regions are self-aligned with the gate region.
    Type: Grant
    Filed: February 17, 2009
    Date of Patent: February 22, 2011
    Assignee: International Business Machines Corporation
    Inventors: Stephen W. Bedell, Josephine B. Chang, Paul Chang, Michael A. Guillorn, Jeffrey W. Sleight
  • Patent number: 7879594
    Abstract: The present invention relates to a method for detecting a target biomolecule in a sample comprising a plurality of biomolecules, whereby the target biomolecule is provided with a tag, said tag comprising a catalytic active moiety which catalyses a reaction yielding an insoluble reaction product which precipitates on flexible electrically conductive nanoelectrodes. The precipitation onto said nanoelectrodes causes a change in their electroconductivity which is accessible to electroanalytical methods. The invention relates further to a biochip comprising a solid support with nanoelectrodes attached thereto and probe molecules bound to all or to a plurality of said nanoelectrodes which may be the same or different, a segment of said probe molecules being able to interact specifically with a segment of the target biomolecules.
    Type: Grant
    Filed: March 15, 2004
    Date of Patent: February 1, 2011
    Assignee: Biomerieux
    Inventors: Bernard Mandrand, Agnes Dupont-Filliard
  • Patent number: 7872324
    Abstract: Provided is a suspended nanowire sensor having good sensing characteristics and suitable for mass production, a method for fabricating the suspended nanowire sensor. The suspended nanowire sensor includes: first and second sensor electrodes formed on upper portions of a substrate and physically separated from each other; and a nanowire sensor material piece extending from the first sensor electrode to the second sensor electrode and physically suspended between the first and second sensor electrodes.
    Type: Grant
    Filed: October 31, 2007
    Date of Patent: January 18, 2011
    Assignee: Electronics and Telecommunications Research Institute
    Inventors: Yong-Shin Kim, Youn-Tae Kim, Duck-Gun Park