Abstract: A sensor for biomolecules includes a silicon fin comprising undoped silicon; a source region adjacent to the silicon fin, the source region comprising heavily doped silicon; a drain region adjacent to the silicon fin, the drain region comprising heavily doped silicon of a doping type that is the same doping type as that of the source region; and a layer of a gate dielectric covering an exterior portion of the silicon fin between the source region and the drain region, the gate dielectric comprising a plurality of antibodies, the plurality of antibodies configured to bind with the biomolecules, such that a drain current flowing between the source region and the drain region varies when the biomolecules bind with the antibodies.

Abstract: Disclosed is a composite material wherein adhesion between a silicon surface and a plating material is enhanced. A method and an apparatus for producing the composite material are also disclosed.

Abstract: The present invention relates to growth of III-V semiconductor nanowires (2) on a Si substrate (3). Controlled vertical nanowire growth is achieved by a step, to be taken prior to the growing of the nanowire, of providing group III or group V atoms to a (111) surface of the Si substrate to provide a group III or group V 5 surface termination (4). A nanostructured device including a plurality of aligned III-V semiconductor nanowires (2) grown on, and protruding from, a (111) surface of a Si substrate (3) in an ordered pattern in compliance with a predetermined device layout is also presented.

Abstract: A method of fabricating a FET device is provided which includes the following steps. Nanowires/pads are formed in a SOI layer over a BOX layer, wherein the nanowires are suspended over the BOX. A HSQ layer is deposited that surrounds the nanowires. A portion(s) of the HSQ layer that surround the nanowires are cross-linked, wherein the cross-linking causes the portion(s) of the HSQ layer to shrink thereby inducing strain in the nanowires. One or more gates are formed that retain the strain induced in the nanowires. A FET device is also provided wherein each of the nanowires has a first region(s) that is deformed such that a lattice constant in the first region(s) is less than a relaxed lattice constant of the nanowires and a second region(s) that is deformed such that a lattice constant in the second region(s) is greater than the relaxed lattice constant of the nanowires.

Abstract: A method of producing sharp tips useful for scanning probe microscopy and related applications is described. The tips are formed by deposition into a mold(s) formed in a sacrificial crystalline semiconductor substrate with an exposed {311} surface which has been etched with a crystallographic etchant to form a 3-sided, trihedral or trigonal pyramidal mold(s) or indentation(s). The resultant tips, when released from the sacrificial mold material or substrate, are typically formed in the shape of a trigonal pyramid or a tetrahedron. Another embodiment involves starting with a {100} surface and the formation of two tips on opposite ends of a wedge at trigonal or trihedral points of the wedge. These tips are less susceptible to the tip wedge effect typical of tips formed using known methods.

Abstract: A method is provided for consuming oxides in a silicon (Si) nanoparticle film. The method forms a colloidal solution film of Si nanoparticles overlying a substrate. The Si nanoparticle colloidal solution film is annealed at a high temperature in the presence of titanium (Ti). In response to the annealing, Si oxide is consumed in a resultant Si nanoparticle film. In one aspect, the consuming the Si oxide in the Si nanoparticle film includes forming Ti oxide in the Si nanoparticle film. Also in response to a low temperature annealing, solvents are evaporated in the colloidal solution film of Si nanoparticles. Si and Ti oxide molecules are sintered in the Si nanoparticle film in response to the high temperature annealing.

Abstract: A packaged power field effect transistor device includes a power field effect transistor die, a DBA substrate, a clip, a wire bond, leads, and an amount of plastic encapsulant. The top of the DBA has a plurality of metal plate islands. A sintered silver feature is disposed on one of the islands. A silvered backside of the die is directly bonded to the sintered silver structure of the DBA. The upper surface of the die includes a first aluminum pad (a source pad) and a second aluminum pad (a gate pad). A sintered silver structure is disposed on the first aluminum pad, but there is no sintered silver structure disposed on the second aluminum pad. A high current clip is attached via soft solder to the sintered silver structure on the first aluminum pad (the source pad). A bond wire is ultrasonically welded to the second aluminum pad (gate pad).

Abstract: A memory array includes a plurality of memory cells, each of which receives a bit line, a first word line, and a second word line. Each memory cell includes a cell selection circuit, which allows the memory cell to be selected. Each memory cell also includes a two-terminal switching device, which includes first and second conductive terminals in electrical communication with a nanotube article. The memory array also includes a memory operation circuit, which is operably coupled to the bit line, the first word line, and the second word line of each cell. The circuit can select the cell by activating an appropriate line, and can apply appropriate electrical stimuli to an appropriate line to reprogrammably change the relative resistance of the nanotube article between the first and second terminals. The relative resistance corresponds to an informational state of the memory cell.

Abstract: A bi-stable quantum wire array of self-assembled nano-medicine and its process present in the invention. The bi-stable quantum wire array with quantum bit and kondo effect is prepared by self-assembling an oxygen radical antagonist of antioxidase, a ?-receptor agonist, a P2 receptor agonist, a calcium antagonist of phenyl alkyl amines, and/or a nucleotide monomer of purines and its binary, ternary, quaternary or quinary compounds and using the interaction of inelastic electron tunneling. The invention not only benefits mechanisms-targeted multifunctional device discoveries, but also profits inventions of nanometer structures, novel materials, quantum calculation devices, biosensors and quantum bit magnetic random access memories (MRAM).

Abstract: There is disclosed a method for making a nano-composite gas sensor. At first, there is provided a substrate. Then, electrodes are provided on the substrate in an array. Finally, a gas-sensing membrane is provided on the electrodes. The gas-sensing membrane includes a nano-conductive film and a peptide film.

Abstract: A semiconductor nanocrystal includes a core including a first semiconductor material and an overcoating including a second semiconductor material. A monodisperse population of the nanocrystals emits blue light over a narrow range of wavelengths with a high quantum efficiency.

Abstract: In accordance with aspects of the invention, a method of forming a metal-insulator-metal stack is provided. The method includes forming a first conducting layer, forming a resistivity-switching carbon-based material above the first conducting layer, and forming a second conducting layer above the carbon-based material, wherein the carbon-based material has a thickness of not more than ten atomic layers. Other aspects are also described.

Abstract: A method of fabricating a FET device is provided which includes the following steps. Nanowires/pads are formed in a SOI layer over a BOX layer, wherein the nanowires are suspended over the BOX. A HSQ layer is deposited that surrounds the nanowires. A portion(s) of the HSQ layer that surround the nanowires are cross-linked, wherein the cross-linking causes the portion(s) of the HSQ layer to shrink thereby inducing strain in the nanowires. One or more gates are formed that retain the strain induced in the nanowires. A FET device is also provided wherein each of the nanowires has a first region(s) that is deformed such that a lattice constant in the first region(s) is less than a relaxed lattice constant of the nanowires and a second region(s) that is deformed such that a lattice constant in the second region(s) is greater than the relaxed lattice constant of the nanowires.

Abstract: A semiconductor device is formed with sub-resolution features and at least one additional feature having a relatively larger critical dimension using only two masks. An embodiment includes forming a plurality of first mandrels, having a first width, and at least one second mandrel, having a second width greater than the first width, overlying a target layer using a first mask, forming sidewall spacers along the length and width of the first and second mandrels, forming a filler adjacent each sidewall spacer, the filler having the first width, removing the filler adjacent sidewall spacers along the widths of the first and second mandrels using a second mask, removing the sidewall spacers, and etching the target layer between the filler and the first and second mandrels, thereby forming at least two target features with different critical dimensions.

Abstract: An organic electroluminescence element having a cathode as a top electrode, and excelling in luminance efficiency, drive voltage, and operational life is provided. The organic electroluminescence element includes an anode over a substrate and a luminescent layer over the anode. The luminescent layer comprises an organic material. An electron injection layer is over the luminescent layer for injecting electrons into the luminescent layer. The electron injection layer is a metal including at least one of an alkaline metal and an alkaline earth metal. A fullerene layer is over the electron injection layer and includes fullerenes and at least one of an alkaline metal and an alkaline earth metal. The at least one of the alkaline metal and the alkaline earth metal included in the fullerene layer has a lower work function than a lowest unoccupied molecular orbit energy level of the fullerenes. A cathode is over the fullerene layer.

Abstract: In some aspects, a method of forming a carbon nano-tube (CNT) memory cell is provided that includes (1) forming a first conductor; (2) forming a steering element above the first conductor; (3) forming a first conducting layer above the first conductor; (4) forming a CNT material above the first conducting layer; (5) implanting a selected implant species into the CNT material; (6) forming a second conducting layer above the CNT material; (7) etching the first conducting layer, CNT material and second conducting layer to form a metal-insulator-metal (MIM) stack; and (8) forming a second conductor above the CNT material and the steering element. Numerous other aspects are provided.

Abstract: A chlorine gas sensor system includes carbon nanotubes at least partially coated with a metal oxide deposited on a substrate, and a source of infra-red light positioned to illuminate at least a portion of the coated nanotubes.

Abstract: A memory cell is provided including a tunnel dielectric layer overlying a semiconductor substrate. The memory cell also includes a floating gate having a first portion overlying the tunnel dielectric layer and a second portion in the form of a nanorod extending from the first portion. In addition, a control gate layer is separated from the floating gate by an intergate dielectric layer.

Abstract: A biosensor using a nanodot and a method of manufacturing the same are provided. A silicon nanowire can be formed by a CMOS process to reduce manufacturing costs. In addition, an electrically charged nanodot is coupled to a target molecule to be detected, in order to readily change conductivity of the silicon nanowire, thereby making it possible to implement a biosensor capable of providing good sensitivity and being manufactured at a low cost.

Abstract: Techniques for providing heat to a small area and apparatus capable of providing heat to a small area are provided.

Abstract: Solid and hollow cylindrical nanopillars with nanoscale diameters are provided. Also provides is a method of making such nanopillars using electron beam lithography followed by the electroplating.

Abstract: A light coupler between an optical fiber (6) and a waveguide is made on a semiconductor-on-insulator substrate (1), this substrate (1) comprising a thin layer of semiconducting material in which the waveguide is made. The coupler comprises a light injector (5) and an adiabatic collector (4) made up with an inverted nanotip formed from the thin layer of semiconducting material. The injector (5) is formed on the insulator (3) and has a face (7) for receiving an end of the optical fiber (6). The adiabatic collector (4) has a cross-section which increases from a first end located on the side of said end of the optical fiber (6) right up to a second end which is connected to the waveguide, the injector (5) covering the adiabatic collector (4) and having a rib waveguide shape.

Abstract: A semiconductor structure including an ordered array of parallel graphene nanoribbons located on a surface of a semiconductor substrate is provided using a deterministically assembled parallel set of nanowires as an etch mask. The deterministically assembled parallel set of nanowires is formed across a gap present in a patterned graphene layer utilizing an electric field assisted assembly process. A semiconductor device, such as a field effect transistor, can be formed on the ordered array of parallel graphene nanoribbons.

Abstract: Direct resistive heating is used to grow nanotubes out of carbon and other materials. A growth-initiated array of nanotubes is provided using a CVD or ion implantation process. These processes use indirect heating to heat the catalysts to initiate growth. Once growth is initiated, an electrical source is connected between the substrate and a plate above the nanotubes to source electrical current through and resistively heat the nanotubes and their catalysts. A material source supplies the heated catalysts with carbon or another material to continue growth of the array of nanotubes. Once direct heating has commenced, the source of indirect heating can be removed or at least reduced. Because direct resistive heating is more efficient than indirect heating the total power consumption is reduced significantly.

Abstract: The inventive method for forming nano-dimensional clusters consists in introducing a solution containing a cluster-forming material into nano-pores of natural or artificial origin contained in a substrate material and in subsequently exposing said solution to a laser radiation pulse in such a way that a low-temperature plasma producing a gaseous medium in the domain of the existence thereof, wherein a cluster material is returned to a pure material by the crystallization thereof on a liquid substrate while the plasma is cooling, occurs, thereby forming mono-crystal quantum dots spliced with the substrate material. Said method makes it possible to form two- or three-dimensional cluster lattices and clusters spliced with each other from different materials. The invention also makes it possible to produce wires from different materials in the substrate nano-cavities and the quantum dots from the solution micro-drops distributed through an organic material applied to a glass.

Abstract: An electrical circuit structure employing graphene as a charge carrier transport layer. The structure includes a plurality of graphene layers. Electrical contact is made with one of the layer of the plurality of graphene layers, so that charge carriers travel only through that one layer. By constructing the active graphene layer within or on a plurality of graphene layers, the active graphene layer maintains the necessary planarity and crystalline integrity to ensure that the high charge carrier mobility properties of the active graphene layer remain intact.

Abstract: Light-emitting diodes, and methods of manufacturing the light-emitting diode, are provided wherein a plurality of nano-rods may be formed on a reflection electrode. The plurality of nano-rods extend perpendicularly from an upper surface of the reflection electrode. Each of the nano-rods includes a first region doped with a first type dopant, a second region doped with a second type dopant that is an opposite type to the first type dopant, and an active region between the first region and the second region. A transparent insulating layer may be formed between the plurality of nano-rods. A transparent electrode may be formed on the plurality of nano-rods and the transparent insulating layer.

Abstract: A lateral p-i-n photodetector is provided that includes an array of vertical semiconductor nanowires of a first conductivity type that are grown over a semiconductor substrate also of the first conductivity type. Each vertically grown semiconductor nanowires of the first conductivity type is surrounded by a thick epitaxial intrinsic semiconductor film. The gap between the now formed vertically grown semiconductor nanowires-intrinsic semiconductor film columns (comprised of the semiconductor nanowire core surrounded by intrinsic semiconductor film) is then filled by forming an epitaxial semiconductor material of a second conductivity type which is different from the first conductivity type. In a preferred embodiment, the vertically grown semiconductor nanowires of the first conductivity type are n+ silicon nanowires, the intrinsic epitaxial semiconductor layer is comprised of intrinsic epitaxial silicon, and the epitaxial semiconductor material of the second conductivity type is comprised of p+ silicon.

Abstract: In accordance with aspects of the invention, a method of forming a memory cell is provided, the method including forming a steering element above a substrate, and forming a memory element coupled to the steering element, wherein the memory element comprises a carbon-based material having a thickness of not more than ten atomic layers. The memory element may be formed by repeatedly performing the following steps: forming a layer of a carbon-based material, the layer having a thickness of about one monolayer, and subjecting the layer of carbon-based material to a thermal anneal. Other aspects are also described.

Abstract: Methods of the present invention can be used to synthesize nanowires with controllable compositions and/or with multiple elements. The methods can include coating solid powder granules, which comprise a first element, with a catalyst. The catalyst and the first element should form when heated a liquid, mixed phase having a eutectic or peritectic point. The granules, which have been coated with the catalyst, can then be heated to a temperature greater than or equal to the eutectic or peritectic point. During heating, a vapor source comprising the second element is introduced. The vapor source chemically interacts with the liquid, mixed phase to consume the first element and to induce condensation of a product that comprises the first and second elements in the form of a nanowire.

Abstract: The present invention relates to growth of III-V semiconductor nanowires (2) on a Si substrate (3). Controlled vertical nanowire growth is achieved by a step, to be taken prior of the growing of the nanowire, of providing group III or group V atoms to a (111) surface of the Si substrate to provide a group III or group V 5 surface termination (4). A nanostructured device comprising a plurality of aligned III-V semiconductor nanowires (2) grown on, and protruding from, a (111) surface of a Si substrate (3) in an ordered pattern in compliance with a predetermined device layout is also presented.

Abstract: A biosensor using a nanodot and a method of manufacturing the same are provided. A silicon nanowire can be formed by a CMOS process to reduce manufacturing costs. In addition, an electrically charged nanodot is coupled to a target molecule to be detected, in order to readily change conductivity of the silicon nanowire, thereby making it possible to implement a biosensor capable of providing good sensitivity and being manufactured at a low cost.

Abstract: A nanostructure pattern which includes pairs of metal lines separated by identical gaps whose dimensions are in the nanometer range, can be prepared by providing a separating sacrificial layer, whose dimensions can be controlled precisely, in the separation gap between the first metal line and the second metal line. The sacrificial layer is removed at the end of the fabrication, leaving a precisely dimensioned gap between the lines.

Abstract: A light-emitting device includes an n-type silicon thin film (2), a silicon thin film (3), and a p-type silicon thin film (4). The silicon thin film (3) is formed on the n-type silicon thin film (2) and the p-type silicon thin film (4) is formed on the silicon thin film (3). The n-type silicon thin film (2), the silicon thin film (3), and the p-type silicon thin film (4) form a pin junction. The n-type silicon thin film (2) includes a plurality of quantum dots (21) composed of n-type Si. The silicon thin film (3) includes a plurality of quantum dots (31) composed of p-type Si. The p-type silicon thin film (4) includes a plurality of quantum dots (41) composed of p-type Si. Electrons are injected from the n-type silicon thin film (2) side and holes are injected from the p-type silicon thin film (4) side, whereby light is emitted at a silicon nitride film (3).

Abstract: Some embodiments include devices that contain bundles of CNTs. An undulating topography extends over the CNTs and within spaces between the CNTs. A global maximum lateral width is defined as the greatest lateral width of any of the spaces. A material is directly over the CNTs, with the material being a plurality of particles that have minimum cross-sectional equatorial widths exceeding the global maximum lateral width. Some embodiments include methods in which a plurality of crossed carbon nanotubes are formed over a semiconductor substrate. The CNTs form an undulating upper topography extending across the CNTs and within spaces between the CNTs. A global maximum lateral width is defined as the greatest lateral width of any of the spaces. A material is deposited over the CNTs, with the material being deposited as particles that have minimum cross-sectional equatorial widths exceeding the global maximum lateral width.

Abstract: A memory cell is provided including a tunnel dielectric layer overlying a semiconductor substrate. The memory cell also includes a floating gate having a first portion overlying the tunnel dielectric layer and a second portion in the form of a nanorod extending from the first portion. In addition, a control gate layer is separated from the floating gate by an intergate dielectric layer.

Abstract: The present invention generally relates to the fabrication of molecular electronics devices from molecular wires and Single Wall Nanotubes (SWNT). In one embodiment, the cutting of a SWNT is achieved by opening a window of small width by lithography patterning of a protective layer on top of the SWNT, followed by applying an oxygen plasma to the exposed SWNT portion. In another embodiment, the gap of a cut SWNT is reconnected by one or more difunctional molecules having appropriate lengths reacting to the functional groups on the cut SWNT ends to form covalent bonds. In another embodiment, the gap of a cut SWNT gap is filled with a self-assembled monolayer from derivatives of novel contorted hexabenzocoranenes. In yet another embodiment, a device based on molecular wire reconnecting a cut SWNT is used as a sensor to detect a biological binding event.

Abstract: A structure comprises at least a porous body holding a substance releasably, comprising a capping member for keeping the substance inside the pore and/or on at least a part of the entire surface of the porous body, and a connecting member for connecting the porous body and the capping member separably, the connecting member comprising a biopolymer compound. A method for releasing a substance from the structure set forth comprises the steps of applying stimulation from outside to the structure, and cleaving at least one of the bonding between the connecting member and the capping member and the bonding between the connecting member and the porous member to make the substance releasable from the structure.

Abstract: Provided may be a method of fabricating a flash memory device having metal nano particles. The method of manufacturing a flash memory device may include forming a metal oxide thin layer on a semiconductor substrate, forming a floating gate of an amorphous metal silicon oxide thin layer by performing a thermal treatment process on the semiconductor substrate where the metal oxide thin layer is formed, and forming metal nano particles in the floating gate by projecting an electron beam on the floating gate, the metal nano particles being surrounded by a silicon oxide layer.

Abstract: The method of fabricating semiconducting nanowires having a desired wire diameter includes providing pre-fabricated semiconducting nanowires, at least one pre-fabricated nanowire having a wire diameter larger than the desired wire diameter (d); and reducing the wire diameter of the at least one pre-fabricated nanowire by etching. The etching is induced by light which is absorbed by the at least one pre-fabricated nanowire. The spectrum of the light is chosen such that the absorption of the at least one pre-fabricated nanowire is significantly reduced when the at least one pre-fabricated nanowire reaches the desired wire diameter.

Abstract: There are provided a semiconductor light emitting device using a phosphor film formed on a nanowire structure and a method of manufacturing the device, the device including: a substrate; a light emitting structure including a first conductivity type semiconductor layer, an active layer and a second conductivity type semiconductor layer sequentially formed on the substrate; a plurality of nanowire structures formed on the light emitting structure and formed of a transparent material; and a phosphor film formed on at least an upper surface and a side surface of each of the plurality of nanowire structures.

Abstract: Disclosed are a carbon nanotube-coated silicon/metal composite particle, a preparation method thereof, an anode for a secondary battery comprising the carbon nanotube-coated silicon/metal composite particle, and a secondary battery comprising the anode, wherein the carbon nanotube-coated silicon/metal composite particle characterized in comprising: a composite particle of silicon and metal; and a carbon nanotube coated on the surface of the composite particle of silicon and metal, wherein the carbon nanotube-coated silicon/metal composite particle may be prepared by preparing composite particle of silicon and metal, followed by treating the composite particles of silicon and metal with heat under a mixed gas atmosphere of an inert gas and a hydrocarbon gas.

Abstract: A light coupler between an optical fiber (6) and a waveguide is made on a semiconductor-on-insulator substrate (1), this substrate (1) comprising a thin layer of semiconducting material in which the waveguide is made. The coupler comprises a light injector (5) and an adiabatic collector (4) made up with an inverted nanotip formed from the thin layer of semiconducting material. The injector (5) is formed on the insulator (3) and has a face (7) for receiving an end of the optical fiber (6). The adiabatic collector (4) has a cross-section which increases from a first end located on the side of said end of the optical fiber (6) right up to a second end which is connected to the waveguide, the injector (5) covering the adiabatic collector (4) and having a rib waveguide shape.

Abstract: A method is for manufacturing a microeletromechanical system resonator having a semiconductor device and a microelectromechanical system structure unit formed on a substrate. The method includes: forming a lower electrode of an oxide-nitride-oxide capacitor unit included in the semiconductor device using a first silicon layer; forming, using a second silicon layer, a substructure of the microelectromechanical system structure unit and an upper electrode of the oxide-nitride-oxide capacitor unit included in the semiconductor device; and forming, using a third silicon layer, a superstructure of the microelectromechanical system structure unit and a gate electrode of a complementary metal oxide semiconductor circuit unit included in the semiconductor device.

Abstract: A memory cell is provided including a tunnel dielectric layer overlying a semiconductor substrate. The memory cell also includes a floating gate having a first portion overlying the tunnel dielectric layer and a second portion in the form of a nanorod extending from the first portion. In addition, a control gate layer is separated from the floating gate by an intergate dielectric layer.

Abstract: Provided are nano wires and a method of manufacturing the same. The method includes forming microgrooves having a plurality of microcavities, the microgrooves forming a regular pattern on a surface of a silicon substrate; forming a metal layer on the silicon substrate by depositing a material which acts as a catalyst to form nano wires on the silicon substrate; agglomerating the metal layer within the microgrooves on the surface of the silicon substrate by heating the metal layer to form catalysts; and growing the nano wires between the catalysts and the silicon substrate using a thermal process.

Abstract: Faceted catalytic dots are used for directing the growth of carbon nanotubes. In one example, a faceted dot is formed on a substrate for a microelectronic device. A growth promoting dopant is applied to a facet of the dot using an angled implant, and a carbon nanotube is grown on the doped facet of the dot.

Abstract: A plurality of conductive pads (2) are formed on a mounting surface of a mounting board. Conductive pads (11) are formed on a principal surface of a semiconductor chip (10) at positions corresponding to the conductive pads of the mounting board, when the principal surface faces toward the mounting board. A plurality of conductive nanotubes (12) extend from the conductive pads of one of the mounting board and the semiconductor chip. A press mechanism (3) presses the semiconductor chip against the mounting board and restricts a position of the semiconductor chip on the mounting surface to mount the semiconductor chip on the mounting board, in a state that tips of the conductive nanotubes are in contact with the corresponding conductive pads not formed with the conductive nanotubes.

Abstract: Segmented semiconductor nanowires are manufactured by removal of material from a layered structure of two or more semiconductor materials in the absence of a template. The removal takes place at some locations on the surface of the layered structure and continues preferentially along the direction of a crystallographic axis, such that nanowires with a segmented structure remain at locations where little or no removal occurs. The interface between different segments can be perpendicular to or at angle with the longitudinal direction of the nanowire.

Abstract: A nonvolatile memory cell is capable of reducing an excessive current leakage due to a rough surface of a polysilicon and of performing even at a low temperature process by forming the first oxide film including a silicon oxynitride (SiOxNy) layer using nitrous oxide plasma and by forming a plurality of silicon nanocrystals in a nitride film by implanting a silicon nanocrystal on the nitride film by an ion implantation method, and a fabricating method thereof and a memory apparatus including the nonvolatile memory cell.