Abstract: Disclosed are synthetic nanocarrier compositions, and related methods, comprising APC presentable transplant antigens and immunosuppressants that provide tolerogenic immune responses (e.g., a reduction in CD8+ T cell proliferation and/or activity) specific to the APC presentable transplant antigens.

Abstract: This invention relates, at least in part, to compositions comprising synthetic nanocarriers and immunosuppressants that result in immune suppressive effects. Such compositions can further comprise antigen and provide antigen-specific tolerogenic immune responses.

Abstract: Disclosed are synthetic nanocarrier compositions, and related methods, comprising MHC Class II-restricted epitopes and immunosuppressants that provide tolerogenic immune responses, such as a reduction in CD4+ T cell help specific to an antigen.

Abstract: Non-volatile memory devices with two stacked layers of chalcogenide materials comprising the active memory device have been investigated for their potential as phase-change memories. The devices tested included GeTe/SnTe, Ge2Se3/SnTe, and Ge2Se3/SnSe stacks. All devices exhibited resistance switching behavior. The polarity of the applied voltage with respect to the SnTe or SnSe layer was critical to the memory switching properties, due to the electric field induced movement of either Sn or Te into the Ge-chalcogenide layer. One embodiment of the invention is a device comprising a stack of chalcogenide-containing layers which exhibit phase-change switching only after a reverse polarity voltage potential is applied across the stack causing ion movement into an adjacent layer and thus “activating” the device to act as a phase-change random access memory device or a reconfigurable electronics device when the applied voltage potential is returned to the normal polarity.

Abstract: Memory devices include a row decoder, a first variable resistance memory cell connected to a first bit line and connected to the row decoder by a word line and a second variable resistance memory cell connected to a second bit line and connected to the row decoder by the word line. The memory devices further include a bit line select circuit coupled to the first and second bit lines and configured to compensate for a difference in word line resistance between the row decoder and the respective first and second memory cells. In some embodiments, the bit line select circuit includes first and second transistors configured to selective respective ones of the first and second bit lines and the first and second transistors have different resistances that compensate for the difference in word line resistance.

Abstract: A solid-state memory device includes: a superlattice laminate having plural crystal layers laminated therein, the crystal layers including first and second crystal layers having mutually opposite compositions; a lower electrode provided on a first surface in a laminating direction of the superlattice laminate; and an upper electrode provided on a second surface of the superlattice laminate in the laminating direction. The first crystal layer included in the superlattice laminate is made of a phase change compound. According to the present invention, the superlattice laminate laminated in opposite directions of the upper and lower electrodes is sandwiched between these electrodes. Therefore, when an electric energy is applied to the superlattice laminate via these electrodes, a uniform electric energy can be applied to a laminated surface of the superlattice laminate. Accordingly, fluctuation of a resistance is small even when information is repeatedly rewritten, and data can be read stably as a result.

Abstract: Some embodiments include memory arrays. The memory arrays can have global bitlines extending along a first horizontal direction, vertical local bitlines extending perpendicularly from the global bitlines, and wordlines extending along a second horizontal direction which is perpendicular to the first horizontal direction. The global bitlines may be subdivided into a first series at a first elevational level, and a second series at a second elevational level which is different from the first elevational level. The global bitlines of the first series can alternate with the global bitlines of the second series. There can be memory cell material directly between the wordlines and the vertical local bitlines. The memory cell material may form a plurality of memory cells uniquely addressed by wordline/global bitline combinations. Some embodiments include cross-point memory cell units that have areas of about 2F2.

Abstract: An integrated circuit includes an array of diodes and an electrode coupled to each diode. The integrated circuit includes a layer of resistance changing material coupled to the electrodes and bit lines coupled to the layer of resistance changing material. The layer of resistance changing material provides a resistance changing element at each intersection of each electrode and each bit line.

Abstract: A memristive Negative Differential Resistance (NDR) device includes a first electrode adjacent to a memristive matrix, the memristive matrix including an intrinsic semiconducting region and a highly doped secondary region, a Metal-Insulator-Transition (MIT) material in series with the memristive matrix, and a second electrode adjacent to the MIT material.

Abstract: A phase change memory device is constituted of a plurality of memory cells including a plurality of phase change memory elements, which are arranged at intersecting points formed between a plurality of word lines and a plurality of bit lines. A write circuit which operates based on a write voltage source (Vwrite) is controlled by control signals (e.g. WE, RDIS, SDIS, and DIN) output from a control circuit which operates based on a voltage source (VDD), where Vwrite>VDD. All the control signals based on VDD are applied to the gates of N-channel MOS transistors included in the write circuit. This allows adequately high write currents to be supplied to phase change memory elements; and this eliminates the necessity of arranging a potential switch circuit in the write circuit, thus reducing the scale of the phase change memory device.

Abstract: A multi-level cell (MLC) phase-change memory device divides data into data groups each comprising multiple bits of data, and stores each of the data groups in a selected phase-change memory cell. A data group is stored in a selected phase-change memory cell by applying a pulse current to the selected phase-change memory cell with a pulse current characteristic corresponding to a data value of the data group. The pulse current characteristic can comprise, for instance, a magnitude, downward slope, or duration of the pulse current. Data is read from a selected phase-change memory cell by sensing a voltage of a bitline connected to the selected phase-change memory cell and comparing the sensed voltage simultaneously with a plurality of reference voltages.

Abstract: The present invention relates to novel therapeutic and diagnostic dendrimers. In particular, the present invention is directed to dendrimer-linker conjugates, methods of synthesizing the same, compositions comprising the conjugates, as well as systems and methods utilizing the conjugates (e.g., in diagnostic and/or therapeutic settings (e.g., for the delivery of therapeutics, imaging, and/or targeting agents (e.g., in disease (e.g., cancer) diagnosis and/or therapy, pain therapy, etc.)). Accordingly, dendrimer-linker conjugates of the present invention may further comprise one or more components for targeting, imaging, sensing, and/or providing a therapeutic or diagnostic material and/or monitoring response to therapy.

Abstract: A phase-change memory device and its firing method are provided. The firing method of the phase-change memory device includes applying a writing current to phase-change memory cells, identifying a state of the phase-change memory cells after applying the writing current, and applying a firing current, in which an additional current is added to the writing current, to the phase-change memory cells in accordance with the state.

Abstract: Programmable via devices and methods for the fabrication thereof are provided. In one aspect, a programmable via device is provided.

Abstract: A phase change memory device includes a plurality of bit lines and a reference bit line intersecting a plurality of word lines. A cell array block has a phase change resistance cell arranged where a word line and a bit line intersect. A reference cell array block is configured to output a reference current and is formed where the word line and a reference bit line intersect. A column selecting unit is configured to select a corresponding bit line connected to the cell array block. A reference column selecting unit is connected to the reference cell array block and is configured to select the reference bit line. A sense amplifier is connected to the column selecting unit and the reference column selecting unit and is configured to receive the reference current and a cell data current of the bit line.

Abstract: A phase change memory device includes a phase change resistance cell configured to sense a crystallization state that changes in response to a current so that data corresponding to the crystallization state can be stored in the phase change resistance cell. A write driving control signal generating unit outputs a write enable signal and a precharge enable signal in response to a write control signal that corresponds to a heating period and a quenching period of the write data. A write driving unit is configured to supply a driving voltage corresponding to the write data to the phase change resistance cell in response to the write enable signal and the precharge enable signal.

Abstract: In a program method for a multi-level phase change memory device, multi-level data to be programmed in a selected memory cell is received, and a program signal is applied to the selected memory cell according to the received multi-level data. Herein, a rising time of the program signal is set to be longer than a falling time of the program signal.

Abstract: A phase change memory in the reset state may be heated to reduce or eliminate electrical drift.

Abstract: The leakage current and power consumption of phase change memories may be reduced using adaptive word line biasing. Depending on the particular voltage applied to the bitline of a programmed cell, the word lines of unselected cells may vary correspondingly. In some embodiments, the word line voltage may be caused to match the bitline voltage of the programmed cell.

Abstract: In accordance with some embodiments, a phase change memory may be formed in which the thermal conductivity in the region outside the programmed volume of phase change material is reduced. This may reduce the power consumption of the resulting phase change memory. The reduction in power consumption may be achieved by forming distinct layers of phase change material that have little or no mixing between them outside the programmed volume. For example, in one embodiment, a diffusion barrier layer may be maintained between the two distinct phase change layers. In another embodiment, a face centered cubic chalcogenide structure may be utilized.

Abstract: A microelectronic programmable structure suitable for storing information and array including the structure and methods of forming and programming the structure are disclosed. The programmable structure generally includes an ion conductor and a plurality of electrodes. Electrical properties of the structure may be altered by applying energy to the structure, and thus information may be stored using the structure.

Abstract: A microelectronic programmable structure suitable for storing information and array including the structure and methods of forming and programming the structure are disclosed. The programmable structure generally includes an ion conductor and a plurality of electrodes. Electrical properties of the structure may be altered by applying energy to the structure, and thus information may be stored using the structure.

Abstract: A microelectronic programmable structure and methods of forming and programming the structure are disclosed. The programmable structure generally includes an ion conductor and a plurality of electrodes. Electrical properties of the structure may be altered by applying a bias across the electrodes, and thus information may be stored using the structure.

Abstract: The invention relates to a vapor grown carbon fiber having a mean fiber diameter of 80 to 500 nm, an aspect ratio of 100 to 200 and preferably a bulk density of 0.02 g/cm3 or less, wherein filaments having a diameter within ±20% of the mean fiber diameter occupies 65% (on a number basis) or more of the total. The production method involves thermal decomposition of a carbon source at 800 to 1,300° C. in the presence of, as a catalyst, a transition metal compound having a vapor pressure of 0.13 kPa (1 mmHg) or more at 150° C. and spraying of the carbon source and the transition metal compound in gas form toward the reactor inner wall to allow reaction to proceed. The vapor grown carbon fiber having a larger aspect ratio has excellent dispersibility, and when added in a resin, a smaller amount contributes to enhancement in electroconductivity and thermal conductivity, as compared with a case using conventional one.

Abstract: A memory is configurable among a plurality of operational modes. The operational modes may dictate the number of storage levels to be associated with each cell within the memory's storage matrix.

Abstract: A memory device comprises a plurality of memory cells, each memory cell comprising a memory cell material that has an initial resistance that is determined in response to an applied programming current in a programming operation, the resistance of the memory cell varying from the initial resistance over a time period following the programming operation, and each memory cell being connected to a conduction line of the memory device that is used to apply the programming current to program the resistance of the corresponding memory cell in the programming operation and that is used to apply a read current to read the resistance of the corresponding memory cell in a read operation. A modification circuit modifies the resistance of a memory cell of the plurality of memory cells selected for a read operation to return its resistance to near the initial resistance prior to a read operation of the memory cell.

Abstract: The present invention relates to a contraceptive composition including an effective amount of a dendrimer compound including one or more naphthyl disulphonic acid surface groups, or a pharmaceutically acceptable salt or solvate of the dendrimer compound; and a pharmaceutically acceptable carrier, excipient and/or diluent therefor. The contraceptive composition may also exhibit antimicrobial activity. The invention also relates to a method of selectively reducing or preventing conception in a female animal, including a human, which method includes administering to the animal an effective amount of a contraceptive composition which composition includes an effective amount of a dendrimer compound including one or more naphthyl disulphonic acid surface groups, or a pharmaceutically acceptable salt or solvate of the dendrimer compound; and a pharmaceutically acceptable carrier, excipient and/or diluent therefor.

Abstract: A phase change memory device using a multiple level write voltage is described. The phase change memory device includes a cell array unit including a phase change resistance cell positioned at an intersection of a word line and a bit line. A voltage selection adjusting unit is configured to select one of a plurality of multiple voltages in response to a voltage adjusting signal to output a driving voltage. A write driving unit is also configured to finely adjust the voltage level of the driving voltage in response to a voltage fine-adjusting signal to supply the driving voltage to the cell array unit.

Abstract: The present invention relates to oligomeric or polymeric saccharide derivatives comprising glucosamine moieties, e.g. derivatives of oligomeric or polymeric glucosamines such as chitosan oligomers or polymers, in which one or more amine groups are substituted by anchoring groups that chemisorb to the surface of a nanoparticle or form an interdigitated bilayer with a surfactant layer surrounding the nanoparticle. The invention also relates to functionalized nanoparticles comprising such derivatives, a method for forming the functionalized particles and to uses thereof as molecular imaging agents, biosensing agents or drug delivery agents, or in the preparation of such agents.

Abstract: An integrated circuit memory device may include an integrated circuit substrate, and a multi-bit memory cell on the integrated circuit substrate. The multi-bit memory cell may be configured to store a first bit of data by changing a first characteristic of the multi-bit memory cell and to store a second bit of data by changing a second characteristic of the multi-bit memory cell. Moreover, the first and second characteristics may be different. Related methods are also discussed.

Abstract: A powder can be produced by immersing microparticles (2) in a first solution (4) which contains coupling molecules (5), and then in a second solution (10) which contains the nanoparticles (12), thereby producing microparticles (2) with nanoparticles (12) attached thereto. The particles form powder particles (14) which allow nanoparticles (12) that are smaller than approximately 5 [mu] to be applied to a component by cold gas spraying.

Abstract: Use of a polylysine, polyamidoamine or polypropylenimine dendrimer having naphthyl disulphonate terminal groups as a topically applied agent in prophylaxis or treatment of sexually transmitted diseases.

Abstract: The present invention provides improved methods and compositions for therapeutically controlling and/or reducing serum phosphate levels in animals and mammalian patients. The methods comprise administering to the patient an amount of a dendrimer composition effective to prevent absorption of substantial amounts of phosphate from the patient's GI tract. In a preferred version, a dose of between 2.5 and 15 grams per day is effective to prevent over 80% of phosphate present in the patient's GI tract from being absorbed. The dendrimer composition may comprise a hydrochloride, hydrobromide, hydroacetate or hydroanionic form.

Abstract: The present invention relates to a peptide nucleic acid (PNA) conjugated with multi-amine linkers, and a method to prepare the same and utilization thereof. More specifically, the method is characterized by conjugating monomers having multi-amine functionality sequentially at a PNA terminal, and effectively immobilizing the PNA conjugated with multi-amine linkers on a solid surface. A PNA array prepared using the PNA conjugated with multi-amine linkers exhibits improved sensitivity and specificity of signals for detecting target nucleic acids as compared to a PNA array using PNA probes having only one amine group. The PNA conjugated with multi-amine linkers can be utilized in nucleic acid detecting devices or kits for gene diagnosis such as PNA microarrays, PNA chips, PNA field-effect transistors and impedance detectors.

Abstract: A variable resistance memory device includes a substrate, a plurality of active lines formed on the substrate, are uniformly separated, and extend in a first direction, a plurality of switching devices formed on the active lines and are separated from one another, a plurality of variable resistance devices respectively formed on and connected to the switching devices, a plurality of local bit lines formed on the variable resistance devices, are uniformly separated, extend in a second direction, and are connected to the variable resistance devices, a plurality of local word lines formed on the local bit lines, are uniformly separated, and extend in the first direction, a plurality of global bit lines formed on the local word lines, are uniformly separated, and extend in the second direction, and a plurality of global word lines formed on the global bit lines, are uniformly separated, and extend in the first direction.

Abstract: A method and device for accomplishing transformation of a switching material from a resistive state to a conductive state. The method utilizes a non-electrical source of energy to effect the switching transformation. The switching material may be a chalcogenide switching material, where the non-electrical source of energy initiates switching by liberating lone pair electrons from bound states of chalcogen atoms. The liberated lone pair electrons form a conductive filament having the characteristics of a solid state plasma to permit high current densities to pass through the switching material. The device includes a switching material with electrical contacts and may be interconnected with other elements in a circuit to regulate electrical communication therebetween.

Abstract: A phase-change memory device and its firing method are provided. The firing method of the phase-change memory device includes applying a writing current to phase-change memory cells, identifying a state of the phase-change memory cells after applying the writing current, and applying a firing current, in which an additional current is added to the writing current, to the phase-change memory cells in accordance with the state.

Abstract: Disclosed are synthetic nanocarrier compositions with coupled adjuvant compositions as well as related methods.

Abstract: In accordance with some embodiments, a phase change memory may be formed in which the thermal conductivity in the region outside the programmed volume of phase change material is reduced. This may reduce the power consumption of the resulting phase change memory. The reduction in power consumption may be achieved by forming distinct layers of phase change material that have little or no mixing between them outside the programmed volume. For example, in one embodiment, a diffusion barrier layer may be maintained between the two distinct phase change layers. In another embodiment, a face centered cubic chalcogenide structure may be utilized.

Abstract: A carbon nanohorn (CNH) is oxidized to make an opening in the side of the CNH. A substance to be included, e.g., a metal, is introduced through the opening. The inclusion substance is moved to a tip part of the carbon nanohorn through heat treatment in vacuum or an inert gas. The CNH is further heat treated in an atmosphere containing oxygen in a low concentration to remove the carbon layer in the tip through catalysis of the inclusion substance. This exposes the inclusion substance. If the inclusion substance is a metal which is not moved to a tip part by the heat treatment in vacuum or an inert gas, the carbon part surrounding the fine catalyst particle is specifically burned by a heat treatment in an low oxygen concentration atmosphere, while utilizing the catalysis. Thus, the fine catalyst particle is fixed to the tip part of the CNH.

Abstract: Disclosed are dosage forms and related methods, that include a first population of synthetic nanocarriers that have one or more first antigens coupled to them, one or more second antigens that are not coupled to the synthetic nanocarriers, and a pharmaceutically acceptable excipient.

Abstract: A method and apparatus for an integrated circuit with programmable memory cells which are arranged between a first and a second conductor for supplying first and second voltage is provided. A control circuit is arranged between the memory cells and the second conductor. The control circuit controls a change time during which at least one of the memory cells is supplied with a changing current from the second supply changing a state of the memory cell. The control circuit senses the state of the memory cell and stops the erasing current when the memory cell is in a changed state. Furthermore an embodiment refers to a data system with a programmable memory and a method of operating an integrated circuit. Another embodiment refers to a method of operating an integrated circuit.

Abstract: Provided are a non-volatile memory device and a method of operating the non-volatile memory device. The non-volatile memory device includes a switching device and a storage node connected to the switching device, wherein the storage node comprises: a first electrode connected to the switching device; a chalcogenide material layer formed on the first electrode; and a second electrode formed on the chalcogenide material layer, and one of the first and second electrodes comprises an electrode contact layer formed adjacent to a limited region of the chalcogenide material layer, and a property of the electrode region adjacent to the chalcogenide material layer is changed reversibly according to the direction in which a current is applied, thereby changing between a high resistance state and a low resistance state.

Abstract: A phase change memory with a primary memory array, a reference memory array, and a comparison circuit is provided. The electrical characteristic curve of the recording layers of the primary memory units is different from the electrical characteristic curve of the recording layers of the reference memory units. The primary memory array includes at least one primary memory unit to generate at least one sensing signal, wherein each of the primary memory units includes at least one recording layer can be programmed to a first resistance and a second resistance. The reference memory array includes at least one reference memory unit to generate at least one reference signal, wherein each of the reference memory units includes at least one recording layer can be programmed to change its resistance. The comparison circuit compares the sensing signal and the reference signal to generate a comparison result.

Abstract: The leakage current and power consumption of phase change memories may be reduced using adaptive word line biasing. Depending on the particular voltage applied to the bitline of a programmed cell, the word lines of unselected cells may vary correspondingly. In some embodiments, the word line voltage may be caused to match the bitline voltage of the programmed cell.

Abstract: Piezoelectric nanostructures, including nanofibers, nanotubes, nanojunctions and nanotrees, may be made of piezoelectric materials alone, or as composites of piezoelectric materials and electrically-conductive materials. Homogeneous or composite nanofibers and nanotubes may be fabricated by electrospinning. Homogeneous or composite nanotubes, nanojunctions and nanotrees may be fabricated by template-assisted processes in which colloidal suspensions and/or modified sol-gels of the desired materials are deposited sequentially into the pores of a template. The electrospinning or template-assisted fabrication methods may employ a modified sol-gel process for obtaining a perovskite phase in the piezoelectric material at a low annealing temperature.

Abstract: Provided is a magnetic-cored dendrimer represented by the following Chemical Formula (1): wherein A represents a metal nanoparticle; Z is a hydrophilic functional group or hydrophobic functional group; and m and n each represent an integer 1 or larger. More particularly, provided are a magnetic-cored dendrimer end-capped with hydrophilic or hydrophobic terminal groups, and a method for preparing the same. The magnetic-cored dendrimer may be used to adsorb and separate contaminants in a simple and effective manner.

Abstract: Physical neural networks based nanotechnology include dendrite circuits that comprise non-volatile nanotube switches. A first terminal of the non-volatile nanotube switches is able to receive an electrical signal and a second terminal of the non-volatile nanotube switches is coupled to a common node that sums any electrical signals at the first terminals of the nanotube switches. The neural networks further includes transfer circuits to propagate the electrical signal, synapse circuits, and axon circuits.

Abstract: Programmable via devices and methods for the fabrication thereof are provided. In one aspect, a programmable via device is provided.

Abstract: A phase change memory in the reset state may be heated to reduce or eliminate electrical drift.