Formed Along Or From Crystallographic Terraces Or Ridges Patents (Class 977/763)
  • Patent number: 8932940
    Abstract: Embodiments of the invention provide a method for direct heteroepitaxial growth of vertical III-V semiconductor nanowires on a silicon substrate. The silicon substrate is etched to substantially completely remove native oxide. It is promptly placed in a reaction chamber. The substrate is heated and maintained at a growth temperature. Group III-V precursors are flowed for a growth time. Preferred embodiment vertical Group III-V nanowires on silicon have a core-shell structure, which provides a radial homojunction or heterojunction. A doped nanowire core is surrounded by a shell with complementary doping. Such can provide high optical absorption due to the long optical path in the axial direction of the vertical nanowires, while reducing considerably the distance over which carriers must diffuse before being collected in the radial direction. Alloy composition can also be varied. Radial and axial homojunctions and heterojunctions can be realized. Embodiments provide for flexible Group III-V nanowire structures.
    Type: Grant
    Filed: October 28, 2009
    Date of Patent: January 13, 2015
    Assignee: The Regents of the University of California
    Inventors: Deli Wang, Cesare Soci, Xinyu Bao, Wei Wei, Yi Jing, Ke Sun
  • Patent number: 8912545
    Abstract: A method is provided for fabricating a nanowire-based semiconductor structure. The method includes forming a first nanowire with a first polygon-shaped cross-section having a first number of sides. The method also includes forming a semiconductor layer on surface of the first nanowire to form a second nanowire with a second polygon-shaped cross-section having a second number of sides, the second number being greater than the first number. Further, the method includes annealing the second nanowire to remove a substantial number of vertexes of the second polygon-shaped cross-section to form the nanowire with a non-polygon-shaped cross-section corresponding to the second polygon-shaped cross-section.
    Type: Grant
    Filed: March 15, 2013
    Date of Patent: December 16, 2014
    Assignee: Semiconductor Manufacturing International Corp.
    Inventors: Deyuan Xiao, James Hong
  • Publication number: 20140151705
    Abstract: A method is provided for fabricating a nanowire-based semiconductor structure. The method includes forming a first nanowire with a first polygon-shaped cross-section having a first number of sides. The method also includes forming a semiconductor layer on surface of the first nanowire to form a second nanowire with a second polygon-shaped cross-section having a second number of sides, the second number being greater than the first number. Further, the method includes annealing the second nanowire to remove a substantial number of vertexes of the second polygon-shaped cross-section to form the nanowire with a non-polygon-shaped cross-section corresponding to the second polygon-shaped cross-section.
    Type: Application
    Filed: March 15, 2013
    Publication date: June 5, 2014
    Applicant: SEMICONDUCTOR MANUFACTURING INTERNATIONAL CORP.
    Inventors: DEYUAN XIAO, JAMES HONG
  • Publication number: 20140090870
    Abstract: Aspects of the present disclosure are directed to apparatuses and methods involving nanowires having junctions therebetween. As consistent with one or more embodiments, an apparatus includes first and second sets of nanowires, in which the second set overlaps the first set. The apparatus further includes a plurality of nanowire joining recrystallization junctions, each junction including material from a nanowire of the first set that is recrystallized into an overlapping nanowire of the second set.
    Type: Application
    Filed: October 1, 2013
    Publication date: April 3, 2014
    Applicant: The Board of Trustees of the Leland Stanford Junior University
    Inventors: Erik C. Garnett, Mark L. Brongersma, Yi Cui, Michael D. McGehee, Mark Greyson Christoforo, Wenshan Cai
  • Patent number: 8658519
    Abstract: Various embodiments provide non-planar nanowires, nanowire arrays, and nanowire networks as well as methods of their formation and applications. The non-planar nanowires and their arrays can be formed in a controlled manner on surfaces having a non-planar orientation. In embodiments, two or more adjacent nanowires from different surfaces can grow to merge together forming one or more nanowire branches and thus forming a nanowire network. In embodiments, the non-planar nanowires and nanowire networks can be used for cantilever oscillation, switching and transistor actions.
    Type: Grant
    Filed: November 14, 2012
    Date of Patent: February 25, 2014
    Assignee: STC.UNM
    Inventor: Stephen D. Hersee
  • Patent number: 8557622
    Abstract: Exemplary embodiments provide semiconductor nanowires and nanowire devices/applications and methods for their formation. In embodiments, in-plane nanowires can be epitaxially grown on a patterned substrate, which are more favorable than vertical ones for device processing and three-dimensional (3D) integrated circuits. In embodiments, the in-plane nanowire can be formed by selective epitaxy utilizing lateral overgrowth and faceting of an epilayer initially grown in a one-dimensional (1D) nanoscale opening. In embodiments, optical, electrical, and thermal connections can be established and controlled between the nanowire, the substrate, and additional electrical or optical components for better device and system performance.
    Type: Grant
    Filed: September 1, 2011
    Date of Patent: October 15, 2013
    Assignee: STC.UNM
    Inventors: Seung Chang Lee, Steven R. J. Brueck
  • Patent number: 8409450
    Abstract: An embodiment of a method of suspending a graphene membrane across a gap in a support structure includes attaching graphene to a substrate. A pre-fabricated support structure having the gap is attached to the graphene. The graphene and the pre-fabricated support structure are then separated from the substrate which leaves the graphene membrane suspended across the gap in the pre-fabricated support structure. An embodiment of a method of depositing material includes placing a support structure having a graphene membrane suspended across a gap under vacuum. A precursor is adsorbed to a surface of the graphene membrane. A portion of the graphene membrane is exposed to a focused electron beam which deposits a material from the precursor onto the graphene membrane. An embodiment of a graphene-based structure includes a support structure having a gap, a graphene membrane suspended across the gap, and a material deposited in a pattern on the graphene membrane.
    Type: Grant
    Filed: March 24, 2009
    Date of Patent: April 2, 2013
    Assignee: The Regents of the University of California
    Inventors: Alexander K. Zettl, Jannik Christian Meyer
  • Patent number: 8338818
    Abstract: Various embodiments provide non-planar nanowires, nanowire arrays, and nanowire networks as well as methods of their formation and applications. The non-planar nanowires and their arrays can be formed in a controlled manner on surfaces having a non-planar orientation. In embodiments, two or more adjacent nanowires from different surfaces can grow to merge together forming one or more nanowire branches and thus forming a nanowire network. In embodiments, the non-planar nanowires and nanowire networks can be used for cantilever oscillation, switching and transistor actions.
    Type: Grant
    Filed: December 10, 2009
    Date of Patent: December 25, 2012
    Assignee: STC.UNM
    Inventor: Stephen D. Hersee
  • Patent number: 8330090
    Abstract: A photosensitive device (100), the photosensitive device (100) comprising a substrate (101) and a plurality of vertically aligned nanowire diodes (102 to 105) provided on and/or in the substrate (101).
    Type: Grant
    Filed: April 29, 2008
    Date of Patent: December 11, 2012
    Assignee: NXP, B.V.
    Inventor: Prabhat Agarwal
  • Patent number: 8330226
    Abstract: A PRAM device includes a lower electrode, a phase-change nanowire and an upper electrode. The phase-change nanowire may be electrically connected to the lower electrode and includes a single element. The upper electrode may be electrically connected to the phase-change nanowires.
    Type: Grant
    Filed: April 25, 2012
    Date of Patent: December 11, 2012
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Tae-Yon Lee
  • Patent number: 8318297
    Abstract: In one aspect, the present invention relates to a synthetic nanostructure. In one embodiment, the synthetic nanostructure has a top region substantially comprising titanate nanowires, a middle region substantially comprising titanate nanoparticles and titanate nanowires, and a bottom region substantially comprising titanium, wherein some of the titanate nanowires of the top region are extending into the middle region, wherein the middle region is between the top region and the bottom region, and wherein some of the titanate nanowires of the top region are substantially perpendicular to the bottom surface of the titanium substrate. At least some of the titanate nanowires in the top region form 3D macroporous scaffolds with interconnected macropores.
    Type: Grant
    Filed: June 25, 2008
    Date of Patent: November 27, 2012
    Assignee: Board of Trustees of the University of Arkansas
    Inventors: Z. Ryan Tian, Joshua Epstein
  • Patent number: 8318126
    Abstract: The present invention includes a method of producing a crystalline metal oxide nanostructure. The method comprises providing a metal salt solution and providing a basic solution; placing a porous membrane between the metal salt solution and the basic solution, wherein metal cations of the metal salt solution and hydroxide ions of the basic solution react, thereby producing a crystalline metal oxide nanostructure.
    Type: Grant
    Filed: May 4, 2010
    Date of Patent: November 27, 2012
    Inventors: Stanislaus S. Wong, Hongjun Zhou
  • Patent number: 8277581
    Abstract: Nickel-iron-zinc alloy nanoparticles of the present invention are in the form of tabular particles having a thickness of 1 ?m or less and an aspect ratio of 2 or more, wherein the (220) plane which is the crystal plane of the face-centered cubic lattice is oriented on the tabular surface of the particles.
    Type: Grant
    Filed: April 10, 2008
    Date of Patent: October 2, 2012
    Assignee: Sumitomo Osaka Cement Co., Ltd.
    Inventors: Masayuki Ishizuka, Nobuhiro Hidaka
  • Patent number: 8206505
    Abstract: The inventive method for forming nano-dimensional clusters consists in introducing a solution containing a cluster-forming material into nano-pores of natural or artificial origin contained in a substrate material and in subsequently exposing said solution to a laser radiation pulse in such a way that a low-temperature plasma producing a gaseous medium in the domain of the existence thereof, wherein a cluster material is returned to a pure material by the crystallization thereof on a liquid substrate while the plasma is cooling, occurs, thereby forming mono-crystal quantum dots spliced with the substrate material. Said method makes it possible to form two- or three-dimensional cluster lattices and clusters spliced with each other from different materials. The invention also makes it possible to produce wires from different materials in the substrate nano-cavities and the quantum dots from the solution micro-drops distributed through an organic material applied to a glass.
    Type: Grant
    Filed: November 29, 2005
    Date of Patent: June 26, 2012
    Inventors: Sergei Nikolaevich Maximovsky, Grigory Avramovich Radutsky
  • Patent number: 8193029
    Abstract: A PRAM device includes a lower electrode, a phase-change nanowire and an upper electrode. The phase-change nanowire may be electrically connected to the lower electrode and includes a single element. The upper electrode may be electrically connected to the phase-change nanowires.
    Type: Grant
    Filed: June 9, 2010
    Date of Patent: June 5, 2012
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Tae-Yon Lee
  • Patent number: 8039953
    Abstract: Heat sink structures employing carbon nanotube or nanowire arrays to reduce the thermal interface resistance between an integrated circuit chip and the heat sink are disclosed. Carbon nanotube arrays are combined with a thermally conductive metal filler disposed between the nanotubes. This structure produces a thermal interface with high axial and lateral thermal conductivities.
    Type: Grant
    Filed: August 2, 2006
    Date of Patent: October 18, 2011
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Carlos Dangelo
  • Publication number: 20110174364
    Abstract: A solar cell having a nanostructure. The nanostructure may include nanowire electron conductors having a fractal structure with a relatively large surface area. The electron conductors may be loaded with nanoparticle quantum dots for absorbing photons. The dots may be immersed in a carrier or hole conductor, initially being a liquid or gel and then solidifying, for effective immersion and contact with the dots. Electrons may move flow via a load from the electron conductors to the holes of the carrier conductor. The solar cell may be fabricated, for example, with an additive process using roll-to-roll manufacturing.
    Type: Application
    Filed: January 13, 2011
    Publication date: July 21, 2011
    Applicant: HONEYWELL INTERNATIONAL INC.
    Inventor: Yue Liu
  • Publication number: 20110121434
    Abstract: A composition comprises a semiconductor substrate having a crystallographic plane oriented parallel to a surface of the substrate and at least one planar semiconductor nanowire epitaxially disposed on the substrate, where the nanowire is aligned along a crystallographic direction of the substrate parallel to the crystallographic plane. To fabricate a planar semiconductor nanowire, at least one nanoparticle is provided on a semiconductor substrate having a crystallographic plane oriented parallel to a surface of the substrate. The semiconductor substrate is heated within a first temperature window in a processing unit. Semi-conductor precursors are added to the processing unit, and a planar semiconductor nanowire is grown from the nanoparticle on the substrate within a second temperature window. The planar semiconductor nanowire grows in a crystallographic direction of the substrate parallel to the crystallographic plane.
    Type: Application
    Filed: April 24, 2009
    Publication date: May 26, 2011
    Inventors: Xiuling Li, Seth A. Fortuna
  • Patent number: 7902540
    Abstract: A lateral p-i-n photodetector is provided that includes an array of vertical semiconductor nanowires of a first conductivity type that are grown over a semiconductor substrate also of the first conductivity type. Each vertically grown semiconductor nanowires of the first conductivity type is surrounded by a thick epitaxial intrinsic semiconductor film. The gap between the now formed vertically grown semiconductor nanowires-intrinsic semiconductor film columns (comprised of the semiconductor nanowire core surrounded by intrinsic semiconductor film) is then filled by forming an epitaxial semiconductor material of a second conductivity type which is different from the first conductivity type. In a preferred embodiment, the vertically grown semiconductor nanowires of the first conductivity type are n+ silicon nanowires, the intrinsic epitaxial semiconductor layer is comprised of intrinsic epitaxial silicon, and the epitaxial semiconductor material of the second conductivity type is comprised of p+ silicon.
    Type: Grant
    Filed: May 21, 2008
    Date of Patent: March 8, 2011
    Assignee: International Business Machines Corporation
    Inventor: Guy M. Cohen
  • Publication number: 20110042641
    Abstract: The present invention generally relates to nanotechnology and, in particular, to branched nanoscale wires cases, the branched nanoscale wires may be produced using vapor-phase and/or solution-phase synthesis. Branched nanoscale wires may be grown by depositing nanoparticles onto a nanoscale wire, and segments or “branches” can then be grown from the nanoparticles. The nanoscale wire may be any nanoscale wire, for example, a semiconductor nanoscale wire, a nanoscale wire having a core and a shell. The segments may be of the same, or of different materials, than the nanoscale wire, for example, semiconductor/metal, semiconductor/semiconductor. The junction between the segment and the nanoscale wire, in some cases, is epitaxial. In one embodiment, the nanoparticles are adsorbed onto the nanoscale wire by immobilizing a positively-charged entity, such as polylysine, to the nanoscale wire, and exposing it to the nanoparticles.
    Type: Application
    Filed: September 11, 2007
    Publication date: February 24, 2011
    Applicant: President and Fellows of Harvard College
    Inventors: Charles M. Lieber, Bozhi Tian, Xiaocheng Jiang
  • Patent number: 7893423
    Abstract: A device and method associated with carbon nanowires, such as single walled carbon nanowires having a high degree of alignment are set forth herein. A catalyst layer is deposited having a predetermined crystallographic configuration so as to control a growth parameter, such as an alignment direction, a diameter, a crystallinity and the like of the carbon nanowire. The catalyst layer is etched to expose a sidewall portion. The carbon nanowire is nucleated from the exposed sidewall portion. An electrical circuit device can include a single crystal substrate, such as Silicon, and a crystallographically oriented catalyst layer on the substrate having an exposed sidewall portion. In the device, carbon nanowires are disposed on the single crystal substrate aligned in a direction associated with the crystallographic properties of the catalyst layer.
    Type: Grant
    Filed: January 21, 2010
    Date of Patent: February 22, 2011
    Assignee: Northrop Grumman Systems Corporation
    Inventors: Vincent Gambin, Roger Su-Tsung Tsai
  • Patent number: 7847325
    Abstract: A discrete trap memory, comprising a silicon substrate layer, a bottom oxide layer on the silicon substrate layer, a Fullerene layer on the bottom oxide layer, a top oxide layer on the Fullerene layer, and a gate layer on the top oxide layer; wherein the Fullerene layer comprises spherical, elliptical or endohedral Fullerenes that act as charge traps.
    Type: Grant
    Filed: March 12, 2009
    Date of Patent: December 7, 2010
    Assignee: Infineon Technologies AG
    Inventors: Gerhard Poeppel, Georg Tempel
  • Patent number: 7838943
    Abstract: A semiconductor structure in which a planar semiconductor device and a horizontal carbon nanotube transistor have a shared gate and a method of fabricating the same are provided in the present application. The hybrid semiconductor structure includes at least one horizontal carbon nanotube transistor and at least one planar semiconductor device, in which the at least one horizontal carbon nanotube transistor and the at least one planar semiconductor device have a shared gate and the at least one horizontal carbon nanotube transistor is located above a gate of the at least one planar semiconductor device.
    Type: Grant
    Filed: July 25, 2005
    Date of Patent: November 23, 2010
    Assignee: International Business Machines Corporation
    Inventors: Toshiharu Furukawa, Mark C. Hakey, Steven J. Holmes, David V. Horak, Charles W. Koburger, III, Mark E. Masters
  • Patent number: 7682943
    Abstract: A resonant tunneling diode, and other one dimensional electronic, photonic structures, and electromechanical MEMS devices, are formed as a heterostructure in a nanowhisker by forming length segments of the whisker with different materials having different band gaps.
    Type: Grant
    Filed: October 5, 2007
    Date of Patent: March 23, 2010
    Assignee: QuNano AB
    Inventors: Lars Ivar Samuelson, Bjorn Jonas Ohlsson
  • Patent number: 7678672
    Abstract: A device and method associated with carbon nanowires, such as single walled carbon nanowires having a high degree of alignment are set forth herein. A catalyst layer is deposited having a predetermined crystallographic configuration so as to control a growth parameter, such as an alignment direction, a diameter, a crystallinity and the like of the carbon nanowire. The catalyst layer is etched to expose a sidewall portion. The carbon nanowire is nucleated from the exposed sidewall portion. An electrical circuit device can include a single crystal substrate, such as Silicon, and a crystallographically oriented catalyst layer on the substrate having an exposed sidewall portion. In the device, carbon nanowires are disposed on the single crystal substrate aligned in a direction associated with the crystallographic properties of the catalyst layer.
    Type: Grant
    Filed: January 16, 2007
    Date of Patent: March 16, 2010
    Assignee: Northrop Grumman Space & Mission Systems Corp.
    Inventors: Vincent Gambin, Roger Su-Tsung Tsai
  • Patent number: 7633148
    Abstract: A plurality of conductive pads (2) are formed on a mounting surface of a mounting board. Conductive pads (11) are formed on a principal surface of a semiconductor chip (10) at positions corresponding to the conductive pads of the mounting board, when the principal surface faces toward the mounting board. A plurality of conductive nanotubes (12) extend from the conductive pads of one of the mounting board and the semiconductor chip. A press mechanism (3) presses the semiconductor chip against the mounting board and restricts a position of the semiconductor chip on the mounting surface to mount the semiconductor chip on the mounting board, in a state that tips of the conductive nanotubes are in contact with the corresponding conductive pads not formed with the conductive nanotubes.
    Type: Grant
    Filed: February 15, 2007
    Date of Patent: December 15, 2009
    Assignee: Fujitsu Limited
    Inventors: Yuji Awano, Masataka Mizukoshi, Taisuke Iwai, Tomoji Nakamura
  • Patent number: 7569847
    Abstract: One-dimensional nanostructures having uniform diameters of less than approximately 200 nm. These inventive nanostructures, which we refer to as “nanowires”, include single-crystalline homostructures as well as heterostructures of at least two single-crystalline materials having different chemical compositions. Because single-crystalline materials are used to form the heterostructure, the resultant heterostructure will be single-crystalline as well. The nanowire heterostructures are generally based on a semiconducting wire wherein the doping and composition are controlled in either the longitudinal or radial directions, or in both directions, to yield a wire that comprises different materials. Examples of resulting nanowire heterostructures include a longitudinal heterostructure nanowire (LOHN) and a coaxial heterostructure nanowire (COHN).
    Type: Grant
    Filed: January 20, 2005
    Date of Patent: August 4, 2009
    Assignee: The Regents of the University of California
    Inventors: Arun Majumdar, Ali Shakouri, Timothy D. Sands, Peidong Yang, Samuel S. Mao, Richard E. Russo, Henning Feick, Eicke R. Weber, Hannes Kind, Michael Huang, Haoquan Yan, Yiying Wu, Rong Fan
  • Patent number: 7569941
    Abstract: One-dimensional nanostructures having uniform diameters of less than approximately 200 nm. These inventive nanostructures, which we refer to as “nanowires”, include single-crystalline homostructures as well as heterostructures of at least two single-crystalline materials having different chemical compositions. Because single-crystalline materials are used to form the heterostructure, the resultant heterostructure will be single-crystalline as well. The nanowire heterostructures are generally based on a semiconducting wire wherein the doping and composition are controlled in either the longitudinal or radial directions, or in both directions, to yield a wire that comprises different materials. Examples of resulting nanowire heterostructures include a longitudinal heterostructure nanowire (LOHN) and a coaxial heterostructure nanowire (COHN).
    Type: Grant
    Filed: December 22, 2006
    Date of Patent: August 4, 2009
    Assignee: The Regents of the University of California
    Inventors: Arun Majumdar, Ali Shakouri, Timothy D. Sands, Peidong Yang, Samuel S. Mao, Richard E. Russo, Henning Feick, Eicke R. Weber, Hannes Kind, Michael Huang, Haoquan Yan, Yiying Wu, Rong Fan
  • Patent number: 7544547
    Abstract: The invention relates to a method for producing a support comprising nanoparticles (22) for the growth of nanostructures (23), said nanoparticles being organised periodically, the method being characterised in that it comprises the following steps: providing a support comprising, in the vicinity of one of its surfaces, a periodic array of crystal defects and/or stress fields (18), depositing, on said surface, a continuous layer (20) of a first material capable of catalysing the nanostructure growth reaction, fractionating the first material layer (20) by a heat treatment so as to form the first material nanoparticles (22).
    Type: Grant
    Filed: January 19, 2007
    Date of Patent: June 9, 2009
    Assignee: Commissariat a l'Energie Atomique
    Inventors: Frank Fournel, Jean Dijon, Pierre Mur
  • Publication number: 20090000539
    Abstract: An apparatus for growing a nanowire includes a crystalline surface, and a feature formed on at least a portion of the crystalline surface. The feature has a region with high surface curvature. A catalyst material is established on the region.
    Type: Application
    Filed: June 29, 2007
    Publication date: January 1, 2009
    Inventor: Theodore I. Kamins
  • Patent number: 7407872
    Abstract: Highly ordered and aligned epitaxy of III-Nitride nanowires is demonstrated in this work. <1010> M-axis is identified as a preferential nanowire growth direction through a detailed study of GaN/AlN trunk/branch nanostructures by transmission electron microscopy. Crystallographic selectivity can be used to achieve spatial and orientational control of nanowire growth. Vertically aligned (Al)GaN nanowires are prepared on M-plane AlN substrates. Horizontally ordered nanowires, extending from the M-plane sidewalls of GaN hexagonal mesas or islands demonstrate new opportunities for self-aligned nanowire devices, interconnects, and networks.
    Type: Grant
    Filed: August 19, 2005
    Date of Patent: August 5, 2008
    Assignee: Yale University
    Inventors: Jung Han, Jie Su
  • Patent number: 7345307
    Abstract: The present invention is directed to thin film transistors using nanowires (or other nanostructures such as nanoribbons, nanotubes and the like) incorporated in and/or disposed proximal to conductive polymer layer(s), and production scalable methods to produce such transistors. In particular, a composite material comprising a conductive polymeric material such as polyaniline (PANI) or polypyrrole (PPY) and one or more nanowires incorporated therein is disclosed.
    Type: Grant
    Filed: September 22, 2005
    Date of Patent: March 18, 2008
    Assignee: Nanosys, Inc.
    Inventors: Yaoling Pan, Francisco Leon, David P. Stumbo
  • Patent number: 7307271
    Abstract: A nano-colonnade structure-and methods of fabrication and interconnection thereof utilize a nanowire column grown nearly vertically from a (111) horizontal surface of a semiconductor layer to another horizontal surface of another layer to connect the layers. The nano-colonnade structure includes a first layer having the (111) horizontal surface; a second layer having the other horizontal surface; an insulator support between the first layer and the second layer that separates the first layer from the second layer. A portion of the second layer overhangs the insulator support, such that the horizontal surface of the overhanging portion is spaced from and faces the (111) horizontal surface of the first layer. The structure further includes a nanowire column extending nearly vertically from the (111) horizontal surface to the facing horizontal surface, such that the nanowire column connects the first layer to the second layer.
    Type: Grant
    Filed: November 5, 2004
    Date of Patent: December 11, 2007
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventors: M. Saif Islam, Philip J. Kuekes, Shih-Yuan Wang, Duncan R. Stewart, Shashank Sharma
  • Patent number: 7303723
    Abstract: A method for manufacturing oriented arrays of ceramic or metal oxide nanostructures, such as titania (TiO2) nanofibers. The nanofibers are formed on the surface of a body that is first sintered at a temperature in the range of about 1,100 to about 1,400 degrees Celsius. Subsequently, the surface is exposed to an H2-bearing gas, such as H2 and N2 in a ratio of about 5:95 at about 700 degrees Celsius for about 8 hours. During heat treatment in the gas phase reaction, sintered titania grains transform into arrays of nanofibers oriented in the same crystallographic direction.
    Type: Grant
    Filed: October 3, 2003
    Date of Patent: December 4, 2007
    Assignee: The Ohio State University Research Foundation
    Inventors: Sheikh A. Akbar, Sehoon Yoo, Kenneth H. Sandhage
  • Patent number: 7255745
    Abstract: Iridium oxide (IrOx) nanowires and a method forming the nanowires are provided. The method comprises: providing a growth promotion film with non-continuous surfaces, having a thickness in the range of 0.5 to 5 nanometers (nm), and made from a material such as Ti, Co, Ni, Au, Ta, polycrystalline silicon (poly-Si), SiGe, Pt, Ir, TiN, or TaN; establishing a substrate temperature in the range of 200 to 600 degrees C.; introducing oxygen as a precursor reaction gas; introducing a (methylcyclopentadienyl)(1,5-cyclooctadiene)iridium(I) precursor; using a metalorganic chemical vapor deposition (MOCVD) process, growing IrOx nanowires from the growth promotion film surfaces. The IrOx nanowires have a diameter in the range of 100 to 1000 ?, a length in the range of 1000 ? to 2 microns, an aspect ratio (length to width) of greater than 50:1. Further, the nanowires include single-crystal nanowire cores covered with an amorphous layer having a thickness of less than 10 ?.
    Type: Grant
    Filed: October 21, 2004
    Date of Patent: August 14, 2007
    Assignee: Sharp Laboratories of America, Inc.
    Inventors: Fengyan Zhang, Robert A. Barrowcliff, Sheng Teng Hsu
  • Patent number: 7132677
    Abstract: An GaN light emitting diode (LED) having a nanorod (or, nanowire) structure is disclosed. The GaN LED employs GaN nanorods in which a n-type GaN nanorod, an InGaN quantum well and a p-type GaN nanorod are subsequently formed in a longitudinal direction by inserting the InGaN quantum well into a p-n junction interface of the p-n junction GaN nanorod. In addition, a plurality of such GaN nanorods are arranged in an array so as to provide an LED having much greater brightness and higher light emission efficiency than a conventional laminated-film GaN LED.
    Type: Grant
    Filed: February 13, 2004
    Date of Patent: November 7, 2006
    Assignee: Dongguk University
    Inventors: Hwa-Mok Kim, Tae-Won Kang, Kwan-Soo Chung
  • Patent number: 7110299
    Abstract: A memory is described which has memory cells that store data using hot electron injection. The data is erased through electron tunneling. The memory cells are described as floating gate transistors wherein the floating gate is fabricated using a conductive layer of nanocrystalline silicon particles. Each nanocrystalline silicon particle has a diameter of about 10 ? to 100 ?. The nanocrystalline silicon particles are in contact such that a charge stored on the floating gate is shared between the particles. The floating gate has a reduced electron affinity to allow for data erase operations using lower voltages.
    Type: Grant
    Filed: January 3, 2005
    Date of Patent: September 19, 2006
    Assignee: Micron Technology, Inc.
    Inventor: Leonard Forbes