Abstract: A device includes a first channel layer, a second channel layer, a gate structure, a source/drain epitaxial structure, and a source/drain contact. The first channel layer and the second channel layer are arranged above the first channel layer in a spaced apart manner over a substrate. The gate structure surrounds the first and second channel layers. The source/drain epitaxial structure is connected to the first and second channel layers. The source/drain contact is connected to the source/drain epitaxial structure. The second channel layer is closer to the source/drain contact than the first channel layer is to the source/drain contact, and the first channel layer is thicker than the second channel layer.

Abstract: FETs including a gated oxide semiconductor spacer interfacing with a channel semiconductor. Transistors may incorporate a non-oxide channel semiconductor, and one or more oxide semiconductors disposed proximal to the transistor gate electrode and the source/drain semiconductor, or source/drain contact metal. In advantageous embodiments, the oxide semiconductor is to be gated by a voltage applied to the gate electrode (i.e., gate voltage) so as to switch the oxide semiconductor between insulating and semiconducting states in conjunction with gating the transistor's non-oxide channel semiconductor between on and off states.

Abstract: Nanowire devices and fin devices are formed in a first region and a second region of a substrate. To form the devices, alternating layers of a first material and a second material are formed, inner spacers are formed adjacent to the layers of the first material, and then the layers of the first material are removed to form nanowires without removing the layers of the first material within the second region. Gate structures of gate dielectrics and gate electrodes are formed within the first region and the second region in order to form the nanowire devices in the first region and the fin devices in the second region.

Abstract: Techniques for dielectric isolation in bulk nanosheet devices are provided. In one aspect, a method of forming a nanosheet device structure with dielectric isolation includes the steps of: optionally implanting at least one dopant into a top portion of a bulk semiconductor wafer, wherein the at least one dopant is configured to increase an oxidation rate of the top portion of the bulk semiconductor wafer; forming a plurality of nanosheets as a stack on the bulk semiconductor wafer; patterning the nanosheets to form one or more nanowire stacks and one or more trenches between the nanowire stacks; forming spacers covering sidewalls of the nanowire stacks; and oxidizing the top portion of the bulk semiconductor wafer through the trenches, wherein the oxidizing step forms a dielectric isolation region in the top portion of the bulk semiconductor wafer. A nanowire FET and method for formation thereof are also provided.

Abstract: Embodiments disclosed herein include semiconductor devices and methods of forming such devices. In an embodiment, a semiconductor device comprises a substrate, a first transistor over the substrate, where the first transistor comprises a vertical stack of first semiconductor channels, and a first gate dielectric surrounding each of the first semiconductor channels. The first gate dielectric has a first thickness. In an embodiment, the semiconductor device further comprises a second transistor over the substrate, where the second transistor comprises a second semiconductor channel. The second semiconductor channel comprises pair of sidewalls and a top surface. In an embodiment, a second gate dielectric is over the pair of sidewalls and the top surface of the fin, where the second gate dielectric has a second thickness that is greater than the first thickness.

Abstract: A semiconductor device according to the present disclosure includes a fin structure over a substrate, a vertical stack of silicon nanostructures disposed over the fin structure, an isolation structure disposed around the fin structure, a germanium-containing interfacial layer wrapping around each of the vertical stack of silicon nanostructures, a gate dielectric layer wrapping around the germanium-containing interfacial layer, and a gate electrode layer wrapping around the gate dielectric layer.

Abstract: A system and method for matching conformers of different molecule are provided. The methods for matching conformers of different molecule include calculating average electron density (AED) values corresponding to a most electronegative group of the different molecules, and matching conformers of the different molecules based on a common AED.

Abstract: A thin-film transistor includes a flexible substrate, an amorphous semiconductor channel layer on the flexible substrate, an organic material piezoelectric stress gate layer adjacent to the amorphous semiconductor channel layer, a gate electrode adjacent to the organic material piezoelectric stress gate layer, and a source electrode and drain electrode coupled to the organic material piezoelectric stress gate layer.

Abstract: A method for making metal nanorods comprises combining a source of metal cations with at least one surfactant to form a mixture, wherein the metal cations are reduced and the metal nanorods are produced. Metal nanorods produced by the method and uses thereof. The metal nanorods are useful in devices such as lateral flow devices.

Abstract: An ultra-long silver nanowire material and a fabrication method thereof are provided. The fabrication method includes the following steps: step 1: adding a reducing sugar and polyvinylpyrrolidone (PVP) to deionized water to obtain a clear solution; step 2: mixing the clear solution with a metal ion solution to obtain a mixed solution A; step 3: mixing the mixed solution A with a halide solution to obtain a mixed solution B; step 4: adding a silver ion-containing solution dropwise to the mixed solution B to obtain a reaction solution and conducting a reaction at 110° C. to 130° C. for 14 h to 20 h to obtain a flocculent product; and step 5: subjecting the flocculent product to sedimentation washing with deionized water and absolute ethanol successively to obtain the ultra-long silver nanowire material. The fabrication method of the present disclosure is low in cost, environmentally friendly, and conducive to industrial production.

Abstract: Self-aligned gate endcap (SAGE) architectures with gate-all-around devices above insulator substrates, and methods of fabricating self-aligned gate endcap (SAGE) architectures with gate-all-around devices above insulator substrates, are described. In an example, an integrated circuit structure includes a semiconductor nanowire above an insulator substrate and having a length in a first direction. A gate structure is around the semiconductor nanowire, the gate structure having a first end opposite a second end in a second direction, orthogonal to the first direction. A pair of gate endcap isolation structures is included. The first of the pair of gate endcap isolation structures is directly adjacent to the first end of the gate structure, and the second of the pair of gate endcap isolation structures is directly adjacent to the second end of the gate structure.

Abstract: Described are various embodiments of a system and method for selectively identifying the presence of a designated chemical species within a chemical sample using a two-dimensional sensor, which, when exposed to illumination, provides a differentiable adsorption sensor response signal for chemical identification.

Abstract: Provided are an antenna and a preparation method thereof, a phase shifter, and a communication device. The antenna includes a first electrode, a second electrode, a third electrode, and a photodielectric variable layer. The first electrode and the second electrode are respectively disposed on opposite two sides of the photodielectric variable layer. The first electrode includes a plurality of transmission electrodes, and the plurality of transmission electrodes are configured to transmit an electrical signal. The second electrode is provided with a fixed potential. The third electrode includes a plurality of radiator units, and the plurality of radiator units are configured to send the electrical signal. The antenna further includes at least one light-emitting element configured to emit light irradiated to the photodielectric variable layer to change a dielectric constant of the photodielectric variable layer.

Abstract: Provided is an all-solid-state battery capable of suppressing a rise in the resistance increase ratio thereof. The all-solid-state battery includes an anode active material layer containing an alloy-based active material, a first fibrous carbon, and a second fibrous carbon, wherein when a fiber diameter of the first fibrous carbon is defined as A, and a fiber diameter of the second fibrous carbon is defined as B, the ratio of A to B is 10 to 300, and when the proportion (wt %) of the first fibrous carbon to the alloy-based active material is defined as X, and the proportion (wt %) of the second fibrous carbon to the alloy-based active material is defined as Y, the proportion ({Y/(X+Y)}×100%) of the contained second fibrous carbon to a total of the first fibrous carbon and the second fibrous carbon is 0.5% to 10%.

Abstract: This complementary switch element includes: a first TFET having a first conductive channel; and a second TFET having a second conductive channel. Each of the first TFET and the second TFET includes: a group IV semiconductor substrate doped in a first conductive type; a nanowire which is formed of a group III-V compound semiconductor and is disposed on the group IV semiconductor substrate; a first electrode connected to the group IV semiconductor substrate; a second electrode connected to the nanowire; and a gate electrode. The nanowire includes a first area connected to the group IV semiconductor substrate and a second area doped in a second conductive type. In the first TFET, the second electrode is a source electrode, and the first electrode is a drain electrode. In the second TFET, the first electrode is a source electrode, and the second electrode is a drain electrode.

Abstract: A nanostructured cross-wire memory architecture is provided that can interface with conventional semiconductor technologies and be electrically accessed and read. The architecture links lower and upper sets of generally parallel nanowires oriented crosswise, with a memory element that has a characteristic conductance. Each nanowire end is attached to an electrode. Conductance of the linkages in the gap between the wires encodes the information. The nanowires may be highly-conductive, self-assembled, nucleic acid-based nanowires enhanced with dopants including metal ions, carbon, metal nanoparticles and intercalators. Conductance of the memory elements can be controlled by sequence, length, conformation, doping, and number of pathways between nanowires. A diode can also be connected in series with each of the memory elements. Linkers may also be redox or electroactive switching molecules or nanoparticles where the charge state changes the resistance of the memory element.

Abstract: Stable, macroscopic single-crystal chiral liquid crystal compositions are described. The compositions include a single-crystal chiral liquid crystal material on a patterned surface. The patterned surface seeds a particular crystallographic orientation at the substrate-liquid crystal interface. Also described are methods of forming the single-crystal chiral liquid crystal compositions.

Abstract: Sensors for detecting analytes are disclosed. In various implementations, the sensing device may include a substrate and a sensor array. The sensor array may be arranged on the substrate, and may include a plurality of sensors. In some implementations, at least two of the sensors may include a first carbon-based sensing material disposed between a first pair of electrodes, and a second carbon-based sensing material disposed between a second pair of electrodes. The first carbon-based sensing material may be configured to detect a presence of each analyte of a group of analytes, and the second carbon-based sensing material may be configured to confirm the presence of each analyte of a subset of the group of analytes. In some instances, the group of analytes includes at least twice as many different analytes as the subset of analytes.

Abstract: A method for fabricating a three-dimensional (3D) static random-access memory (SRAM) architecture using catalyst influenced chemical etching (CICE). Utilizing CICE, semiconductor fins can be etched with no etch taper, smooth sidewalls and no maximum height limitation. CICE enables stacking of as many nanosheet layers a desired and also enables a 3D stacked architecture for SRAM cells. Furthermore, CICE can be used to etch silicon waveguides thereby creating waveguides with smooth sidewalls to improve transmission efficiency and, for photon-based quantum circuits, to eliminate charge fluctuations that may affect photon indistinguishability.

Abstract: Electrical storage devices (10,38) are provided with pasted negative electrodes (12) and pasted positive electrodes (15) with porous separators (18) between them, with current collectors (20,22) disposed between the separator (18) and the negative and positive pastes (13,16), respectively.

Abstract: Provided is a button device including a humidity sensor. The button device includes a substrate having a plurality of sensing regions, a housing on the substrate, the housing separating a first sensing region of the plurality of sensing regions from other sensing regions, a porous structure within the housing, the porous structure having through-holes, a first electrode on the porous structure, a second electrode on the porous structure, the second electrode being electrically connected to the first electrode through the porous structure, and a temperature sensor disposed adjacent to the first sensing region to sense a temperature of the first sensing region, The porous structure includes a body having an outer surface defining the through-holes, the body having an air gap therein.

Abstract: Provided here is a method of manufacturing a lattice electrode useful in an energy storage device such as a battery or capacitor. A lattice electrode useful in an energy storage device such as a battery or capacitor also is provided, along with energy storage devices such as batteries or capacitors.

Abstract: A light emitting device for emitting UVC radiation. The device comprises a substrate and a patterned layer. The patterned layer comprises a plurality of mask regions on the substrate. Exposed portions of the substrate are disposed between the mask regions. A plurality of nanostructures are disposed on the exposed portions of the substrate and over the mask regions, the plurality of nanostructures being a single crystal semiconductor and comprising a core tip. An active layer is disposed over the plurality of nanostructures. The active layer is a quantum well structure and comprises at least one material chosen from AIN, AlGaN and GaN. A p-doped layer is disposed over the active layer. Both the active layer and the p-doped layer are conformal to the plurality of nanostructures so as to form an emitter tip over the core tip.

Abstract: A method forms heterogeneous complementary FETs and a related semiconductor structure. The method comprises forming a layered nanosheet stack comprising two layers of a first channel material alternating with two layers of a second channel material, depositing a dielectric layer on a top layer of the nanosheet stack, and forming a checkered mask material with at least a first and a second row above the dielectric material. The first and the second row are distanced from each other. The method removes the first channel material and the second channel material outside an area of the checkered mask material, resulting in the at least a first row of pillars and a second row of pillars of layered nanosheet stacks. The method selectively removes in each of the pillars of the first stripe the second channel material.

Abstract: According to one aspect of the present invention, a silver nanowire mesh (Ag NW-mesh) electrode and a fabricating method thereof. The Ag NW-mesh electrode includes a flexible substrate; and a mesh pattern layer which is disposed on the flexible substrate and in which a plurality of first meal lines and a plurality of second metal lines are composed of Ag NWs and intersect each other in an orthogonal or diagonal direction to form a grid pattern, wherein the first metal lines and the second metal lines of the mesh pattern layer form an angle of 35 degrees to 55 degrees with respect to a bending direction.

Abstract: A memory device includes a bottom electrode, an insulating layer, and a top electrode. The bottom electrode includes a plurality of carbon nanotubes. The insulating layer is disposed over the plurality of carbon nanotubes. The top electrode includes a graphene layer separated from the plurality of carbon nanotubes by the insulating layer.

Abstract: A method for making a field effect transistor includes providing a graphene nanoribbon composite structure. The graphene nanoribbon composite structure includes a substrate and a plurality of graphene nanoribbons spaced apart from each other. The plurality of graphene nanoribbons are located on the substrate and extend substantially along a same direction, and each of the plurality of graphene nanoribbons includes a first end and a second end opposite to the first end. A source electrode is formed on the first end, and a drain electrode is formed on the second end. The source electrode and the drain electrode are electrically connected to the plurality of graphene nanoribbons. An insulating layer is formed on the plurality of graphene nanoribbons, and the plurality of graphene nanoribbons are between the insulating layer and the substrate. A gate is formed on a surface of the insulating layer away from the substrate.

Abstract: A piezoelectric substrate attachment structure including a press section pressed by contact, a piezoelectric substrate provided adjacent to the press section, and a base section provided adjacent to the piezoelectric substrate on an opposite side from the press section. The following relationship Equation (a) is satisfied: da/E?a<db/E?b??(a) wherein da is a thickness of the press section in a direction of adjacency to the piezoelectric substrate, E?a is a storage modulus of the press section from dynamic viscoelastic analysis, db is a thickness of the base section in the adjacency direction, and E?b is a storage modulus of the base section from dynamic viscoelastic analysis.

Abstract: An apparatus that includes a substrate divided into a plurality of different regions, where the substrate remains physically together. A first device located in a first region of the plurality of different regions, where the first device has a first height. A second device located in a second region of the plurality of different regions. The second device has a second height and the second device is a different device from the first device. A third device located in a third region of the plurality of different regions. The third device has a third height and the third device is a different device from the first device and the second device. The second height is smaller than the first height.

Abstract: A light-emitting element includes: a first conductive semiconductor layer; a plurality of rods disposed on the first conductive semiconductor layer, the rods comprising a first conductive semiconductor; a first insulating film disposed on a surface of the first conductive semiconductor layer while being absent under the rods; a plurality of light-emitting layers disposed on lateral surfaces of the rods; a plurality of second conductive semiconductor layers disposed on outer sides of the light-emitting layers; and a plurality of second insulating films disposed at upper ends of the rods.

Abstract: The filter of a gas sensor comprises an inorganic porous support supporting both an organic sulfonic acid compound including sulfo group (—SO3H) and a Lewis acid having at least a metal element of transitional metal elements, Al element, Ga element, In element, Ge element, and Sn element. The Lewis acid loaded in the inorganic porous support adsorbs low concentration siloxanes. The organic sulfonic acid compound including sulfo group polymerizes adsorbed siloxanes in the filter so as not to desorb from the filter.

Abstract: A method of fabricating a semiconductor device is provided. An initial stack of layers is formed over a substrate. The initial stack alternates between a first material layer and a second material layer that has a different composition from the first material layer. The initial stack is divided into a first stack and a second stack. First GAA transistors are formed in the first stack by using the first material layers as respective channel regions for the first GAA transistors and using the second material layers as respective replacement gates for the first GAA transistors. Second GAA transistors are formed in the second stack by using the second material layers as respective channel regions for the second GAA transistors and using the first material layers as respective replacement gates for the second GAA transistors. The second GAA transistors are vertically offset from the first GAA transistors.

Abstract: A method of manufacturing a semiconductor nanowire semiconductor device is described. The method includes forming an amorphous channel material layer on a substrate, patterning the channel material layer to form semiconductor nanowires extending in a lateral direction on the substrate, and forming a cover layer covering an upper of the semiconductor nanowire. The cover layer and the nanowire are patterned to form a trench exposing a side section of an one end of the semiconductor nanowire and a catalyst material layer is formed in contact with a side surface of the semiconductor nanowire, and metal induced crystallization (MIC) by heat treatment is performed to crystallize the semiconductor nanowire in a length direction of the nanowire from the one end of the semiconductor nanowire in contact with the catalyst material.

Abstract: An integrated circuit structure includes: a semiconductor nanowire extending in a length direction and including a body portion; a gate dielectric surrounding the body portion; a gate electrode insulated from the body portion by the gate dielectric; a semiconductor source portion adjacent to a first side of the body portion; and a semiconductor drain portion adjacent to a second side of the body portion opposite the first side, the narrowest dimension of the second side of the body portion being smaller than the narrowest dimension of the first side. In an embodiment, the nanowire has a conical tapering. In an embodiment, the gate electrode extends along the body portion in the length direction to the source portion, but not to the drain portion. In an embodiment, the drain portion at the second side of the body portion has a lower dopant concentration than the source portion at the first side.

Abstract: A magnetoresistive element comprises a novel iPMA cap layer on a surface of a ferromagnetic recording layer. The iPMA cap layer introduces giant interfacial magnetic anisotropy energies (G-iMAE) on the interface between the recording layer and the iPMA cap layer, yielding a giant interfacial perpendicular magnetic anisotropy (G-iPMA) of the recording layer.

Abstract: A silver nanowire (SNW) protection layer structure includes a substrate; a SNW layer, disposed on the substrate and covering only a partial region of a surface of the substrate, the SNW layer including a plurality of SNW channels; and a SNW protection layer, disposed on the SNW layer and covering a region corresponding to the plurality of SNW channels, the SNW protection layer including a light-resistant antioxidant. A manufacturing method for the SNW protection layer structure above is further provided. The SNW protection layer structure and the manufacturing method thereof are applicable in a touch sensor.

Abstract: The present disclosure is directed to methods and embedding battery tab attachment structures within composites of electrode active materials and carbon nanotubes, which lack binder and lack collector foils, and the resulting self-standing electrodes. Such methods and the resulting self-standing electrodes may facilitate the use of such composites in battery and power applications.

Abstract: Fabricating a doped bismuth vanadate electrode includes spray coating a substrate with an aqueous solution with vanadium-containing anions and bismuth-containing cations to yield a coated substrate, heating the coated substrate to form crystalline bismuth vanadate on the substrate, and doping the crystalline bismuth vanadate with lithium ions to yield a doped bismuth vanadate electrode.

Abstract: A method for manufacturing a stacked gate-all-around nano-sheet CMOS device, including: providing a substrate with a fin structure, where a channel layer for an NMOS is a sacrificial layer for a PMOS, a channel layer for the PMOS is a sacrificial layer for the NMOS; and mobility of holes in the second material is greater than mobility of holes in the first material; forming a dummy gate stack extending across the fin structure; forming source-or-drain regions in the fin structure at two sides of the dummy gate stack; removing the dummy gate stack and the sacrificial layers covered by the dummy gate stack, to expose a surface of a part of the channel layer that is located between the source-or-drain regions, where a nano-sheet array is formed by the channel layer with the exposed surface; and forming a gate stack structure surrounding each nano sheet in the nano-sheet array.

Abstract: Disclosed is a system for detecting contaminants in a sample fluid. The system has a colloidal dispersion circuit with a reservoir containing a colloidal dispersion with colloidal particles capable of exhibiting localized surface plasmon resonance (“LSPR particles”), a Raman spectrometer/flow cell and a pump for circulating the colloidal dispersion through the colloidal dispersion circuit. A colloidal dispersion level sensor measures the extent of colloidal dispersion in the colloidal dispersion circuit. A permeation valve diverts the colloidal dispersion in the colloidal dispersion circuit through an ultra-filtration membrane with a pore size smaller than the LSPR particles, thus preventing the LSPR particles from passing through. The sample may be introduced into the colloidal dispersion circuit through a fluid sample injection valve. A processor is connected to the Raman spectrometer/flow cell, the pump, the permeation valve, the colloidal dispersion level sensor, and the fluid sample injection port.

Abstract: The present invention provides a micro-LED chip, a manufacturing method of the micro-LED chip, and a display panel. The micro-LED chip includes a plurality of sub-chips connected in series. The first sub-chip and the last sub-chip are connected to a first electrode and a second electrode, respectively. Accordingly, a voltage across the micro-LED chip is increased, power consumption of a driving thin film transistor (TFT) is reduced, and a high power consumption problem of driving TFTs in conventional micro-LED displays is improved.

Abstract: Provided are organic metal halide crystals having a 1D nanotube structure. The metal halide crystals may have a unit cell that includes two or more face-sharing metal halide dimers. The metal halide crystals also may include organic cations. Methods of forming metal halide crystals having a 1D nanotube structure also are provided.

Abstract: A quantum rod luminescent display device includes a first substrate having a plurality of pixel regions; a plurality of first electrodes alternately arranged with a plurality of second electrodes in each of the plurality of pixel regions; a plurality of quantum rod compound layers over the first electrodes and the second electrodes, respectively in each of the plurality of pixel regions, each of the quantum rod compound layers including a quantum rod having a core, a shell surrounding the core, and an electron acceptor; a second substrate facing the first substrate; and a backlight unit at an outer surface of the first substrate. The electron acceptor is attached to or adjacent to the quantum rod.

Abstract: A method of fabricating an electronic device includes the following steps. At least one first set and at least one second set of nanowires and pads are etched in an SOI layer of an SOI wafer. A first gate stack is formed that surrounds at least a portion of each of the first set of nanowires that serves as a channel region of a capacitor device. A second gate stack is formed that surrounds at least a portion of each of the second set of nanowires that serves as a channel region of a FET device. Source and drain regions of the FET device are selectively doped. A first silicide is formed on the source and drain regions of the capacitor device that extends at least to an edge of the first gate stack. A second silicide is formed on the source and drain regions of the FET device.

Abstract: Device for forming, on a nanowire made of a semiconductor, an alloy of this semiconductor with a metal or metalloid by bringing this nanowire into contact with electrically conductive metal or metalloid probes and Joule heating the nanowire at the points of contact with the probes so as to form an alloy such as a silicide. Application to the production of controlled-channel-length metal-silicide transistors.

Abstract: Various examples are provided for pillar array photo detectors. In one example, among others, a photo detection system includes an array of substantially aligned photo sensitive nanorods extending between first and second electrodes, and a plurality of resistance monitoring circuits coupled at different positions about the circumference of the electrodes. In another example, a photo detector includes first and second electrodes, and an array of substantially aligned photo sensitive nanorods extending between the substantially parallel electrodes. Light passing through an electrode excites electrons in the photo sensitive nanorods that are illuminated by the light.

Abstract: An inorganic fiber structure comprising inorganic nanofibers having an average fiber diameter of 3 ?m or less, in which an entirety including the inside thereof is adhered with an inorganic adhesive, and the porosity thereof is 90% or more, is disclosed.

Abstract: A piezo-resistive MEMS resonator comprising an anchor, a resonator mounted on the anchor, an actuator mounted to apply an electrostatic force on the resonator and a piezo-resistive read-out means comprising a nanowire coupled to the resonator.

Abstract: A method of manufacturing a thermal interface material, comprising providing a sheet comprising nano-scale fibers, the sheet having at least one exposed surface; and stabilizing the fibers with a stabilizing material disposed in at least a portion of a void space between the fibers in the sheet. The fibers may be CNT's or metallic nano-wires. Stabilizing may include infiltrating the fibers with a polymerizable material. The polymerizable material may be mixed with nano- or micro-particles. The composite system may include two films, with the fibers in between, to create a sandwich. Each capping film may include two sub films: a palladium film closer to the stabilizing material to improve adhesion; and a nano-particle film for contact with a device to be cooled or a heat sink.

Abstract: An integrated circuit device includes a first transistor having a first channel between a first source/drain, and a second transistor having a second channel between a second source/drain. The first transistor operates based on a first amount of current and the second transistor operates based on a second amount of current different from the first amount of current. The first and second channels have fixed channel widths. The fixed channel widths may be based on fins or nanowires included in the first and second transistors.