Nanowire Or Quantum Wire (axially Elongated Structure Having Two Dimensions Of 100 Nm Or Less) Patents (Class 977/762)
  • Patent number: 11913901
    Abstract: Sensors for detecting analytes are disclosed. In various implementations, the sensing device may include a substrate and a sensor array. The sensor array may be arranged on the substrate, and may include a plurality of sensors. In some implementations, at least two of the sensors may include a first carbon-based sensing material disposed between a first pair of electrodes, and a second carbon-based sensing material disposed between a second pair of electrodes. The first carbon-based sensing material may be configured to detect a presence of each analyte of a group of analytes, and the second carbon-based sensing material may be configured to confirm the presence of each analyte of a subset of the group of analytes. In some instances, the group of analytes includes at least twice as many different analytes as the subset of analytes.
    Type: Grant
    Filed: February 22, 2021
    Date of Patent: February 27, 2024
    Assignee: Lyten, Inc.
    Inventors: Sung H. Lim, Hossein-Ali Ghezelbash, Chiapu Chang, George Clayton Gibbs, Anurag Kumar
  • Patent number: 11881435
    Abstract: A method for fabricating a three-dimensional (3D) static random-access memory (SRAM) architecture using catalyst influenced chemical etching (CICE). Utilizing CICE, semiconductor fins can be etched with no etch taper, smooth sidewalls and no maximum height limitation. CICE enables stacking of as many nanosheet layers a desired and also enables a 3D stacked architecture for SRAM cells. Furthermore, CICE can be used to etch silicon waveguides thereby creating waveguides with smooth sidewalls to improve transmission efficiency and, for photon-based quantum circuits, to eliminate charge fluctuations that may affect photon indistinguishability.
    Type: Grant
    Filed: May 3, 2022
    Date of Patent: January 23, 2024
    Assignee: Board of Regents, The University of Texas System
    Inventors: Sidlgata V. Sreenivasan, Akhila Mallavarapu, Jaydeep Kulkarni, Michael Watts, Sanjay Banerjee
  • Patent number: 11855293
    Abstract: Electrical storage devices (10,38) are provided with pasted negative electrodes (12) and pasted positive electrodes (15) with porous separators (18) between them, with current collectors (20,22) disposed between the separator (18) and the negative and positive pastes (13,16), respectively.
    Type: Grant
    Filed: April 5, 2021
    Date of Patent: December 26, 2023
    Assignee: Lukatit Investments 12 (Pty) Ltd
    Inventor: Jan Petrus Human
  • Patent number: 11828718
    Abstract: Provided is a button device including a humidity sensor. The button device includes a substrate having a plurality of sensing regions, a housing on the substrate, the housing separating a first sensing region of the plurality of sensing regions from other sensing regions, a porous structure within the housing, the porous structure having through-holes, a first electrode on the porous structure, a second electrode on the porous structure, the second electrode being electrically connected to the first electrode through the porous structure, and a temperature sensor disposed adjacent to the first sensing region to sense a temperature of the first sensing region, The porous structure includes a body having an outer surface defining the through-holes, the body having an air gap therein.
    Type: Grant
    Filed: May 6, 2021
    Date of Patent: November 28, 2023
    Assignee: Electronics and Telecommunications Research Institute
    Inventors: Choon Gi Choi, Mondal Shuvra, Bok Ki Min, Yoonsik Yi
  • Patent number: 11817588
    Abstract: Provided here is a method of manufacturing a lattice electrode useful in an energy storage device such as a battery or capacitor. A lattice electrode useful in an energy storage device such as a battery or capacitor also is provided, along with energy storage devices such as batteries or capacitors.
    Type: Grant
    Filed: October 4, 2019
    Date of Patent: November 14, 2023
    Assignees: Carnegie Mellon University, The Curators of the University of Missouri
    Inventors: Rahul Panat, Jie Li, Jonghyun Park, Mohammad Sadeq Saleh
  • Patent number: 11769858
    Abstract: A light emitting device for emitting UVC radiation. The device comprises a substrate and a patterned layer. The patterned layer comprises a plurality of mask regions on the substrate. Exposed portions of the substrate are disposed between the mask regions. A plurality of nanostructures are disposed on the exposed portions of the substrate and over the mask regions, the plurality of nanostructures being a single crystal semiconductor and comprising a core tip. An active layer is disposed over the plurality of nanostructures. The active layer is a quantum well structure and comprises at least one material chosen from AIN, AlGaN and GaN. A p-doped layer is disposed over the active layer. Both the active layer and the p-doped layer are conformal to the plurality of nanostructures so as to form an emitter tip over the core tip.
    Type: Grant
    Filed: February 8, 2022
    Date of Patent: September 26, 2023
    Assignee: THE BOEING COMPANY
    Inventors: Shanying Cui, Danny Kim
  • Patent number: 11756837
    Abstract: A method forms heterogeneous complementary FETs and a related semiconductor structure. The method comprises forming a layered nanosheet stack comprising two layers of a first channel material alternating with two layers of a second channel material, depositing a dielectric layer on a top layer of the nanosheet stack, and forming a checkered mask material with at least a first and a second row above the dielectric material. The first and the second row are distanced from each other. The method removes the first channel material and the second channel material outside an area of the checkered mask material, resulting in the at least a first row of pillars and a second row of pillars of layered nanosheet stacks. The method selectively removes in each of the pillars of the first stripe the second channel material.
    Type: Grant
    Filed: March 17, 2021
    Date of Patent: September 12, 2023
    Assignee: International Business Machines Corporation
    Inventors: Cezar Bogdan Zota, Clarissa Convertino, Kirsten Emilie Moselund
  • Patent number: 11735330
    Abstract: According to one aspect of the present invention, a silver nanowire mesh (Ag NW-mesh) electrode and a fabricating method thereof. The Ag NW-mesh electrode includes a flexible substrate; and a mesh pattern layer which is disposed on the flexible substrate and in which a plurality of first meal lines and a plurality of second metal lines are composed of Ag NWs and intersect each other in an orthogonal or diagonal direction to form a grid pattern, wherein the first metal lines and the second metal lines of the mesh pattern layer form an angle of 35 degrees to 55 degrees with respect to a bending direction.
    Type: Grant
    Filed: May 25, 2021
    Date of Patent: August 22, 2023
    Assignee: KOREA INSTITUTE OF SCIENCE AND TECHNOLOGY
    Inventors: Sang Woo Kim, Seong Jun Kim
  • Patent number: 11665986
    Abstract: A memory device includes a bottom electrode, an insulating layer, and a top electrode. The bottom electrode includes a plurality of carbon nanotubes. The insulating layer is disposed over the plurality of carbon nanotubes. The top electrode includes a graphene layer separated from the plurality of carbon nanotubes by the insulating layer.
    Type: Grant
    Filed: December 17, 2021
    Date of Patent: May 30, 2023
    Assignee: NANYA TECHNOLOGY CORPORATION
    Inventor: Wei-Chuan Fang
  • Patent number: 11658232
    Abstract: A method for making a field effect transistor includes providing a graphene nanoribbon composite structure. The graphene nanoribbon composite structure includes a substrate and a plurality of graphene nanoribbons spaced apart from each other. The plurality of graphene nanoribbons are located on the substrate and extend substantially along a same direction, and each of the plurality of graphene nanoribbons includes a first end and a second end opposite to the first end. A source electrode is formed on the first end, and a drain electrode is formed on the second end. The source electrode and the drain electrode are electrically connected to the plurality of graphene nanoribbons. An insulating layer is formed on the plurality of graphene nanoribbons, and the plurality of graphene nanoribbons are between the insulating layer and the substrate. A gate is formed on a surface of the insulating layer away from the substrate.
    Type: Grant
    Filed: March 19, 2021
    Date of Patent: May 23, 2023
    Assignees: Tsinghua University, HON HAI PRECISION INDUSTRY CO., LTD.
    Inventors: Tian-Fu Zhang, Li-Hui Zhang, Yuan-Hao Jin, Qun-Qing Li, Shou-Shan Fan
  • Patent number: 11647675
    Abstract: A piezoelectric substrate attachment structure including a press section pressed by contact, a piezoelectric substrate provided adjacent to the press section, and a base section provided adjacent to the piezoelectric substrate on an opposite side from the press section. The following relationship Equation (a) is satisfied: da/E?a<db/E?b??(a) wherein da is a thickness of the press section in a direction of adjacency to the piezoelectric substrate, E?a is a storage modulus of the press section from dynamic viscoelastic analysis, db is a thickness of the base section in the adjacency direction, and E?b is a storage modulus of the base section from dynamic viscoelastic analysis.
    Type: Grant
    Filed: September 22, 2017
    Date of Patent: May 9, 2023
    Assignee: Mitsui Chemicals, Inc.
    Inventors: Kazuhiro Tanimoto, Masahiko Mitsuzuka, Mitsunobu Yoshida
  • Patent number: 11646391
    Abstract: A light-emitting element includes: a first conductive semiconductor layer; a plurality of rods disposed on the first conductive semiconductor layer, the rods comprising a first conductive semiconductor; a first insulating film disposed on a surface of the first conductive semiconductor layer while being absent under the rods; a plurality of light-emitting layers disposed on lateral surfaces of the rods; a plurality of second conductive semiconductor layers disposed on outer sides of the light-emitting layers; and a plurality of second insulating films disposed at upper ends of the rods.
    Type: Grant
    Filed: July 1, 2021
    Date of Patent: May 9, 2023
    Assignee: NICHIA CORPORATION
    Inventor: Atsuo Michiue
  • Patent number: 11646306
    Abstract: An apparatus that includes a substrate divided into a plurality of different regions, where the substrate remains physically together. A first device located in a first region of the plurality of different regions, where the first device has a first height. A second device located in a second region of the plurality of different regions. The second device has a second height and the second device is a different device from the first device. A third device located in a third region of the plurality of different regions. The third device has a third height and the third device is a different device from the first device and the second device. The second height is smaller than the first height.
    Type: Grant
    Filed: March 24, 2021
    Date of Patent: May 9, 2023
    Assignee: International Business Machines Corporation
    Inventors: Julien Frougier, Veeraraghavan S. Basker, Andrew Gaul, Ruilong Xie
  • Patent number: 11638895
    Abstract: The filter of a gas sensor comprises an inorganic porous support supporting both an organic sulfonic acid compound including sulfo group (—SO3H) and a Lewis acid having at least a metal element of transitional metal elements, Al element, Ga element, In element, Ge element, and Sn element. The Lewis acid loaded in the inorganic porous support adsorbs low concentration siloxanes. The organic sulfonic acid compound including sulfo group polymerizes adsorbed siloxanes in the filter so as not to desorb from the filter.
    Type: Grant
    Filed: February 19, 2018
    Date of Patent: May 2, 2023
    Assignees: Figaro Engineering Inc., University Public Corporation Osaka
    Inventors: Masato Takeuchi, Junpei Furuno, Tatsuya Tanihira, Kenichi Yoshioka
  • Patent number: 11631671
    Abstract: A method of fabricating a semiconductor device is provided. An initial stack of layers is formed over a substrate. The initial stack alternates between a first material layer and a second material layer that has a different composition from the first material layer. The initial stack is divided into a first stack and a second stack. First GAA transistors are formed in the first stack by using the first material layers as respective channel regions for the first GAA transistors and using the second material layers as respective replacement gates for the first GAA transistors. Second GAA transistors are formed in the second stack by using the second material layers as respective channel regions for the second GAA transistors and using the first material layers as respective replacement gates for the second GAA transistors. The second GAA transistors are vertically offset from the first GAA transistors.
    Type: Grant
    Filed: December 29, 2020
    Date of Patent: April 18, 2023
    Assignee: Tokyo Electron Limited
    Inventors: H. Jim Fulford, Anton J. Devilliers, Mark I. Gardner, Daniel Chanemougame, Jeffrey Smith, Lars Liebmann, Subhadeep Kal
  • Patent number: 11594414
    Abstract: A method of manufacturing a semiconductor nanowire semiconductor device is described. The method includes forming an amorphous channel material layer on a substrate, patterning the channel material layer to form semiconductor nanowires extending in a lateral direction on the substrate, and forming a cover layer covering an upper of the semiconductor nanowire. The cover layer and the nanowire are patterned to form a trench exposing a side section of an one end of the semiconductor nanowire and a catalyst material layer is formed in contact with a side surface of the semiconductor nanowire, and metal induced crystallization (MIC) by heat treatment is performed to crystallize the semiconductor nanowire in a length direction of the nanowire from the one end of the semiconductor nanowire in contact with the catalyst material.
    Type: Grant
    Filed: September 30, 2021
    Date of Patent: February 28, 2023
    Inventor: Ying Hong
  • Patent number: 11575005
    Abstract: An integrated circuit structure includes: a semiconductor nanowire extending in a length direction and including a body portion; a gate dielectric surrounding the body portion; a gate electrode insulated from the body portion by the gate dielectric; a semiconductor source portion adjacent to a first side of the body portion; and a semiconductor drain portion adjacent to a second side of the body portion opposite the first side, the narrowest dimension of the second side of the body portion being smaller than the narrowest dimension of the first side. In an embodiment, the nanowire has a conical tapering. In an embodiment, the gate electrode extends along the body portion in the length direction to the source portion, but not to the drain portion. In an embodiment, the drain portion at the second side of the body portion has a lower dopant concentration than the source portion at the first side.
    Type: Grant
    Filed: March 30, 2018
    Date of Patent: February 7, 2023
    Assignee: Intel Corporation
    Inventors: Seung Hoon Sung, Dipanjan Basu, Ashish Agrawal, Benjamin Chu-Kung, Siddharth Chouksey, Cory C. Bomberger, Tahir Ghani, Anand S. Murthy, Jack T. Kavalieros
  • Patent number: 11545290
    Abstract: A magnetoresistive element comprises a novel iPMA cap layer on a surface of a ferromagnetic recording layer. The iPMA cap layer introduces giant interfacial magnetic anisotropy energies (G-iMAE) on the interface between the recording layer and the iPMA cap layer, yielding a giant interfacial perpendicular magnetic anisotropy (G-iPMA) of the recording layer.
    Type: Grant
    Filed: November 12, 2020
    Date of Patent: January 3, 2023
    Inventors: Yimin Guo, Rongfu Xiao, Jun Chen
  • Patent number: 11513638
    Abstract: A silver nanowire (SNW) protection layer structure includes a substrate; a SNW layer, disposed on the substrate and covering only a partial region of a surface of the substrate, the SNW layer including a plurality of SNW channels; and a SNW protection layer, disposed on the SNW layer and covering a region corresponding to the plurality of SNW channels, the SNW protection layer including a light-resistant antioxidant. A manufacturing method for the SNW protection layer structure above is further provided. The SNW protection layer structure and the manufacturing method thereof are applicable in a touch sensor.
    Type: Grant
    Filed: December 18, 2020
    Date of Patent: November 29, 2022
    Assignee: Cambrios Film Solutions Corporation
    Inventors: Yeh-Sheng Wang, Wei-Chia Fang, Chun-Hung Chu, Chung-Chin Hsiao, Ya-Ting Lin, Shih-Ching Chen
  • Patent number: 11489147
    Abstract: The present disclosure is directed to methods and embedding battery tab attachment structures within composites of electrode active materials and carbon nanotubes, which lack binder and lack collector foils, and the resulting self-standing electrodes. Such methods and the resulting self-standing electrodes may facilitate the use of such composites in battery and power applications.
    Type: Grant
    Filed: May 7, 2021
    Date of Patent: November 1, 2022
    Assignee: HONDA MOTOR CO., LTD.
    Inventors: Avetik Harutyunyan, Oleg Kuznetsov
  • Patent number: 11479872
    Abstract: Fabricating a doped bismuth vanadate electrode includes spray coating a substrate with an aqueous solution with vanadium-containing anions and bismuth-containing cations to yield a coated substrate, heating the coated substrate to form crystalline bismuth vanadate on the substrate, and doping the crystalline bismuth vanadate with lithium ions to yield a doped bismuth vanadate electrode.
    Type: Grant
    Filed: May 8, 2020
    Date of Patent: October 25, 2022
    Assignee: Arizona Board of Regents on behalf of Arizona State University
    Inventors: Umesh Prasad, Jyoti Prakash, Arunachala Kannan
  • Patent number: 11411091
    Abstract: A method for manufacturing a stacked gate-all-around nano-sheet CMOS device, including: providing a substrate with a fin structure, where a channel layer for an NMOS is a sacrificial layer for a PMOS, a channel layer for the PMOS is a sacrificial layer for the NMOS; and mobility of holes in the second material is greater than mobility of holes in the first material; forming a dummy gate stack extending across the fin structure; forming source-or-drain regions in the fin structure at two sides of the dummy gate stack; removing the dummy gate stack and the sacrificial layers covered by the dummy gate stack, to expose a surface of a part of the channel layer that is located between the source-or-drain regions, where a nano-sheet array is formed by the channel layer with the exposed surface; and forming a gate stack structure surrounding each nano sheet in the nano-sheet array.
    Type: Grant
    Filed: October 30, 2019
    Date of Patent: August 9, 2022
    Inventors: Huaxiang Yin, Tianchun Ye, Qingzhu Zhang, Jiaxin Yao
  • Patent number: 11313802
    Abstract: Disclosed is a system for detecting contaminants in a sample fluid. The system has a colloidal dispersion circuit with a reservoir containing a colloidal dispersion with colloidal particles capable of exhibiting localized surface plasmon resonance (“LSPR particles”), a Raman spectrometer/flow cell and a pump for circulating the colloidal dispersion through the colloidal dispersion circuit. A colloidal dispersion level sensor measures the extent of colloidal dispersion in the colloidal dispersion circuit. A permeation valve diverts the colloidal dispersion in the colloidal dispersion circuit through an ultra-filtration membrane with a pore size smaller than the LSPR particles, thus preventing the LSPR particles from passing through. The sample may be introduced into the colloidal dispersion circuit through a fluid sample injection valve. A processor is connected to the Raman spectrometer/flow cell, the pump, the permeation valve, the colloidal dispersion level sensor, and the fluid sample injection port.
    Type: Grant
    Filed: December 17, 2021
    Date of Patent: April 26, 2022
    Assignee: HORIBA INSTRUMENTS, INCORPORATED
    Inventors: Timothy Michael Holt, Michelle N. Sestak
  • Patent number: 11316069
    Abstract: The present invention provides a micro-LED chip, a manufacturing method of the micro-LED chip, and a display panel. The micro-LED chip includes a plurality of sub-chips connected in series. The first sub-chip and the last sub-chip are connected to a first electrode and a second electrode, respectively. Accordingly, a voltage across the micro-LED chip is increased, power consumption of a driving thin film transistor (TFT) is reduced, and a high power consumption problem of driving TFTs in conventional micro-LED displays is improved.
    Type: Grant
    Filed: December 18, 2019
    Date of Patent: April 26, 2022
    Inventor: Yong Fan
  • Patent number: 10947119
    Abstract: Provided are organic metal halide crystals having a 1D nanotube structure. The metal halide crystals may have a unit cell that includes two or more face-sharing metal halide dimers. The metal halide crystals also may include organic cations. Methods of forming metal halide crystals having a 1D nanotube structure also are provided.
    Type: Grant
    Filed: October 9, 2018
    Date of Patent: March 16, 2021
    Assignee: Florida State University Research Foundation, Inc.
    Inventors: Biwu Ma, Haoran Lin
  • Publication number: 20150146452
    Abstract: A quantum rod luminescent display device includes a first substrate having a plurality of pixel regions; a plurality of first electrodes alternately arranged with a plurality of second electrodes in each of the plurality of pixel regions; a plurality of quantum rod compound layers over the first electrodes and the second electrodes, respectively in each of the plurality of pixel regions, each of the quantum rod compound layers including a quantum rod having a core, a shell surrounding the core, and an electron acceptor; a second substrate facing the first substrate; and a backlight unit at an outer surface of the first substrate. The electron acceptor is attached to or adjacent to the quantum rod.
    Type: Application
    Filed: November 24, 2014
    Publication date: May 28, 2015
    Inventors: Kyu-Nam KIM, Jin-Wuk KIM, Byung-Geol KIM, Sung-Woo KIM, Kyung-Kook JANG, Hee-Yeol KIM, Sung-Il WOO
  • Patent number: 9034668
    Abstract: Device for forming, on a nanowire made of a semiconductor, an alloy of this semiconductor with a metal or metalloid by bringing this nanowire into contact with electrically conductive metal or metalloid probes and Joule heating the nanowire at the points of contact with the probes so as to form an alloy such as a silicide. Application to the production of controlled-channel-length metal-silicide transistors.
    Type: Grant
    Filed: July 13, 2011
    Date of Patent: May 19, 2015
    Assignee: COMMISSARIAT À L'ÉNERGIE ATOMIQUE ET AUX ÉNERGIES ALTERNATIVES
    Inventors: Massimo Mongillo, Silvano De Franceschi, Panayotis Spathis
  • Patent number: 9035383
    Abstract: A method of fabricating an electronic device includes the following steps. At least one first set and at least one second set of nanowires and pads are etched in an SOI layer of an SOI wafer. A first gate stack is formed that surrounds at least a portion of each of the first set of nanowires that serves as a channel region of a capacitor device. A second gate stack is formed that surrounds at least a portion of each of the second set of nanowires that serves as a channel region of a FET device. Source and drain regions of the FET device are selectively doped. A first silicide is formed on the source and drain regions of the capacitor device that extends at least to an edge of the first gate stack. A second silicide is formed on the source and drain regions of the FET device.
    Type: Grant
    Filed: August 15, 2013
    Date of Patent: May 19, 2015
    Assignee: International Business Machines Corporation
    Inventors: Sarunya Bangsaruntip, Amlan Majumdar, Jeffrey W. Sleight
  • Publication number: 20150129743
    Abstract: Various examples are provided for pillar array photo detectors. In one example, among others, a photo detection system includes an array of substantially aligned photo sensitive nanorods extending between first and second electrodes, and a plurality of resistance monitoring circuits coupled at different positions about the circumference of the electrodes. In another example, a photo detector includes first and second electrodes, and an array of substantially aligned photo sensitive nanorods extending between the substantially parallel electrodes. Light passing through an electrode excites electrons in the photo sensitive nanorods that are illuminated by the light.
    Type: Application
    Filed: October 30, 2014
    Publication date: May 14, 2015
    Inventors: Jinhui Song, Chengming Jiang
  • Patent number: 9023743
    Abstract: An inorganic fiber structure comprising inorganic nanofibers having an average fiber diameter of 3 ?m or less, in which an entirety including the inside thereof is adhered with an inorganic adhesive, and the porosity thereof is 90% or more, is disclosed.
    Type: Grant
    Filed: January 14, 2010
    Date of Patent: May 5, 2015
    Assignees: Japan Vilene Company, Ltd., Fukuoka Prefectural Government, Kyushu University, National University Corporation
    Inventors: Rie Watanabe, Takashi Tarao, Masaaki Kawabe, Tetsu Yamaguchi, Shinji Sakai, Koei Kawakami
  • Patent number: 9017808
    Abstract: A method of manufacturing a thermal interface material, comprising providing a sheet comprising nano-scale fibers, the sheet having at least one exposed surface; and stabilizing the fibers with a stabilizing material disposed in at least a portion of a void space between the fibers in the sheet. The fibers may be CNT's or metallic nano-wires. Stabilizing may include infiltrating the fibers with a polymerizable material. The polymerizable material may be mixed with nano- or micro-particles. The composite system may include two films, with the fibers in between, to create a sandwich. Each capping film may include two sub films: a palladium film closer to the stabilizing material to improve adhesion; and a nano-particle film for contact with a device to be cooled or a heat sink.
    Type: Grant
    Filed: March 12, 2009
    Date of Patent: April 28, 2015
    Assignee: The Research Foundation for The State University of New York
    Inventors: Hao Wang, Bahgat Sammakia, Yayong Liu, Kaikun Yang
  • Patent number: 9017561
    Abstract: A piezo-resistive MEMS resonator comprising an anchor, a resonator mounted on the anchor, an actuator mounted to apply an electrostatic force on the resonator and a piezo-resistive read-out means comprising a nanowire coupled to the resonator.
    Type: Grant
    Filed: August 28, 2013
    Date of Patent: April 28, 2015
    Assignee: NXP, B.V.
    Inventors: Gerhard Koops, Jozef Thomas Martinus van Beek
  • Patent number: 9018122
    Abstract: The present invention includes a nanostructure, a method of making thereof, and a method of photocatalysis. In one embodiment, the nanostructure includes a crystalline phase and an amorphous phase in contact with the crystalline phase. Each of the crystalline and amorphous phases has at least one dimension on a nanometer scale. In another embodiment, the nanostructure includes a nanoparticle comprising a crystalline phase and an amorphous phase. The amorphous phase is in a selected amount. In another embodiment, the nanostructure includes crystalline titanium dioxide and amorphous titanium dioxide in contact with the crystalline titanium dioxide. Each of the crystalline and amorphous titanium dioxide has at least one dimension on a nanometer scale.
    Type: Grant
    Filed: March 3, 2010
    Date of Patent: April 28, 2015
    Assignee: The Regents of the University of California
    Inventors: Samuel S. Mao, Xiaobo Chen
  • Publication number: 20150109652
    Abstract: The embodiments described herein provide an electrochromic device. In an exemplary embodiment, the electrochromic device includes (1) a substrate and (2) a film supported by the substrate, where the film includes transparent conducting oxide (TCO) nanostructures. In a further embodiment, the electrochromic device further includes (a) an electrolyte, where the nanostructures are embedded in the electrolyte, resulting in an electrolyte, nanostructure mixture positioned above the substrate and (b) a counter electrode positioned above the mixture. In a further embodiment, the electrochromic device further includes a conductive coating deposited on the substrate between the substrate and the mixture. In a further embodiment, the electrochromic device further includes a second substrate positioned above the mixture.
    Type: Application
    Filed: August 21, 2012
    Publication date: April 23, 2015
    Applicant: THE REGENTS OF THE UNIVERSITY OF CALIFORNIA
    Inventors: Delia Milliron, Ravisubhash Tangirala, Anna Llordes, Raffaella Buonsanti, Guillermo Garcia
  • Patent number: 9012887
    Abstract: The present invention relates to growth of III-V semiconductor nanowires (2) on a Si substrate (3). Controlled vertical nanowire growth is achieved by a step, to be taken prior to the growing of the nanowire, of providing group III or group V atoms to a (111) surface of the Si substrate to provide a group III or group V 5 surface termination (4). A nanostructured device including a plurality of aligned III-V semiconductor nanowires (2) grown on, and protruding from, a (111) surface of a Si substrate (3) in an ordered pattern in compliance with a predetermined device layout is also presented.
    Type: Grant
    Filed: October 24, 2011
    Date of Patent: April 21, 2015
    Assignee: Qunano AB
    Inventors: Lars Samuelson, Jonas Ohlsson, Thomas Mårtensson, Patrik Svensson
  • Patent number: 8994108
    Abstract: In one aspect, a method of fabricating an electronic device includes the following steps. An alternating series of device and sacrificial layers are formed in a stack on an SOI wafer. Nanowire bars are etched into the device/sacrificial layers such that each of the device layers in a first portion of the stack and each of the device layers in a second portion of the stack has a source region, a drain region and a plurality of nanowire channels connecting the source region and the drain region. The sacrificial layers are removed from between the nanowire bars. A conformal gate dielectric layer is selectively formed surrounding the nanowire channels in the first portion of the stack which serve as a channel region of a nanomesh FET transistor. Gates are formed surrounding the nanowire channels in the first and second portions of the stack.
    Type: Grant
    Filed: August 21, 2013
    Date of Patent: March 31, 2015
    Assignee: International Business Machines Corporation
    Inventors: Josephine B. Chang, Isaac Lauer, Chung-Hsun Lin, Jeffrey W. Sleight
  • Patent number: 8993991
    Abstract: Provided are semiconductor devices and methods of manufacturing the same. The semiconductor device includes a substrate including a first top surface, a second top surface lower in level than the first top surface, and a first perpendicular surface disposed between the first and second top surfaces, a first source/drain region formed under the first top surface, a first nanowire extended from the first perpendicular surface in one direction and being spaced apart from the second top surface, a second nanowire extended from a side surface of the first nanowire in the one direction, being spaced apart from the second top surface, and including a second source/drain region, a gate electrode on the first nanowire, and a dielectric layer between the first nanowire and the gate electrode.
    Type: Grant
    Filed: July 29, 2011
    Date of Patent: March 31, 2015
    Assignee: Electronics and Telecommunications Research Institute
    Inventors: Dongwoo Suh, Sung Bock Kim, Hojun Ryu
  • Patent number: 8992883
    Abstract: Disclosed are methods for producing ZnO nanostructures, the methods comprising heating an aqueous solution comprising a zinc compound, a base, and a polymer which is polyvinylpyrrolidinone or poly(ethylene glycol).
    Type: Grant
    Filed: June 4, 2010
    Date of Patent: March 31, 2015
    Assignee: Indian Institute of Technology Bombay
    Inventors: Bharati Panigrahy, Mohammed Aslam, Devi Shanker Misra, Dhirendra Bahadur
  • Patent number: 8986999
    Abstract: Methods and apparatuses for encapsulating inorganic micro- or nanostructures within polymeric microgels are described. In various embodiments, viruses are encapsulated with microgels during microgel formation. The viruses can provide a template for in situ synthesis of the inorganic structures within the microgel. The inorganic structures can be distributed substantially homogeneously throughout the microgel, or can be distributed non-uniformly within the microgel. The inventive microgel compositions can be used for a variety of applications including electronic devices, biotechnological devices, fuel cells, display devices and optical devices.
    Type: Grant
    Filed: February 7, 2014
    Date of Patent: March 24, 2015
    Assignees: Massachusetts Institute of Technology, President and Fellows of Harvard University
    Inventors: Yoon Sung Nam, Angela Belcher, Andrew Parsons Magyar, Daeyeon Lee, Jin-Woong Kim, David Weitz
  • Publication number: 20150079716
    Abstract: A light emitting diode includes a substrate, a first-type semiconductor layer, a nanorod layer and a transparent planar layer. The first-type semiconductor layer is disposed over the substrate. The nanorod layer is formed on the first-type semiconductor layer. The nanorod layer includes a plurality of nanorods and each of the nanorods has a quantum well structure and a second-type semiconductor layer. The quantum well structure is in contact with the first-type semiconductor layer, and the second-type semiconductor layer is formed on the quantum well structure. The transparent planar layer is filled between the nanorods. A surface of the second-type semiconductor layer is exposed out of the transparent planar layer.
    Type: Application
    Filed: November 26, 2014
    Publication date: March 19, 2015
    Inventors: Chang-Chin YU, Hsiu-Mu TANG, Mong-Ea LIN
  • Patent number: 8980772
    Abstract: A barrier fabric with a nano-fibrous layer for mechanical retention of organic substances formed by a sandwich structure containing a basic material from unwoven fabric of “spunbond” type with areal weight of 15 to 50 g/m2 to which at least one nano-fibrous layer is arranged, selected from hydrophilic polymer, a hydrophobic polymer, or in the case of double-layer arrangement, a combination of the hydrophilic polymer in one layer and the hydrophobic polymer in the other layer. The nano-fibrous layer is equipped with a protective covering layer, and the individual layers of the sandwich are connected to each other. The nano-fibrous layer has an organic polymer material with areal weight of 0.05 to 0.3 g/m2 and thickness from 90 to 150 nm. The covering layer is selected from an unwoven fabric of “spunbond” type, “meltblown” type, cotton textile and/or a mixture of cotton and polyester.
    Type: Grant
    Filed: August 9, 2013
    Date of Patent: March 17, 2015
    Assignee: Ceska Vcela s.r.o.
    Inventor: Miroslav Kubin
  • Patent number: 8980137
    Abstract: A composite for providing electromagnetic shielding including a plurality of nanotubes; and a plurality of elongate metallic nanostructures.
    Type: Grant
    Filed: August 4, 2011
    Date of Patent: March 17, 2015
    Assignee: Nokia Corporation
    Inventors: Vladimir Alexsandrovich Ermolov, Markku Anttoni Oksanen, Khattiya Chalapat, Gheorghe Sorin Paraoanu
  • Patent number: 8974900
    Abstract: Disclosed is a transparent conductive film that comprises at least one carrier layer disposed on the opposite side of a transparent support from at least one conductive layer, and at least one hardcoat layer disposed on the at least one carrier layer. Such films, which exhibit superior hardness, adhesion, and curl, are useful for electronics applications.
    Type: Grant
    Filed: April 19, 2012
    Date of Patent: March 10, 2015
    Assignee: Carestream Health, Inc.
    Inventors: Karissa L. Eckert, Matthew T. Stebbins
  • Patent number: 8975205
    Abstract: Embodiments of the present disclosure include structures, photocatalytic structures, and photoelectrochemical structures, methods of making these structures, methods of making photocatalysis, methods of splitting H2O, methods of splitting CO2, and the like.
    Type: Grant
    Filed: November 10, 2009
    Date of Patent: March 10, 2015
    Assignee: University of Georgia Research Foundation, Inc.
    Inventors: Wilson Smith, Yiping Zhao
  • Publication number: 20150064891
    Abstract: A method of fabricating stacked nanowire for a transistor gate and a stacked nanowire device are described. The method includes etching a fin as a vertical structure from a substrate and forming two or more pairs of spacers at vertically separated positions of the fin. The method also includes oxidizing to form the nanowires at the vertically separated positions of the fin.
    Type: Application
    Filed: September 4, 2013
    Publication date: March 5, 2015
    Applicant: International Business Machines Corporation
    Inventors: Kangguo Cheng, Bruce B. Doris, Pouya Hashemi, Ali Khakifirooz, Alexander Reznicek
  • Publication number: 20150062465
    Abstract: Disclosed are a touch window and a touch device including the same. The touch window includes first and second areas, wherein the second area is bentable from the first area.
    Type: Application
    Filed: August 26, 2014
    Publication date: March 5, 2015
    Inventor: Jae Hak HER
  • Patent number: 8966730
    Abstract: A method of manufacturing a sensor network is described which includes stretching a silicon substrate over a desired area, and generating a plurality of nodes fabricated on the stretchable silicon substrate. The nodes include at least one of an energy harvesting and storage element, a communication device, a sensing device, and a processor. The nodes are interconnected via interconnecting conductors formed in the substrate.
    Type: Grant
    Filed: April 12, 2011
    Date of Patent: March 3, 2015
    Assignee: The Boeing Company
    Inventors: Michael Alexander Carralero, John Lyle Vian
  • Patent number: 8969145
    Abstract: In one aspect, a method of fabricating a nanowire FET device includes the following steps. A layer of III-V semiconductor material is formed on an SOI layer of an SOI wafer. Fins are etched into the III-V material and SOI layer. One or more dummy gates are formed over a portion of the fins that serves as a channel region of the device. A gap filler material is deposited onto the wafer. The dummy gates are removed selective to the gap filler material, forming trenches in the gap filler material. The SOI layer is removed from portions of the fins within the trenches thereby forming suspended nanowire channels in the channel regions of the device. The trenches are filled with at least one gate material to form one or more replacement gates surrounding the nanowire channels in a gate-all-around configuration.
    Type: Grant
    Filed: January 19, 2013
    Date of Patent: March 3, 2015
    Assignee: International Business Machines Corporation
    Inventors: Josephine B. Chang, Isaac Lauer, Jeffrey W. Sleight, Amlan Majumdar
  • Patent number: 8962137
    Abstract: Disclosed herein are a branched nanowire having parasitic nanowires grown at a surface of the branched nanowire, and a method for fabricating the same. The branched nanowire may be fabricated in a fractal form and seeds of the parasitic nanowires may be formed by thermal energy irradiation and/or a wet-etching process. The branched nanowire may effectively be used in a wide variety of applications such as, for example, sensors, photodetectors, light emitting elements, light receiving elements, and the like.
    Type: Grant
    Filed: March 11, 2009
    Date of Patent: February 24, 2015
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Eun Kyung Lee, Byoung Ryong Choi, Sang Jin Lee
  • Patent number: 8962517
    Abstract: Nanowires useful as heterogeneous catalysts are provided. The nanowire catalysts are useful in a variety of catalytic reactions, for example, the oxidative coupling of methane to C2 hydrocarbons. Related methods for use and manufacture of the same are also disclosed.
    Type: Grant
    Filed: November 29, 2012
    Date of Patent: February 24, 2015
    Assignee: Siluria Technologies, Inc.
    Inventors: Fabio R. Zurcher, Erik C. Scher, Joel M. Cizeron, Wayne P. Schammel, Alex Tkachenko, Joel Gamoras, Dmitry Karshtedt, Greg Nyce, Anja Rumplecker, Jarod McCormick, Anna Merzlyak, Marian Alcid, Daniel Rosenberg, Erik-Jan Ras