Nanowire Or Quantum Wire (axially Elongated Structure Having Two Dimensions Of 100 Nm Or Less) Patents (Class 977/762)
  • Publication number: 20150146452
    Abstract: A quantum rod luminescent display device includes a first substrate having a plurality of pixel regions; a plurality of first electrodes alternately arranged with a plurality of second electrodes in each of the plurality of pixel regions; a plurality of quantum rod compound layers over the first electrodes and the second electrodes, respectively in each of the plurality of pixel regions, each of the quantum rod compound layers including a quantum rod having a core, a shell surrounding the core, and an electron acceptor; a second substrate facing the first substrate; and a backlight unit at an outer surface of the first substrate. The electron acceptor is attached to or adjacent to the quantum rod.
    Type: Application
    Filed: November 24, 2014
    Publication date: May 28, 2015
    Inventors: Kyu-Nam KIM, Jin-Wuk KIM, Byung-Geol KIM, Sung-Woo KIM, Kyung-Kook JANG, Hee-Yeol KIM, Sung-Il WOO
  • Patent number: 9035383
    Abstract: A method of fabricating an electronic device includes the following steps. At least one first set and at least one second set of nanowires and pads are etched in an SOI layer of an SOI wafer. A first gate stack is formed that surrounds at least a portion of each of the first set of nanowires that serves as a channel region of a capacitor device. A second gate stack is formed that surrounds at least a portion of each of the second set of nanowires that serves as a channel region of a FET device. Source and drain regions of the FET device are selectively doped. A first silicide is formed on the source and drain regions of the capacitor device that extends at least to an edge of the first gate stack. A second silicide is formed on the source and drain regions of the FET device.
    Type: Grant
    Filed: August 15, 2013
    Date of Patent: May 19, 2015
    Assignee: International Business Machines Corporation
    Inventors: Sarunya Bangsaruntip, Amlan Majumdar, Jeffrey W. Sleight
  • Patent number: 9034668
    Abstract: Device for forming, on a nanowire made of a semiconductor, an alloy of this semiconductor with a metal or metalloid by bringing this nanowire into contact with electrically conductive metal or metalloid probes and Joule heating the nanowire at the points of contact with the probes so as to form an alloy such as a silicide. Application to the production of controlled-channel-length metal-silicide transistors.
    Type: Grant
    Filed: July 13, 2011
    Date of Patent: May 19, 2015
    Assignee: COMMISSARIAT À L'ÉNERGIE ATOMIQUE ET AUX ÉNERGIES ALTERNATIVES
    Inventors: Massimo Mongillo, Silvano De Franceschi, Panayotis Spathis
  • Publication number: 20150129743
    Abstract: Various examples are provided for pillar array photo detectors. In one example, among others, a photo detection system includes an array of substantially aligned photo sensitive nanorods extending between first and second electrodes, and a plurality of resistance monitoring circuits coupled at different positions about the circumference of the electrodes. In another example, a photo detector includes first and second electrodes, and an array of substantially aligned photo sensitive nanorods extending between the substantially parallel electrodes. Light passing through an electrode excites electrons in the photo sensitive nanorods that are illuminated by the light.
    Type: Application
    Filed: October 30, 2014
    Publication date: May 14, 2015
    Inventors: Jinhui Song, Chengming Jiang
  • Patent number: 9023743
    Abstract: An inorganic fiber structure comprising inorganic nanofibers having an average fiber diameter of 3 ?m or less, in which an entirety including the inside thereof is adhered with an inorganic adhesive, and the porosity thereof is 90% or more, is disclosed.
    Type: Grant
    Filed: January 14, 2010
    Date of Patent: May 5, 2015
    Assignees: Japan Vilene Company, Ltd., Fukuoka Prefectural Government, Kyushu University, National University Corporation
    Inventors: Rie Watanabe, Takashi Tarao, Masaaki Kawabe, Tetsu Yamaguchi, Shinji Sakai, Koei Kawakami
  • Patent number: 9018122
    Abstract: The present invention includes a nanostructure, a method of making thereof, and a method of photocatalysis. In one embodiment, the nanostructure includes a crystalline phase and an amorphous phase in contact with the crystalline phase. Each of the crystalline and amorphous phases has at least one dimension on a nanometer scale. In another embodiment, the nanostructure includes a nanoparticle comprising a crystalline phase and an amorphous phase. The amorphous phase is in a selected amount. In another embodiment, the nanostructure includes crystalline titanium dioxide and amorphous titanium dioxide in contact with the crystalline titanium dioxide. Each of the crystalline and amorphous titanium dioxide has at least one dimension on a nanometer scale.
    Type: Grant
    Filed: March 3, 2010
    Date of Patent: April 28, 2015
    Assignee: The Regents of the University of California
    Inventors: Samuel S. Mao, Xiaobo Chen
  • Patent number: 9017561
    Abstract: A piezo-resistive MEMS resonator comprising an anchor, a resonator mounted on the anchor, an actuator mounted to apply an electrostatic force on the resonator and a piezo-resistive read-out means comprising a nanowire coupled to the resonator.
    Type: Grant
    Filed: August 28, 2013
    Date of Patent: April 28, 2015
    Assignee: NXP, B.V.
    Inventors: Gerhard Koops, Jozef Thomas Martinus van Beek
  • Patent number: 9017808
    Abstract: A method of manufacturing a thermal interface material, comprising providing a sheet comprising nano-scale fibers, the sheet having at least one exposed surface; and stabilizing the fibers with a stabilizing material disposed in at least a portion of a void space between the fibers in the sheet. The fibers may be CNT's or metallic nano-wires. Stabilizing may include infiltrating the fibers with a polymerizable material. The polymerizable material may be mixed with nano- or micro-particles. The composite system may include two films, with the fibers in between, to create a sandwich. Each capping film may include two sub films: a palladium film closer to the stabilizing material to improve adhesion; and a nano-particle film for contact with a device to be cooled or a heat sink.
    Type: Grant
    Filed: March 12, 2009
    Date of Patent: April 28, 2015
    Assignee: The Research Foundation for The State University of New York
    Inventors: Hao Wang, Bahgat Sammakia, Yayong Liu, Kaikun Yang
  • Publication number: 20150109652
    Abstract: The embodiments described herein provide an electrochromic device. In an exemplary embodiment, the electrochromic device includes (1) a substrate and (2) a film supported by the substrate, where the film includes transparent conducting oxide (TCO) nanostructures. In a further embodiment, the electrochromic device further includes (a) an electrolyte, where the nanostructures are embedded in the electrolyte, resulting in an electrolyte, nanostructure mixture positioned above the substrate and (b) a counter electrode positioned above the mixture. In a further embodiment, the electrochromic device further includes a conductive coating deposited on the substrate between the substrate and the mixture. In a further embodiment, the electrochromic device further includes a second substrate positioned above the mixture.
    Type: Application
    Filed: August 21, 2012
    Publication date: April 23, 2015
    Applicant: THE REGENTS OF THE UNIVERSITY OF CALIFORNIA
    Inventors: Delia Milliron, Ravisubhash Tangirala, Anna Llordes, Raffaella Buonsanti, Guillermo Garcia
  • Patent number: 9012887
    Abstract: The present invention relates to growth of III-V semiconductor nanowires (2) on a Si substrate (3). Controlled vertical nanowire growth is achieved by a step, to be taken prior to the growing of the nanowire, of providing group III or group V atoms to a (111) surface of the Si substrate to provide a group III or group V 5 surface termination (4). A nanostructured device including a plurality of aligned III-V semiconductor nanowires (2) grown on, and protruding from, a (111) surface of a Si substrate (3) in an ordered pattern in compliance with a predetermined device layout is also presented.
    Type: Grant
    Filed: October 24, 2011
    Date of Patent: April 21, 2015
    Assignee: Qunano AB
    Inventors: Lars Samuelson, Jonas Ohlsson, Thomas Mårtensson, Patrik Svensson
  • Patent number: 8993991
    Abstract: Provided are semiconductor devices and methods of manufacturing the same. The semiconductor device includes a substrate including a first top surface, a second top surface lower in level than the first top surface, and a first perpendicular surface disposed between the first and second top surfaces, a first source/drain region formed under the first top surface, a first nanowire extended from the first perpendicular surface in one direction and being spaced apart from the second top surface, a second nanowire extended from a side surface of the first nanowire in the one direction, being spaced apart from the second top surface, and including a second source/drain region, a gate electrode on the first nanowire, and a dielectric layer between the first nanowire and the gate electrode.
    Type: Grant
    Filed: July 29, 2011
    Date of Patent: March 31, 2015
    Assignee: Electronics and Telecommunications Research Institute
    Inventors: Dongwoo Suh, Sung Bock Kim, Hojun Ryu
  • Patent number: 8992883
    Abstract: Disclosed are methods for producing ZnO nanostructures, the methods comprising heating an aqueous solution comprising a zinc compound, a base, and a polymer which is polyvinylpyrrolidinone or poly(ethylene glycol).
    Type: Grant
    Filed: June 4, 2010
    Date of Patent: March 31, 2015
    Assignee: Indian Institute of Technology Bombay
    Inventors: Bharati Panigrahy, Mohammed Aslam, Devi Shanker Misra, Dhirendra Bahadur
  • Patent number: 8994108
    Abstract: In one aspect, a method of fabricating an electronic device includes the following steps. An alternating series of device and sacrificial layers are formed in a stack on an SOI wafer. Nanowire bars are etched into the device/sacrificial layers such that each of the device layers in a first portion of the stack and each of the device layers in a second portion of the stack has a source region, a drain region and a plurality of nanowire channels connecting the source region and the drain region. The sacrificial layers are removed from between the nanowire bars. A conformal gate dielectric layer is selectively formed surrounding the nanowire channels in the first portion of the stack which serve as a channel region of a nanomesh FET transistor. Gates are formed surrounding the nanowire channels in the first and second portions of the stack.
    Type: Grant
    Filed: August 21, 2013
    Date of Patent: March 31, 2015
    Assignee: International Business Machines Corporation
    Inventors: Josephine B. Chang, Isaac Lauer, Chung-Hsun Lin, Jeffrey W. Sleight
  • Patent number: 8986999
    Abstract: Methods and apparatuses for encapsulating inorganic micro- or nanostructures within polymeric microgels are described. In various embodiments, viruses are encapsulated with microgels during microgel formation. The viruses can provide a template for in situ synthesis of the inorganic structures within the microgel. The inorganic structures can be distributed substantially homogeneously throughout the microgel, or can be distributed non-uniformly within the microgel. The inventive microgel compositions can be used for a variety of applications including electronic devices, biotechnological devices, fuel cells, display devices and optical devices.
    Type: Grant
    Filed: February 7, 2014
    Date of Patent: March 24, 2015
    Assignees: Massachusetts Institute of Technology, President and Fellows of Harvard University
    Inventors: Yoon Sung Nam, Angela Belcher, Andrew Parsons Magyar, Daeyeon Lee, Jin-Woong Kim, David Weitz
  • Publication number: 20150079716
    Abstract: A light emitting diode includes a substrate, a first-type semiconductor layer, a nanorod layer and a transparent planar layer. The first-type semiconductor layer is disposed over the substrate. The nanorod layer is formed on the first-type semiconductor layer. The nanorod layer includes a plurality of nanorods and each of the nanorods has a quantum well structure and a second-type semiconductor layer. The quantum well structure is in contact with the first-type semiconductor layer, and the second-type semiconductor layer is formed on the quantum well structure. The transparent planar layer is filled between the nanorods. A surface of the second-type semiconductor layer is exposed out of the transparent planar layer.
    Type: Application
    Filed: November 26, 2014
    Publication date: March 19, 2015
    Inventors: Chang-Chin YU, Hsiu-Mu TANG, Mong-Ea LIN
  • Patent number: 8980772
    Abstract: A barrier fabric with a nano-fibrous layer for mechanical retention of organic substances formed by a sandwich structure containing a basic material from unwoven fabric of “spunbond” type with areal weight of 15 to 50 g/m2 to which at least one nano-fibrous layer is arranged, selected from hydrophilic polymer, a hydrophobic polymer, or in the case of double-layer arrangement, a combination of the hydrophilic polymer in one layer and the hydrophobic polymer in the other layer. The nano-fibrous layer is equipped with a protective covering layer, and the individual layers of the sandwich are connected to each other. The nano-fibrous layer has an organic polymer material with areal weight of 0.05 to 0.3 g/m2 and thickness from 90 to 150 nm. The covering layer is selected from an unwoven fabric of “spunbond” type, “meltblown” type, cotton textile and/or a mixture of cotton and polyester.
    Type: Grant
    Filed: August 9, 2013
    Date of Patent: March 17, 2015
    Assignee: Ceska Vcela s.r.o.
    Inventor: Miroslav Kubin
  • Patent number: 8980137
    Abstract: A composite for providing electromagnetic shielding including a plurality of nanotubes; and a plurality of elongate metallic nanostructures.
    Type: Grant
    Filed: August 4, 2011
    Date of Patent: March 17, 2015
    Assignee: Nokia Corporation
    Inventors: Vladimir Alexsandrovich Ermolov, Markku Anttoni Oksanen, Khattiya Chalapat, Gheorghe Sorin Paraoanu
  • Patent number: 8975205
    Abstract: Embodiments of the present disclosure include structures, photocatalytic structures, and photoelectrochemical structures, methods of making these structures, methods of making photocatalysis, methods of splitting H2O, methods of splitting CO2, and the like.
    Type: Grant
    Filed: November 10, 2009
    Date of Patent: March 10, 2015
    Assignee: University of Georgia Research Foundation, Inc.
    Inventors: Wilson Smith, Yiping Zhao
  • Patent number: 8974900
    Abstract: Disclosed is a transparent conductive film that comprises at least one carrier layer disposed on the opposite side of a transparent support from at least one conductive layer, and at least one hardcoat layer disposed on the at least one carrier layer. Such films, which exhibit superior hardness, adhesion, and curl, are useful for electronics applications.
    Type: Grant
    Filed: April 19, 2012
    Date of Patent: March 10, 2015
    Assignee: Carestream Health, Inc.
    Inventors: Karissa L. Eckert, Matthew T. Stebbins
  • Publication number: 20150062465
    Abstract: Disclosed are a touch window and a touch device including the same. The touch window includes first and second areas, wherein the second area is bentable from the first area.
    Type: Application
    Filed: August 26, 2014
    Publication date: March 5, 2015
    Inventor: Jae Hak HER
  • Publication number: 20150064891
    Abstract: A method of fabricating stacked nanowire for a transistor gate and a stacked nanowire device are described. The method includes etching a fin as a vertical structure from a substrate and forming two or more pairs of spacers at vertically separated positions of the fin. The method also includes oxidizing to form the nanowires at the vertically separated positions of the fin.
    Type: Application
    Filed: September 4, 2013
    Publication date: March 5, 2015
    Applicant: International Business Machines Corporation
    Inventors: Kangguo Cheng, Bruce B. Doris, Pouya Hashemi, Ali Khakifirooz, Alexander Reznicek
  • Patent number: 8966730
    Abstract: A method of manufacturing a sensor network is described which includes stretching a silicon substrate over a desired area, and generating a plurality of nodes fabricated on the stretchable silicon substrate. The nodes include at least one of an energy harvesting and storage element, a communication device, a sensing device, and a processor. The nodes are interconnected via interconnecting conductors formed in the substrate.
    Type: Grant
    Filed: April 12, 2011
    Date of Patent: March 3, 2015
    Assignee: The Boeing Company
    Inventors: Michael Alexander Carralero, John Lyle Vian
  • Patent number: 8969145
    Abstract: In one aspect, a method of fabricating a nanowire FET device includes the following steps. A layer of III-V semiconductor material is formed on an SOI layer of an SOI wafer. Fins are etched into the III-V material and SOI layer. One or more dummy gates are formed over a portion of the fins that serves as a channel region of the device. A gap filler material is deposited onto the wafer. The dummy gates are removed selective to the gap filler material, forming trenches in the gap filler material. The SOI layer is removed from portions of the fins within the trenches thereby forming suspended nanowire channels in the channel regions of the device. The trenches are filled with at least one gate material to form one or more replacement gates surrounding the nanowire channels in a gate-all-around configuration.
    Type: Grant
    Filed: January 19, 2013
    Date of Patent: March 3, 2015
    Assignee: International Business Machines Corporation
    Inventors: Josephine B. Chang, Isaac Lauer, Jeffrey W. Sleight, Amlan Majumdar
  • Patent number: 8962517
    Abstract: Nanowires useful as heterogeneous catalysts are provided. The nanowire catalysts are useful in a variety of catalytic reactions, for example, the oxidative coupling of methane to C2 hydrocarbons. Related methods for use and manufacture of the same are also disclosed.
    Type: Grant
    Filed: November 29, 2012
    Date of Patent: February 24, 2015
    Assignee: Siluria Technologies, Inc.
    Inventors: Fabio R. Zurcher, Erik C. Scher, Joel M. Cizeron, Wayne P. Schammel, Alex Tkachenko, Joel Gamoras, Dmitry Karshtedt, Greg Nyce, Anja Rumplecker, Jarod McCormick, Anna Merzlyak, Marian Alcid, Daniel Rosenberg, Erik-Jan Ras
  • Patent number: 8962131
    Abstract: Transparent conductive films comprising silver nanowires dispersed in polyvinyl alcohol or gelatin can be prepared by coating from aqueous solvent using common aqueous solvent coating techniques. These films have good transparency, conductivity, and stability. Coating on a flexible support allows the manufacture of flexible conductive materials.
    Type: Grant
    Filed: March 19, 2010
    Date of Patent: February 24, 2015
    Assignee: Carestream Health Inc.
    Inventors: Choufeng Zou, Karissa Eckert
  • Patent number: 8962137
    Abstract: Disclosed herein are a branched nanowire having parasitic nanowires grown at a surface of the branched nanowire, and a method for fabricating the same. The branched nanowire may be fabricated in a fractal form and seeds of the parasitic nanowires may be formed by thermal energy irradiation and/or a wet-etching process. The branched nanowire may effectively be used in a wide variety of applications such as, for example, sensors, photodetectors, light emitting elements, light receiving elements, and the like.
    Type: Grant
    Filed: March 11, 2009
    Date of Patent: February 24, 2015
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Eun Kyung Lee, Byoung Ryong Choi, Sang Jin Lee
  • Patent number: 8958241
    Abstract: A magnetic memory according to an embodiment includes: a magnetic nanowire; first insulating layers provided on a first surface of the magnetic nanowire, each of the first insulating layers having a first and second end faces, a thickness of the first insulating layer over the first end face being thicker than a thickness of the first insulating layer over the second end face; first electrodes on surfaces of the first insulating layers opposite to the first surface; second insulating layers on the second surface of the magnetic nanowire, each of the second insulating layers having a third and fourth end faces, a thickness of the second insulating layer over the third surface being thicker than a thickness of the second insulating layer over the fourth end face; and second electrodes on surfaces of the second insulating layers.
    Type: Grant
    Filed: September 9, 2013
    Date of Patent: February 17, 2015
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Tsuyoshi Kondo, Hirofumi Morise, Shiho Nakamura, Takuya Shimada, Yoshiaki Fukuzumi, Hideaki Aochi
  • Patent number: 8956637
    Abstract: This invention provides novel nanofiber enhanced surface area substrates and structures comprising such substrates for use in various medical devices, as well as methods and uses for such substrates and medical devices. In one particular embodiment, methods for enhancing cellular functions on a surface of a medical device implant are disclosed which generally comprise providing a medical device implant comprising a plurality of nanofibers (e.g., nanowires) thereon and exposing the medical device implant to cells such as osteoblasts.
    Type: Grant
    Filed: April 28, 2011
    Date of Patent: February 17, 2015
    Assignee: Nanosys, Inc.
    Inventors: Robert S. Dubrow, Lawrence A. Bock, R. Hugh Daniels, Veeral D. Hardev, Chunming Niu, Vijendra Sahi
  • Publication number: 20150043056
    Abstract: A method of generating light is disclosed. The method comprises: directing an optical pulse to a semiconductor optical amplifier being at a temperature above 0° C. The optical pulse is preferably characterized by a wavelength within an emission spectrum of the semiconductor optical amplifier and by a pulse area selected to induce Rabi oscillations in the semiconductor optical amplifier, and to emit light at a frequency of at least 1 THz.
    Type: Application
    Filed: August 7, 2014
    Publication date: February 12, 2015
    Inventors: Amir CAPUA, Gadi Eisenstein
  • Patent number: 8951430
    Abstract: Methods of metal assisted chemical etching III-V semiconductors are provided. The methods can include providing an electrically conductive film pattern disposed on a semiconductor substrate comprising a III-V semiconductor. At least a portion of the III-V semiconductor immediately below the conductive film pattern may be selectively removed by immersing the electrically conductive film pattern and the semiconductor substrate into an etchant solution comprising an acid and an oxidizing agent having an oxidation potential less than an oxidation potential of hydrogen peroxide. Such methods can form high aspect ratio semiconductor nanostructures.
    Type: Grant
    Filed: March 15, 2013
    Date of Patent: February 10, 2015
    Assignee: The Board of Trustees of the University of Illinois
    Inventors: Xiuling Li, Matthew T. Dejarld, Jae Cheol Shin, Winston Chern
  • Patent number: 8952354
    Abstract: A multi junction photovoltaic cell for converting light into electrical energy, comprising a substrate (3) having a surface (31), wherein a region (4) at the surface (31) of the substrate (3) is doped such that a first p-n junction is formed in the substrate (3). The photovoltaic cell has a nanowire (2) that is arranged on the surface (31) of the substrate (3) at a position where the doped region (4) is located in the substrate (3), such that a second p-n junction is formed at the nanowire (2) and in series connection with the first p-n junction.
    Type: Grant
    Filed: April 13, 2010
    Date of Patent: February 10, 2015
    Assignee: Sol Voltaics AB
    Inventor: Jerry M. Olson
  • Publication number: 20150035411
    Abstract: A pressing force sensor that includes a flat membrane piezoelectric element and a support. The flat membrane piezoelectric element includes a piezoelectric sheet having a piezoelectric constant d14. A first electrode is formed on a first main surface of the piezoelectric sheet and a second electrode is formed on a second main surface thereof. Long directions of the first electrode and the second electrode and a uniaxial stretching direction of the piezoelectric sheet form an angle of 45°. An opening portion having an elliptical section is formed on the support. The flat membrane piezoelectric element abuts the opening portion of the support. The support and the flat membrane piezoelectric element are disposed such that the opening portion is included within an area of the second electrode.
    Type: Application
    Filed: October 16, 2014
    Publication date: February 5, 2015
    Inventors: Hideki Kawamura, Masamichi Ando
  • Patent number: 8940628
    Abstract: A method of manufacturing an interconnection of an embodiment includes: forming a via which penetrates an interlayer insulation film on a substrate; forming an underlying film in the via; removing the underlying film on a bottom part of the via; forming a catalyst metal inactivation film on the underlying film; removing the inactivation film on the bottom part of the via; forming a catalyst metal film on the bottom part of the via on which the inactivation film is removed; performing a first plasma treatment and a second plasma treatment using a gas not containing carbon on a member in which the catalyst metal film is formed; forming a graphite layer on the catalyst film after the first and second plasma treatment processes; and causing a growth of a carbon nanotube from the catalyst film on which the graphite layer is formed.
    Type: Grant
    Filed: December 26, 2013
    Date of Patent: January 27, 2015
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Yuichi Yamazaki, Tadashi Sakai
  • Patent number: 8940190
    Abstract: A composite for providing electromagnetic shielding including a plurality of nanotubes; and a plurality of elongate metallic nanostructures.
    Type: Grant
    Filed: August 4, 2011
    Date of Patent: January 27, 2015
    Assignee: Nokia Corporation
    Inventors: Vladimir Alexsandrovich Ermolov, Markku Anttoni Oksanen, Khattiya Chalapat, Gheorghe Sorin Paraoanu
  • Patent number: 8940244
    Abstract: The present invention relates to hierarchical structured nanotubes, to a method for preparing the same and to an application for the same, wherein the nanotubes include a plurality of connecting nanotubes for constituting a three-dimensional multi-dendrite morphology; and the method includes the following steps: (A) providing a polymer template including a plurality of organic nanowires; (B) forming an inorganic layer on the surface of the organic nanowires in the polymer template; and (C) performing a heat treatment on the polymer template having the inorganic layer on the surface so that partial atoms of the organic nanowires enter the inorganic layer.
    Type: Grant
    Filed: December 17, 2012
    Date of Patent: January 27, 2015
    Assignee: National Tsing Hua University
    Inventors: Hsueh-Shih Chen, Po-Hsun Chen, Jeng Liang Kuo, Tsong-Pyng Perng
  • Patent number: 8937297
    Abstract: Optoelectronic device including light-emitting means in the form of nanowires (2, 3) having a core/shell-type structure and produced on a substrate (11), in which said nanowires comprise an active zone (22, 32) including at least two types of quantum wells associated with different emission wavelengths and distributed among at least two different regions (220, 221; 320, 321) of said active zone, in which the device also includes a first electrical contact zone (15) on the substrate and a second electrical contact zone (16) on the emitting means, in which said second zone is arranged so that, as the emitting means are distributed according to at least two groups, the electrical contact is achieved for each of said at least two groups at a different region of the active zone, and the electrical power supply is controlled so as to obtain the emission of a multi-wavelength light.
    Type: Grant
    Filed: December 3, 2012
    Date of Patent: January 20, 2015
    Assignee: Commissariat a l'Energie Atomique et aux Energies Alternatives
    Inventors: Philippe Gilet, Ann-Laure Bavencove
  • Patent number: 8937294
    Abstract: Disclosed herein is a semiconducting nanoparticle comprising a one-dimensional semiconducting nanoparticle having a first end and a second end; where the second end is opposed to the first end; and two first endcaps, one of which contacts the first end and the other of which contacts the second end respectively of the one-dimensional semiconducting nanoparticle; where the first endcap that contacts the first end comprises a first semiconductor and where the first endcap extends from the first end of the one-dimensional semiconducting nanoparticle to form a first nanocrystal heterojunction; where the first endcap that contacts the second end comprises a second semiconductor; where the first endcap extends from the second end of the one-dimensional semiconducting nanoparticle to form a second nanocrystal heterojunction; and where the first semiconductor and the second semiconductor are chemically different from each other.
    Type: Grant
    Filed: March 15, 2013
    Date of Patent: January 20, 2015
    Inventors: Moonsub Shim, Nuri Oh, You Zhai, Sooji Nam, Peter Trefonas, Kishori Deshpande, Jake Joo
  • Patent number: 8934289
    Abstract: A mechanism is provided for storing multiple bits in a domain wall nanowire magnetic junction device. The multiple bits are encoded based on a resistance of the domain wall nanowire magnetic junction device using a single domain wall. The single domain wall is shifted to change the resistance of the domain wall nanowire magnetic junction device to encode a selected bit. The resistance is checked to ensure that it corresponds to a preselected resistance for the selected bit. Responsive to the resistance corresponding to the preselected resistance for the selected bit, he selected bit is stored. Responsive to the resistance not being the preselected resistance for the selected bit, the single domain wall is shifted until the resistance corresponds to the preselected resistance.
    Type: Grant
    Filed: November 30, 2012
    Date of Patent: January 13, 2015
    Assignee: International Business Machines Corporation
    Inventors: Anthony J. Annunziata, Michael C. Gaidis, William Gallagher, Luc Thomas
  • Patent number: 8932940
    Abstract: Embodiments of the invention provide a method for direct heteroepitaxial growth of vertical III-V semiconductor nanowires on a silicon substrate. The silicon substrate is etched to substantially completely remove native oxide. It is promptly placed in a reaction chamber. The substrate is heated and maintained at a growth temperature. Group III-V precursors are flowed for a growth time. Preferred embodiment vertical Group III-V nanowires on silicon have a core-shell structure, which provides a radial homojunction or heterojunction. A doped nanowire core is surrounded by a shell with complementary doping. Such can provide high optical absorption due to the long optical path in the axial direction of the vertical nanowires, while reducing considerably the distance over which carriers must diffuse before being collected in the radial direction. Alloy composition can also be varied. Radial and axial homojunctions and heterojunctions can be realized. Embodiments provide for flexible Group III-V nanowire structures.
    Type: Grant
    Filed: October 28, 2009
    Date of Patent: January 13, 2015
    Assignee: The Regents of the University of California
    Inventors: Deli Wang, Cesare Soci, Xinyu Bao, Wei Wei, Yi Jing, Ke Sun
  • Patent number: 8927968
    Abstract: A method of forming a semiconductor device is provided. The method includes providing a structure including, a handle substrate, a buried boron nitride layer located above an uppermost surface of the handle substrate, a buried oxide layer located on an uppermost surface of the buried boron nitride layer, and a top semiconductor layer located on an uppermost surface of the buried oxide layer. Next, a first semiconductor pad, a second semiconductor pad and a plurality of semiconductor nanowires connecting the first semiconductor pad and the second semiconductor pad in a ladder-like configuration are patterned into the top semiconductor layer. The semiconductor nanowires are suspended by removing a portion of the buried oxide layer from beneath each semiconductor nanowire, wherein a portion of the uppermost surface of the buried boron nitride layer is exposed. Next, a gate all-around field effect transistor is formed.
    Type: Grant
    Filed: August 26, 2013
    Date of Patent: January 6, 2015
    Assignee: International Business Machines Corporation
    Inventors: Guy Cohen, Michael A. Guillorn, Alfred Grill, Leathen Shi
  • Patent number: 8927397
    Abstract: A method of fabricating an electronic device includes the following steps. A SOI wafer is provided having a SOI layer over a BOX. At least one first/second set of nanowires and pads are patterned in the SOI layer. A conformal gate dielectric layer is selectively formed surrounding a portion of each of the first set of nanowires that serves as a channel region of a transistor device. A first metal gate stack is formed on the conformal gate dielectric layer surrounding the portion of each of the first set of nanowires that serves as the channel region of the transistor device in a gate all around configuration. A second metal gate stack is formed surrounding a portion of each of the second set of nanowires that serves as a channel region of a diode device in a gate all around configuration.
    Type: Grant
    Filed: February 7, 2013
    Date of Patent: January 6, 2015
    Assignee: International Business Machines Corporation
    Inventors: Josephine B. Chang, Isaac Lauer, Chung-Hsun Lin, Jeffrey W. Sleight
  • Patent number: 8927405
    Abstract: A method of forming a semiconductor device is provided. The method includes providing a structure including, a handle substrate, a buried boron nitride layer located above an uppermost surface of the handle substrate, a buried oxide layer located on an uppermost surface of the buried boron nitride layer, and a top semiconductor layer located on an uppermost surface of the buried oxide layer. Next, a first semiconductor pad, a second semiconductor pad and a plurality of semiconductor nanowires connecting the first semiconductor pad and the second semiconductor pad in a ladder-like configuration are patterned into the top semiconductor layer. The semiconductor nanowires are suspended by removing a portion of the buried oxide layer from beneath each semiconductor nanowire, wherein a portion of the uppermost surface of the buried boron nitride layer is exposed. Next, a gate all-around field effect transistor is formed.
    Type: Grant
    Filed: December 18, 2012
    Date of Patent: January 6, 2015
    Assignee: International Business Machines Corporation
    Inventors: Guy Cohen, Michael A. Guillorn, Alfred Grill, Leathen Shi
  • Patent number: 8923039
    Abstract: A mechanism is provided for storing multiple bits in a domain wall nanowire magnetic junction device. The multiple bits are encoded based on a resistance of the domain wall nanowire magnetic junction device using a single domain wall. The single domain wall is shifted to change the resistance of the domain wall nanowire magnetic junction device to encode a selected bit. The resistance is checked to ensure that it corresponds to a preselected resistance for the selected bit. Responsive to the resistance corresponding to the preselected resistance for the selected bit, the selected bit is stored. Responsive to the resistance not being the preselected resistance for the selected bit, the single domain wall is shifted until the resistance corresponds to the preselected resistance.
    Type: Grant
    Filed: November 6, 2012
    Date of Patent: December 30, 2014
    Assignee: International Business Machines Corporation
    Inventors: Anthony J. Annunziata, Michael C. Gaidis, William Gallagher, Luc Thomas
  • Publication number: 20140370326
    Abstract: A method for forming porous metal structures and the resulting structure may include forming a metal structure above a substrate. A masking layer may be formed above the metal structure, and then etched using a reactive ion etching process with a mask etchant and a metal etchant. Etching the masking layer may result in the formation of a plurality of pores in the metal structure. In some embodiments, the metal structure may include a first end region, a second end region, and an intermediate region. Before etching the masking layer, a protective layer may be formed above the first end region and the second end region, so that the plurality of pores is contained within the intermediate region. In some embodiments, the intermediate metal region may be a nanostructure such as a nanowire.
    Type: Application
    Filed: June 18, 2013
    Publication date: December 18, 2014
    Inventors: Yann Astier, Jingwei Bai, Robert L. Bruce, Aaron D. Franklin, Joshua T. Smith
  • Patent number: 8906733
    Abstract: A method for creating a nanostructure according to one embodiment includes depositing material in a template for forming an array of nanocables; removing only a portion of the template such that the template forms an insulating layer between the nanocables; and forming at least one layer over the nanocables. A nanostructure according to one embodiment includes a nanocable having a roughened outer surface and a solid core. A nanostructure according to one embodiment includes an array of nanocables each having a roughened outer surface and a solid core, the roughened outer surface including reflective cavities; and at least one layer formed over the roughened outer surfaces of the nanocables, the at least one layer creating a photovoltaically active p-n junction. Additional systems and methods are also presented.
    Type: Grant
    Filed: October 25, 2010
    Date of Patent: December 9, 2014
    Assignees: Q1 Nanosystems, Inc., The Regents Of The University Of California
    Inventors: Ruxandra Vidu, Brian Argo, John Argo, Pieter Stroeve, Saif Islam, Jie-Ren Ku, Michael Chen
  • Publication number: 20140352144
    Abstract: Claimed methods reduce leakage currents in transparent conductive films comprising conductive nanostructures without substantially impairing the films' optical properties or physical integrity. Imposition of electrical stimuli to separate conductive regions leads to reduced conductivity of the intervening lesser conductive regions.
    Type: Application
    Filed: May 8, 2014
    Publication date: December 4, 2014
    Applicant: Carestream Health, Inc.
    Inventors: Robert J. Monson, Andrew T. Fried, Eric L. Granstrom
  • Patent number: 8901655
    Abstract: A method of fabricating an electronic device includes the following steps. A SOI wafer is provided having a SOI layer over a BOX. At least one first/second set of nanowires and pads are patterned in the SOI layer. A conformal gate dielectric layer is selectively formed surrounding a portion of each of the first set of nanowires that serves as a channel region of a transistor device. A first metal gate stack is formed on the conformal gate dielectric layer surrounding the portion of each of the first set of nanowires that serves as the channel region of the transistor device in a gate all around configuration. A second metal gate stack is formed surrounding a portion of each of the second set of nanowires that serves as a channel region of a diode device in a gate all around configuration.
    Type: Grant
    Filed: August 19, 2013
    Date of Patent: December 2, 2014
    Assignee: International Business Machines Corporation
    Inventors: Josephine B. Chang, Isaac Lauer, Chung-Hsun Lin, Jeffrey W. Sleight
  • Patent number: 8900029
    Abstract: The present application relates to a method for making a carbon nanotube field emitter. A carbon nanotube film is drawn from the carbon nanotube array by a drawing tool. The carbon nanotube film includes a triangle region. A portion of the carbon nanotube film closed to the drawing tool is treated into a carbon nanotube wire including a vertex of the triangle region. The triangle region is cut from the carbon nanotube film by a laser beam along a cutting line. A distance between the vertex of the triangle region and the cutting line can be in a range from about 10 microns to about 5 millimeters.
    Type: Grant
    Filed: October 22, 2012
    Date of Patent: December 2, 2014
    Assignees: Tsinghua University, Hon Hai Precision Industry Co., Ltd.
    Inventors: Peng Liu, Shou-Shan Fan
  • Patent number: 8900935
    Abstract: In one exemplary embodiment, a method includes: providing a semiconductor device having a substrate, a nanowire, a first structure and a second structure, where the nanowire is suspended between the first structure and the second structure, where the first structure and the second structure overly the substrate; and performing atomic layer deposition to deposit a film on at least a portion of the semiconductor device, where performing atomic layer deposition to deposit the film includes performing atomic layer deposition to deposit the film on at least a surface of the nanowire.
    Type: Grant
    Filed: January 25, 2011
    Date of Patent: December 2, 2014
    Assignee: International Business Machines Corporation
    Inventors: Dechao Guo, Zhengwen Li, Kejia Wang, Zhen Zhang, Yu Zhu
  • Patent number: 8901534
    Abstract: A semiconductor device, such as an LED, includes a plurality of first conductivity type semiconductor nanowire cores located over a support, a continuous second conductivity type semiconductor layer extending over and around the cores, a plurality of interstitial voids located in the second conductivity type semiconductor layer and extending between the cores, and first electrode layer that contacts the second conductivity type semiconductor layer and extends into the interstitial voids.
    Type: Grant
    Filed: December 5, 2012
    Date of Patent: December 2, 2014
    Assignee: GLO AB
    Inventor: Patrik Svensson