With Specified Cross-sectional Profile (e.g., Belt-shaped, Etc.) Patents (Class 977/765)
  • Patent number: 8932940
    Abstract: Embodiments of the invention provide a method for direct heteroepitaxial growth of vertical III-V semiconductor nanowires on a silicon substrate. The silicon substrate is etched to substantially completely remove native oxide. It is promptly placed in a reaction chamber. The substrate is heated and maintained at a growth temperature. Group III-V precursors are flowed for a growth time. Preferred embodiment vertical Group III-V nanowires on silicon have a core-shell structure, which provides a radial homojunction or heterojunction. A doped nanowire core is surrounded by a shell with complementary doping. Such can provide high optical absorption due to the long optical path in the axial direction of the vertical nanowires, while reducing considerably the distance over which carriers must diffuse before being collected in the radial direction. Alloy composition can also be varied. Radial and axial homojunctions and heterojunctions can be realized. Embodiments provide for flexible Group III-V nanowire structures.
    Type: Grant
    Filed: October 28, 2009
    Date of Patent: January 13, 2015
    Assignee: The Regents of the University of California
    Inventors: Deli Wang, Cesare Soci, Xinyu Bao, Wei Wei, Yi Jing, Ke Sun
  • Publication number: 20140014169
    Abstract: Semiconductor nanostrings, mats containing semiconductor nanostrings, and devices and modules, such as, solar energy generating modules, including semiconductor nanostrings or mats containing semiconductor nanostrings are described herein. Methods for making multi-layer nanostrings and mats and other devices including multi-layer nanostrings are also described.
    Type: Application
    Filed: July 15, 2013
    Publication date: January 16, 2014
    Inventors: James A. RAND, Scott MORRISON, John BLUM
  • Patent number: 8569900
    Abstract: A nanowire device includes a nanowire having differently functionalized segments. Each of the segments is configured to interact with a species to modulate the conductance of a segment. The nanowire is grown from a single catalyst and the segments include a first segment at a non-linear angle from a second segment.
    Type: Grant
    Filed: July 20, 2009
    Date of Patent: October 29, 2013
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventors: Nathaniel J. Quitoriano, Theodore I. Kamins, Hans S. Cho
  • Patent number: 8564031
    Abstract: The invention provides a high voltage-resistant lateral double-diffused transistor. The lateral double-diffused MOS transistor includes a channel region, a gate dielectric, a gate region, a source region, a drain region, a source end extension region and a drain end S-shaped drifting region, wherein the channel region has a lateral cylindrical silicon nanowire structure, on which a layer of gate dielectric is uniformly covered, the gate region is on the gate dielectric, the gate region and the gate dielectric completely surround the channel region, the source end extension region lies between the source region and the channel region, the drain end S-shaped drifting region lies between the drain region and the channel region, the plan view of the drain end S-shaped drifting region is in the form of single or multiple S-shaped structure(s), and an insulating material with a relative dielectric constant of 1-4 is filled within the S-shaped structure(s).
    Type: Grant
    Filed: April 1, 2011
    Date of Patent: October 22, 2013
    Assignee: Peking University
    Inventors: Ru Huang, Jibin Zou, Runsheng Wang, Gengyu Yang, Yujie Ai, Jiewen Fan
  • Patent number: 8450724
    Abstract: A device is provided by use of a helical substituted polyacetylene. The device comprises a structure comprised of a helical substituted polyacetylene having a helical main chain, and a pair of electrodes for applying a voltage or electric current to the structure, wherein the molecule of the helical substituted polyacetylene has a length larger than the distance between the pair of the electrodes.
    Type: Grant
    Filed: September 21, 2007
    Date of Patent: May 28, 2013
    Assignee: Canon Kabushiki Kaisha
    Inventors: Takeyuki Sone, Akira Kuriyama, Koji Yano, Otto Albrecht, Masayoshi Tabata
  • Publication number: 20130125912
    Abstract: A nanofiber 10 made of a water soluble polymer, having a cavity 13, and containing an oily component 14 in the cavity 13. The nanofiber 10 preferably has a small-diametered portion 12 and a large-diametered portion 11. The cavity 13 is preferably in the large-diametered portion 11. The cavity 13 is also preferably in both the large-diametered portion 11 and the small-diametered portion 12, with the cavity 13 in the large-diametered portion 11 and the cavity 13 in the small-diametered portion 12 being interconnected.
    Type: Application
    Filed: June 28, 2011
    Publication date: May 23, 2013
    Applicant: KAO CORPORATION
    Inventors: Takehiko Tojo, Yoshimi Yamashita, Masataka Ishikawa, Mika Shuin, Shinnosuke Uno
  • Patent number: 8367435
    Abstract: In exemplary implementations of this invention, hydrothermal synthesis of zinc oxide nanowires is morphologically controlled. Metal complex ions are used to suppress growth in a face-selective manner, by electrostatic crystal growth inhibition. This permits the aspect ratio (height/diameter) of the nanowires to be dynamically tuned over a wide range, from needle-like nanowires that are efficient field emitters to flattened nanowires with a platelet-like shape. The nanowire synthesis is all inorganic and occurs at low temperatures (e.g., <=60° C.). The growth inhibition may be predictively modeled, using speciation plots and treating non-zinc complex ions as ligands. Microfluidic channels may be used for the synthesis, with different solutions flowing down different channels, permitting nanowires with different properties to be synthesized in parallel.
    Type: Grant
    Filed: December 3, 2010
    Date of Patent: February 5, 2013
    Assignee: Massachusetts Institute of Technology
    Inventors: Brian Yichiun Chow, Jaebum Joo, Manu Prakash
  • Patent number: 8330090
    Abstract: A photosensitive device (100), the photosensitive device (100) comprising a substrate (101) and a plurality of vertically aligned nanowire diodes (102 to 105) provided on and/or in the substrate (101).
    Type: Grant
    Filed: April 29, 2008
    Date of Patent: December 11, 2012
    Assignee: NXP, B.V.
    Inventor: Prabhat Agarwal
  • Publication number: 20120202345
    Abstract: Techniques for silicide, germanide or germanosilicide formation in extremely small structures are provided. In one aspect, a method for forming a silicide, germanide or germanosilicide in a three-dimensional silicon, germanium or silicon germanium structure having extremely small dimensions is provided. The method includes the following steps. At least one element is implanted into the structure. At least one metal is deposited onto the structure. The structure is annealed to intersperse the metal within the silicon, germanium or silicon germanium to form the silicide, germanide or germanosilicide wherein the implanted element serves to prevent morphological degradation of the silicide, germanide or germanosilicide. The implanted element can include at least one of carbon, fluorine and silicon.
    Type: Application
    Filed: February 7, 2011
    Publication date: August 9, 2012
    Applicant: International Business Machines Corporation
    Inventors: Benjamin Luke Fletcher, Christian Lavoie, Siegfried Lutz Maurer, Zhen Zhang
  • Patent number: 8206505
    Abstract: The inventive method for forming nano-dimensional clusters consists in introducing a solution containing a cluster-forming material into nano-pores of natural or artificial origin contained in a substrate material and in subsequently exposing said solution to a laser radiation pulse in such a way that a low-temperature plasma producing a gaseous medium in the domain of the existence thereof, wherein a cluster material is returned to a pure material by the crystallization thereof on a liquid substrate while the plasma is cooling, occurs, thereby forming mono-crystal quantum dots spliced with the substrate material. Said method makes it possible to form two- or three-dimensional cluster lattices and clusters spliced with each other from different materials. The invention also makes it possible to produce wires from different materials in the substrate nano-cavities and the quantum dots from the solution micro-drops distributed through an organic material applied to a glass.
    Type: Grant
    Filed: November 29, 2005
    Date of Patent: June 26, 2012
    Inventors: Sergei Nikolaevich Maximovsky, Grigory Avramovich Radutsky
  • Publication number: 20120104335
    Abstract: The present invention provides phthalocyanine nanowires having a minor diameter of 100 nm or less and a ratio (length/minor diameter) of length to minor diameter of 10 or more, an ink composition characterized by containing, as essential components, the phthalocyanine nanowires and an organic solvent, a film including the phthalocyanine nanowires, and an electronic element including a film. Since by using an ink composition containing the phthalocyanine nanowires of the present invention a phthalocyanine film can be formed by a wet process such as coating or printing, a break-proof, lightweight, low-cost electronic element can be provided on a flexible plastic substrate.
    Type: Application
    Filed: April 13, 2010
    Publication date: May 3, 2012
    Applicant: DIC CORPORATION
    Inventors: Hideki Etori, Hideyuki Murata, Norimasa Fukazawa, Shou Inagaki, Hiroshi Isozumi, Masanori Kasai
  • Patent number: 8149485
    Abstract: Dynamically reconfigurable holograms with electronically erasable programmable intermediate layers are disclosed. An example apparatus includes first nanowires, each of the first nanowires having protuberances along a length thereof. The example apparatus also includes second nanowires arranged approximately perpendicular to the first nanowires, the protuberances of the first nanowires being approximately parallel to corresponding ones of the second nanowires. In addition, a layer is disposed between the first and second nanowires. The layer is to control refractive indices at nanowire intersections at intersecting ones of the first and second nanowires.
    Type: Grant
    Filed: December 29, 2008
    Date of Patent: April 3, 2012
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventors: Jingjing Li, Philip J. Kuekes, Shih-Yuan Wang
  • Patent number: 8124227
    Abstract: The object of the present invention is carbon nanofibers mainly characterized by their high specific volume of mesopores, their high gas adsorption capacity and presenting a graphitic hollow structure. A second object of this invention is a procedure for obtaining such carbon nanofibers, which makes use of a metallic nickel catalyst and specific process furnace parameters that combined with the chemical composition of the furnace atmosphere and the fluidodynamic conditions of the gas stream inside the furnace, result in a faster growth of the carbon nanofibers and also in a higher quality of the carbon nanofibers obtained.
    Type: Grant
    Filed: May 9, 2008
    Date of Patent: February 28, 2012
    Assignee: Grupo Antolin-Ingenieria, S.A.
    Inventors: José Luis Gonzalez Moral, José Vera Agulló, César Merino Sánchez, Ignacio Martín Gullón
  • Patent number: 8101976
    Abstract: A memory system having electromechanical memory cells and decoders is disclosed. A decoder circuit selects at least one of the memory cells of an array of such cells. Each cell in the array is a crossbar junction at least one element of which is a nanotube or a nanotube ribbon. The decoder circuit is constructed of crossbar junctions at least one element of each junction being a nanotube or a nanotube ribbon.
    Type: Grant
    Filed: September 11, 2007
    Date of Patent: January 24, 2012
    Assignee: Nantero Inc.
    Inventors: Brent M. Segal, Darren K. Brock, Thomas Rueckes
  • Publication number: 20110309233
    Abstract: Methods, apparatuses, systems, and devices relating to fabricating one or more nanowires are disclosed. One method for fabricating a nanowire includes: selecting a particular wavelength of electromagnetic radiation for absorption for a nanowire; determining a diameter corresponding to the particular wavelength; and fabricating a nanowire having the determined diameter. According to another embodiment, one or more nanowires may be fabricated in an array, each having the same or different determined diameters. An image sensor and method of imaging using such an array are also disclosed.
    Type: Application
    Filed: December 13, 2010
    Publication date: December 22, 2011
    Applicants: PRESIDENT AND FELLOWS OF HARVARD COLLEGE, ZENA TECHNOLOGIES, INC.
    Inventors: Kwanyong SEO, Paul Steinvurzel, Ethan Schonbrun, Munib Wober, Kenneth B. Crozier
  • Patent number: 8034315
    Abstract: Some embodiments include devices that contain bundles of CNTs. An undulating topography extends over the CNTs and within spaces between the CNTs. A global maximum lateral width is defined as the greatest lateral width of any of the spaces. A material is directly over the CNTs, with the material being a plurality of particles that have minimum cross-sectional equatorial widths exceeding the global maximum lateral width. Some embodiments include methods in which a plurality of crossed carbon nanotubes are formed over a semiconductor substrate. The CNTs form an undulating upper topography extending across the CNTs and within spaces between the CNTs. A global maximum lateral width is defined as the greatest lateral width of any of the spaces. A material is deposited over the CNTs, with the material being deposited as particles that have minimum cross-sectional equatorial widths exceeding the global maximum lateral width.
    Type: Grant
    Filed: September 22, 2008
    Date of Patent: October 11, 2011
    Assignee: Micron Technology, Inc.
    Inventors: Nishant Sinha, Gurtej S. Sandhu, Eugene Marsh, Neil Greeley, John Smythe
  • Patent number: 7932543
    Abstract: Provided are a wire structure and a semiconductor device having the wire structure. The wire structure includes a first wire that has a first region having a width of several to tens of nanometers and a second region having a width wider than that of the first region.
    Type: Grant
    Filed: December 27, 2007
    Date of Patent: April 26, 2011
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Sang-jun Choi, Jung-hyun Lee, Hyung-jin Bae, Chang-soo Lee
  • Publication number: 20100261013
    Abstract: The present invention is directed to methods to harvest, integrate and exploit nanomaterials, and particularly elongated nanowire materials. The invention provides methods for harvesting nanowires that include selectively etching a sacrificial layer placed on a nanowire growth substrate to remove nanowires. The invention also provides methods for integrating nanowires into electronic devices that include placing an outer surface of a cylinder in contact with a fluid suspension of nanowires and rolling the nanowire coated cylinder to deposit nanowires onto a surface. Methods are also provided to deposit nanowires using an ink-jet printer or an aperture to align nanowires. Additional aspects of the invention provide methods for preventing gate shorts in nanowire based transistors. Additional methods for harvesting and integrating nanowires are provided.
    Type: Application
    Filed: June 22, 2010
    Publication date: October 14, 2010
    Applicant: NANOSYS, INC.
    Inventors: Xiangfeng Duan, Chunming Niu, Stephen A. Empedocles, David P. Stumbo
  • Publication number: 20100253997
    Abstract: Various embodiments of the present invention are directed to dynamically and electronically reconfigurable optical devices that can be operated as a lens or prism for incident beams of electromagnetic radiation. The optical devices include a phase-modulation layer (1501) disposed between first and second nanowire layers (1502,1503). Overlapping nanowires can be electronically addressed to implement a selected effective refractive index pattern of one or more regions (1510) of the phase-modulation layer, such that each region refracts a portion of an incident beam of electromagnetic radiation having a wavelength of interest in order to focus, diverge, or bend the incident beam.
    Type: Application
    Filed: April 2, 2009
    Publication date: October 7, 2010
    Inventor: Jingjing Li
  • Patent number: 7781778
    Abstract: There are provided a semiconductor light emitting device using a phosphor film formed on a nanowire structure and a method of manufacturing the device, the device including: a substrate; a light emitting structure including a first conductivity type semiconductor layer, an active layer and a second conductivity type semiconductor layer sequentially formed on the substrate; a plurality of nanowire structures formed on the light emitting structure and formed of a transparent material; and a phosphor film formed on at least an upper surface and a side surface of each of the plurality of nanowire structures.
    Type: Grant
    Filed: September 5, 2007
    Date of Patent: August 24, 2010
    Inventors: Won Ha Moon, Chang Hwan Choi, Young Nam Hwang, Hyun Jun Kim
  • Patent number: 7719678
    Abstract: Various aspects of the present invention are directed to a nanowire configured to couple electromagnetic radiation to a selected guided wave and devices incorporating such nanowires. In one aspect of the present invention, a nanowire structure includes a substrate and at least one nanowire attached to the substrate. A diameter, composition, or both may vary generally periodically along a length of the at least one nanowire. A coating may cover at least part of a circumferential surface of the at least one nanowire. The nanowire structure may be incorporated in a device including at least one optical-to-electrical converter operable to convert a guided wave propagating along the length of the at least one nanowire, at least in part responsive to irradiation, to an electrical signal. Other aspects of the present invention are directed to methods of fabricating nanowires structured to support guided waves.
    Type: Grant
    Filed: April 25, 2007
    Date of Patent: May 18, 2010
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventors: Theodore I. Kamins, Alexandre M. Bratkovski
  • Patent number: 7663202
    Abstract: Nanowire-based photodiodes are disclosed. The photodiodes include a first optical waveguide having a tapered first end, a second optical waveguide having a tapered second end, and at least one nanowire comprising at least one semiconductor material connecting the first and second ends in a bridging configuration. Methods of making the photodiodes are also disclosed.
    Type: Grant
    Filed: June 26, 2007
    Date of Patent: February 16, 2010
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventors: Shih-Yuan Wang, Michael Renne Ty Tan, Alexandre M. Bratkovski, R. Stanley Williams, Nobuhiko Kobayashi
  • Patent number: 7652418
    Abstract: An electron emission device which can uniformly emit electrons and can be simply manufactured at a reduced cost, and a display apparatus having improved uniform brightness of pixels by using the electron emission device. In addition, a simple method of manufacturing the electron emission device. The electron emission device includes: a first substrate; a cathode electrode and an electron emission unit disposed on the first substrate; a gate electrode electrically insulated from the cathode electrode; an insulating layer disposed between the cathode electrode and the gate electrode to insulate the cathode electrode from the gate electrode; and an electron emission source including carbon nanotubes (CNTs) that contact the cathode electrode, wherein distances between the gate electrode and the tips of the CNTs are uniform.
    Type: Grant
    Filed: October 26, 2006
    Date of Patent: January 26, 2010
    Assignee: Samsung SDI Co., Ltd.
    Inventors: Young-Chul Choi, Jong-Hwan Park
  • Publication number: 20100006751
    Abstract: A novel, compact non-radioactive electron emitter is provided with a cylindrical shape and with an interior space (6), which forms a vacuum chamber. A substrate (7) forms the bottom of the arrangement with a plurality of field emitter tips (5) formed of carbon nanotubes in the interior space (6). The tips are fastened to the substrate. A layer structure forms the cover of the arrangement, having, from the outside towards the interior space (6), an electrode layer (13), which acts as a counterelectrode and is applied to a gas-impermeable and electron-permeable membrane (10). A substrate (11), which is left open in the form of a window (12) in the area above the field emitter tips (6), acts as a carrier substrate for the membrane (10) and the electrode layer (13). A circumferential wall (14) of the arrangement is formed by an electrically insulating material. The field emitter tips (5) and the electrode layer (13) are connected to a d.c.
    Type: Application
    Filed: April 14, 2009
    Publication date: January 14, 2010
    Applicant: Dragerwerk AG & Co. KGaA
    Inventors: Wolfgang Bather, Stefan Zimmermann
  • Patent number: 7592679
    Abstract: A sensor includes at least two electrodes, and at least one nanowire extending substantially laterally between the electrodes. The at least one nanowire has at least two segments with a junction or connection formed therebetween. A sensing material changeable between at least two states is positioned adjacent to the junction or connection, and adjacent to at least a portion of each of the segments.
    Type: Grant
    Filed: October 19, 2006
    Date of Patent: September 22, 2009
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventors: Theodore I. Kamins, Philip J. Kuekes, Carrie L. Donley, Jason J. Blackstock
  • Patent number: 7582975
    Abstract: A nanowire device includes a nanowire formed between two surfaces, and a gap formed at a predetermined location in the nanowire.
    Type: Grant
    Filed: April 27, 2007
    Date of Patent: September 1, 2009
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventors: Theodore I. Kamins, Philip J. Kuekes, Carrie L. Donley, Jason J. Blackstock
  • Patent number: 7569941
    Abstract: One-dimensional nanostructures having uniform diameters of less than approximately 200 nm. These inventive nanostructures, which we refer to as “nanowires”, include single-crystalline homostructures as well as heterostructures of at least two single-crystalline materials having different chemical compositions. Because single-crystalline materials are used to form the heterostructure, the resultant heterostructure will be single-crystalline as well. The nanowire heterostructures are generally based on a semiconducting wire wherein the doping and composition are controlled in either the longitudinal or radial directions, or in both directions, to yield a wire that comprises different materials. Examples of resulting nanowire heterostructures include a longitudinal heterostructure nanowire (LOHN) and a coaxial heterostructure nanowire (COHN).
    Type: Grant
    Filed: December 22, 2006
    Date of Patent: August 4, 2009
    Assignee: The Regents of the University of California
    Inventors: Arun Majumdar, Ali Shakouri, Timothy D. Sands, Peidong Yang, Samuel S. Mao, Richard E. Russo, Henning Feick, Eicke R. Weber, Hannes Kind, Michael Huang, Haoquan Yan, Yiying Wu, Rong Fan
  • Patent number: 7569847
    Abstract: One-dimensional nanostructures having uniform diameters of less than approximately 200 nm. These inventive nanostructures, which we refer to as “nanowires”, include single-crystalline homostructures as well as heterostructures of at least two single-crystalline materials having different chemical compositions. Because single-crystalline materials are used to form the heterostructure, the resultant heterostructure will be single-crystalline as well. The nanowire heterostructures are generally based on a semiconducting wire wherein the doping and composition are controlled in either the longitudinal or radial directions, or in both directions, to yield a wire that comprises different materials. Examples of resulting nanowire heterostructures include a longitudinal heterostructure nanowire (LOHN) and a coaxial heterostructure nanowire (COHN).
    Type: Grant
    Filed: January 20, 2005
    Date of Patent: August 4, 2009
    Assignee: The Regents of the University of California
    Inventors: Arun Majumdar, Ali Shakouri, Timothy D. Sands, Peidong Yang, Samuel S. Mao, Richard E. Russo, Henning Feick, Eicke R. Weber, Hannes Kind, Michael Huang, Haoquan Yan, Yiying Wu, Rong Fan
  • Publication number: 20090001498
    Abstract: Nanowire-based photodiodes are disclosed. The photodiodes include a first optical waveguide having a tapered first end, a second optical waveguide having a tapered second end, and at least one nanowire comprising at least one semiconductor material connecting the first and second ends in a bridging configuration. Methods of making the photodiodes are also disclosed.
    Type: Application
    Filed: June 26, 2007
    Publication date: January 1, 2009
    Inventors: Shih-Yuan Wang, Michael Renne Ty Tan, Alexandre M. Bratkovski, R. Stanley Williams, Nobuhiko Kobayashi
  • Publication number: 20080266556
    Abstract: Various aspects of the present invention are directed to a nanowire configured to couple electromagnetic radiation to a selected guided wave and devices incorporating such nanowires. In one aspect of the present invention, a nanowire structure includes a substrate and at least one nanowire attached to the substrate. A diameter, composition, or both may vary generally periodically along a length of the at least one nanowire. A coating may cover at least part of a circumferential surface of the at least one nanowire. The nanowire structure may be incorporated in a device including at least one optical-to-electrical converter operable to convert a guided wave propagating along the length of the at least one nanowire, at least in part responsive to irradiation, to an electrical signal. Other aspects of the present invention are directed to methods of fabricating nanowires structured to support guided waves.
    Type: Application
    Filed: April 25, 2007
    Publication date: October 30, 2008
    Inventors: Theodore I. Kamins, Alexandre M. Bratkovski
  • Publication number: 20080150025
    Abstract: Various methods for forming active electronic devices, such as field-effect transistors, and devices made using these methods are disclosed. Some of the methods include growing freestanding nano-, micro- and milli-scale semiconducting structures that are used for the active semiconducting channels of the active electronic devices. Others of the methods include forming strands of active electronic devices along a wire. Yet others of the methods utilize both of these concepts so that the active electronic devices on a particular strand include freestanding semiconducting structures.
    Type: Application
    Filed: December 13, 2006
    Publication date: June 26, 2008
    Applicant: Versatilis LLC
    Inventor: Ajaykumar R. Jain
  • Patent number: 7332810
    Abstract: An integrated circuit device having vias having good resistance to migration causing the breaking of a wiring line, or an integrated circuit device having a wiring structure that is fined by breaking the limit of lithography technique is provided. The former device comprises a plurality of elements fabricated on a semiconductor substrate, wiring lines for making the elements and the integrated circuit device function, and vias for interconnecting wiring lines in separate layers, the via being formed of one or more cylindrical structures made up of carbon atoms. The latter device comprises a plurality of elements fabricated on a semiconductor substrate and wiring members for making the elements and the integrated circuit device function, at least part of the wiring members being formed of one or more cylindrical structures made up of carbon atoms.
    Type: Grant
    Filed: June 8, 2006
    Date of Patent: February 19, 2008
    Assignee: Fujitsu Limited
    Inventor: Yuji Awano
  • Patent number: 7247877
    Abstract: A method and structure for an integrated circuit comprising a first transistor and an embedded carbon nanotube field effect transistor (CNT FET) proximate to the first transistor, wherein the CNT FET is dimensioned smaller than the first transistor. The CNT FET is adapted to sense signals from the first transistor, wherein the signals comprise any of temperature, voltage, current, electric field, and magnetic field signals. Moreover, the CNT FET is adapted to measure stress and strain in the integrated circuit, wherein the stress and strain comprise any of mechanical and thermal stress and strain. Additionally, the CNT FET is adapted to detect defective circuits within the integrated circuit.
    Type: Grant
    Filed: August 20, 2004
    Date of Patent: July 24, 2007
    Assignee: International Business Machines Corporation
    Inventors: Mark C. Hakey, Mark E. Masters, Leah M. P. Pastel, David P. Vallett
  • Patent number: 7132677
    Abstract: An GaN light emitting diode (LED) having a nanorod (or, nanowire) structure is disclosed. The GaN LED employs GaN nanorods in which a n-type GaN nanorod, an InGaN quantum well and a p-type GaN nanorod are subsequently formed in a longitudinal direction by inserting the InGaN quantum well into a p-n junction interface of the p-n junction GaN nanorod. In addition, a plurality of such GaN nanorods are arranged in an array so as to provide an LED having much greater brightness and higher light emission efficiency than a conventional laminated-film GaN LED.
    Type: Grant
    Filed: February 13, 2004
    Date of Patent: November 7, 2006
    Assignee: Dongguk University
    Inventors: Hwa-Mok Kim, Tae-Won Kang, Kwan-Soo Chung
  • Patent number: 7084507
    Abstract: An integrated circuit device having vias having good resistance to migration causing the breaking of a wiring line, or an integrated circuit device having a wiring structure that is fined by breaking the limit of lithography technique is provided. The former device comprises a plurality of elements fabricated on a semiconductor substrate, wiring lines for making the elements and the integrated circuit device function, and vias for interconnecting wiring lines in separate layers, the via being formed of one or more cylindrical structures made up of carbon atoms. The latter device comprises a plurality of elements fabricated on a semiconductor substrate and wiring members for making the elements and the integrated circuit device function, at least part of the wiring members being formed of one or more cylindrical structures made up of carbon atoms.
    Type: Grant
    Filed: March 28, 2002
    Date of Patent: August 1, 2006
    Assignee: Fujitsu Limited
    Inventor: Yuji Awano