Search Patents
  • Self-aligned gate endcap (SAGE) architecture having gate contacts
    Patent number: 11424245
    Abstract: Self-aligned gate endcap (SAGE) architectures having gate contacts, and methods of fabricating SAGE architectures having gate contacts, are described. In an example, an integrated circuit structure includes a gate structure over a semiconductor fin. A gate endcap isolation structure is laterally adjacent to and in contact with the gate structure. A trench contact structure is over the semiconductor fin, where the gate endcap isolation structure is laterally adjacent to and in contact with the trench contact structure. A local gate-to-contact interconnect is electrically connecting the gate structure to the trench contact structure.
    Type: Grant
    Filed: March 6, 2019
    Date of Patent: August 23, 2022
    Assignee: Intel Corporation
    Inventors: Sairam Subramanian, Walid M. Hafez
  • SELF-ALIGNED GATE ENDCAP (SAGE) ARCHITECTURES WITH VERTICAL SIDEWALLS
    Publication number: 20210351300
    Abstract: Self-aligned gate endcap (SAGE) architectures with vertical sidewalls, and methods of fabricating self-aligned gate endcap (SAGE) architectures with vertical sidewalls, are described. In an example, an integrated circuit structure includes a semiconductor fin having sidewalls along a length of the semiconductor fin, each sidewall tapering outwardly from a top of the semiconductor fin toward a bottom of the semiconductor fin. A gate endcap isolation structure is spaced apart from the semiconductor fin and has a length parallel with the length of the semiconductor fin. The gate endcap isolation structure has a substantially vertical sidewall laterally facing one of the outwardly tapering sidewalls of the semiconductor fin.
    Type: Application
    Filed: May 7, 2020
    Publication date: November 11, 2021
    Inventors: Ritesh K. DAS, Kiran CHIKKADI, Ryan PEARCE
  • SELF-ALIGNED GATE ENDCAP (SAGE) ARCHITECTURES WITHOUT FIN END GAP
    Publication number: 20210091075
    Abstract: Self-aligned gate endcap (SAGE) architectures without fin end gaps, and methods of fabricating self-aligned gate endcap (SAGE) architectures without fin end gaps, are described. In an example, an integrated circuit structure includes a semiconductor fin having a cut along a length of the semiconductor fin. A gate endcap isolation structure has a first portion parallel with the length of the semiconductor fin and is spaced apart from the semiconductor fin. The gate endcap isolation structure also has a second portion in a location of the cut of the semiconductor fin and in contact with the semiconductor fin.
    Type: Application
    Filed: September 23, 2019
    Publication date: March 25, 2021
    Inventors: Szuya S. LIAO, Scott B. CLENDENNING, Jessica TORRES, Lukas BAUMGARTEL, Kiran CHIKKADI, Diane LANCASTER, Matthew V. METZ, Florian GSTREIN, Martin M. MITAN, Rami HOURANI
  • Dual self-aligned gate endcap (SAGE) architectures
    Patent number: 11688792
    Abstract: Dual self-aligned gate endcap (SAGE) architectures, and methods of fabricating dual self-aligned gate endcap (SAGE) architectures, are described. In an example, an integrated circuit structure includes a first semiconductor fin having a cut along a length of the first semiconductor fin. A second semiconductor fin is parallel with the first semiconductor fin. A first gate endcap isolation structure is between the first semiconductor fin and the second semiconductor fin. A second gate endcap isolation structure is in a location of the cut along the length of the first semiconductor fin.
    Type: Grant
    Filed: November 15, 2021
    Date of Patent: June 27, 2023
    Assignee: Intel Corporation
    Inventors: Sairam Subramanian, Walid M. Hafez, Sridhar Govindaraju, Mark Liu, Szuya S. Liao, Chia-Hong Jan, Nick Lindert, Christopher Kenyon
  • Dual self-aligned gate endcap (SAGE) architectures
    Patent number: 11205708
    Abstract: Dual self-aligned gate endcap (SAGE) architectures, and methods of fabricating dual self-aligned gate endcap (SAGE) architectures, are described. In an example, an integrated circuit structure includes a first semiconductor fin having a cut along a length of the first semiconductor fin. A second semiconductor fin is parallel with the first semiconductor fin. A first gate endcap isolation structure is between the first semiconductor fin and the second semiconductor fin. A second gate endcap isolation structure is in a location of the cut along the length of the first semiconductor fin.
    Type: Grant
    Filed: April 2, 2018
    Date of Patent: December 21, 2021
    Assignee: Intel Corporation
    Inventors: Sairam Subramanian, Walid M. Hafez, Sridhar Govindaraju, Mark Liu, Szuya S. Liao, Chia-Hong Jan, Nick Lindert, Christopher Kenyon
  • UNIDIRECTIONAL SELF-ALIGNED GATE ENDCAP (SAGE) ARCHITECTURES WITH GATE-ORTHOGONAL WALLS
    Publication number: 20190304971
    Abstract: Unidirectional self-aligned gate endcap (SAGE) architectures with gate-orthogonal walls, and methods of fabricating unidirectional self-aligned gate endcap (SAGE) architectures with gate-orthogonal walls, are described. In an example, integrated circuit structure includes a first semiconductor fin having a cut along a length of the first semiconductor fin. A second semiconductor fin has a cut along a length of the second semiconductor fin. A gate endcap isolation structure is between the first semiconductor fin and the second semiconductor fin. The gate endcap isolation structure has a substantially uniform width along the lengths of the first and second semiconductor fins.
    Type: Application
    Filed: March 30, 2018
    Publication date: October 3, 2019
    Inventors: Walid M. HAFEZ, Sridhar GOVINDARAJU, Mark LIU, Szuya S. LIAO, Chia-Hong JAN, Nick LINDERT, Christopher KENYON, Sairam SUBRAMANIAN
  • SELF-ALIGNED GATE ENDCAP (SAGE) ARCHITECTURES WITH IMPROVED CAP
    Publication number: 20230197826
    Abstract: Self-aligned gate endcap (SAGE) architectures with improved caps, and methods of fabricating self-aligned gate endcap (SAGE) architectures with improved caps, are described. In an example, an integrated circuit structure includes a first gate structure over a first semiconductor fin. A second gate structure is over a second semiconductor fin. A gate endcap isolation structure is between the first gate structure and the second gate structure. The gate endcap isolation structure has a higher-k dielectric cap layer on a lower-k dielectric wall. The higher-k dielectric cap layer includes hafnium and oxygen and has 70% or greater monoclinic crystallinity.
    Type: Application
    Filed: December 21, 2021
    Publication date: June 22, 2023
    Inventors: Christine RADLINGER, Tongtawee WACHARASINDHU, Andre BARAN, Kiran CHIKKADI, Devin MERRILL, Nilesh DENDGE, David J. TOWNER, Christopher KENYON
  • SELF-ALIGNED GATE ENDCAP (SAGE) ARCHITECTURES WITHOUT FIN END GAP
    Publication number: 20240088143
    Abstract: Self-aligned gate endcap (SAGE) architectures without fin end gaps, and methods of fabricating self-aligned gate endcap (SAGE) architectures without fin end gaps, are described. In an example, an integrated circuit structure includes a semiconductor fin having a cut along a length of the semiconductor fin. A gate endcap isolation structure has a first portion parallel with the length of the semiconductor fin and is spaced apart from the semiconductor fin. The gate endcap isolation structure also has a second portion in a location of the cut of the semiconductor fin and in contact with the semiconductor fin.
    Type: Application
    Filed: November 21, 2023
    Publication date: March 14, 2024
    Inventors: Szuya S. Liao, Scott B. CLENDENNING, Jessica TORRES, Lukas BAUMGARTEL, Kiran CHIKKADI, Diane LANCASTER, Matthew V. METZ, Florian GSTREIN, Martin M. MITAN, Rami HOURANI
  • UNIDIRECTIONAL SELF-ALIGNED GATE ENDCAP (SAGE) ARCHITECTURES WITH GATE-ORTHOGONAL WALLS
    Publication number: 20220077145
    Abstract: Unidirectional self-aligned gate endcap (SAGE) architectures with gate-orthogonal walls, and methods of fabricating unidirectional self-aligned gate endcap (SAGE) architectures with gate-orthogonal walls, are described. In an example, integrated circuit structure includes a first semiconductor fin having a cut along a length of the first semiconductor fin. A second semiconductor fin has a cut along a length of the second semiconductor fin. A gate endcap isolation structure is between the first semiconductor fin and the second semiconductor fin. The gate endcap isolation structure has a substantially uniform width along the lengths of the first and second semiconductor fins.
    Type: Application
    Filed: November 17, 2021
    Publication date: March 10, 2022
    Inventors: Walid M. HAFEZ, Sridhar GOVINDARAJU, Mark LIU, Szuya S. LIAO, Chia-Hong JAN, Nick LINDERT, Christopher KENYON, Sairam SUBRAMANIAN
  • SELF-ALIGNED GATE ENDCAP (SAGE) ARCHITECTURE HAVING LOCAL INTERCONNECTS
    Publication number: 20200286891
    Abstract: Self-aligned gate endcap (SAGE) architectures having local interconnects, and methods of fabricating SAGE architectures having local interconnects, are described. In an example, an integrated circuit structure includes a first gate structure over a first semiconductor fin, and a second gate structure over a second semiconductor fin. A gate endcap isolation structure is between the first and second semiconductor fins and laterally between and in contact with the first and second gate structures. A gate plug is over the gate endcap isolation structure and laterally between and in contact with the first and second gate structures. A local gate interconnect is between the gate plug and the gate endcap isolation structure, the local gate interconnect in contact with the first and second gate structures.
    Type: Application
    Filed: March 6, 2019
    Publication date: September 10, 2020
    Inventors: Sairam SUBRAMANIAN, Walid M. HAFEZ, Sridhar GOVINDARAJU, Kiran CHIKKADI
  • NEW FRACTION OF SAGE EXTRACT AND USES THEREOF
    Publication number: 20160106794
    Abstract: The present invention relates to a new fraction of sage extract in which only traces of rosmarinic acid, carnosic acid and derivatives thereof and resins are present, a process for the preparation of such extract, compositions comprising it, and the use of the extract fraction and of the compositions for the protection of the skin or mucous membranes.
    Type: Application
    Filed: May 22, 2014
    Publication date: April 21, 2016
    Inventor: Valentino MERCATI
  • SELF-ALIGNED GATE ENDCAP (SAGE) ARCHITECTURE HAVING GATE OR CONTACT PLUGS
    Publication number: 20200287015
    Abstract: Self-aligned gate endcap (SAGE) architectures having gate or contact plugs, and methods of fabricating SAGE architectures having gate or contact plugs, are described. In an example, an integrated circuit structure includes a first gate structure over a first semiconductor fin. A second gate structure is over a second semiconductor fin. A gate endcap isolation structure is between the first and second semiconductor fins and laterally between and in contact with the first and second gate structures. A gate plug is over the gate endcap isolation structure and laterally between the first gate structure and the second gate structure. A crystalline metal oxide material is laterally between and in contact with the gate plug and the first gate structure, and laterally between and in contact with the gate plug and the second gate structure.
    Type: Application
    Filed: March 6, 2019
    Publication date: September 10, 2020
    Inventors: Sairam SUBRAMANIAN, Walid M. HAFEZ
  • SELF-ALIGNED GATE ENDCAP (SAGE) ARCHITECTURE HAVING GATE OR CONTACT PLUGS
    Publication number: 20220359705
    Abstract: Self-aligned gate endcap (SAGE) architectures having gate or contact plugs, and methods of fabricating SAGE architectures having gate or contact plugs, are described. In an example, an integrated circuit structure includes a first gate structure over a first semiconductor fin. A second gate structure is over a second semiconductor fin. A gate endcap isolation structure is between the first and second semiconductor fins and laterally between and in contact with the first and second gate structures. A gate plug is over the gate endcap isolation structure and laterally between the first gate structure and the second gate structure. A crystalline metal oxide material is laterally between and in contact with the gate plug and the first gate structure, and laterally between and in contact with the gate plug and the second gate structure.
    Type: Application
    Filed: July 22, 2022
    Publication date: November 10, 2022
    Inventors: Sairam SUBRAMANIAN, Walid M. HAFEZ
  • 3-alkoxybenzylamine derivatives and their use as medicines for treating schizophrenia
    Patent number: 6350913
    Abstract: The present invention relates to novel 3-alkoxybenzylamine derivatives of general formula (1): which are useful as medicinal products and in particular as antipsychotic agents.
    Type: Grant
    Filed: May 29, 2001
    Date of Patent: February 26, 2002
    Assignee: Pierre Fabre Medicament
    Inventors: Bernard Vacher, Stéphane Cuisiat, Wouter Koek
  • Self-aligned gate endcap (SAGE) architecture having local interconnects
    Patent number: 11705453
    Abstract: Self-aligned gate endcap (SAGE) architectures having local interconnects, and methods of fabricating SAGE architectures having local interconnects, are described. In an example, an integrated circuit structure includes a first gate structure over a first semiconductor fin, and a second gate structure over a second semiconductor fin. A gate endcap isolation structure is between the first and second semiconductor fins and laterally between and in contact with the first and second gate structures. A gate plug is over the gate endcap isolation structure and laterally between and in contact with the first and second gate structures. A local gate interconnect is between the gate plug and the gate endcap isolation structure, the local gate interconnect in contact with the first and second gate structures.
    Type: Grant
    Filed: March 6, 2019
    Date of Patent: July 18, 2023
    Assignee: Intel Corporation
    Inventors: Sairam Subramanian, Walid M. Hafez, Sridhar Govindaraju, Kiran Chikkadi
  • SELF-ALIGNED GATE ENDCAP (SAGE) ARCHITECTURES WITH REDUCED CAP
    Publication number: 20220310818
    Abstract: Self-aligned gate endcap (SAGE) architectures with reduced or removed caps, and methods of fabricating self-aligned gate endcap (SAGE) architectures with reduced or removed caps, are described. In an example, an integrated circuit structure includes a first gate electrode over a first semiconductor fin. A second gate electrode is over a second semiconductor fin. A gate endcap isolation structure is between the first gate electrode and the second gate electrode, the gate endcap isolation structure having a higher-k dielectric cap layer on a lower-k dielectric wall. A local interconnect is on the first gate electrode, on the higher-k dielectric cap layer, and on the second gate electrode, the local interconnect having a bottommost surface above an uppermost surface of the higher-k dielectric cap layer.
    Type: Application
    Filed: March 24, 2021
    Publication date: September 29, 2022
    Inventors: Seung Hoon SUNG, Tristan TRONIC, Szuya S. LIAO, Jack T. KAVALIEROS
  • Self-aligned gate endcap (SAGE) architecture having gate or contact plugs
    Patent number: 11876121
    Abstract: Self-aligned gate endcap (SAGE) architectures having gate or contact plugs, and methods of fabricating SAGE architectures having gate or contact plugs, are described. In an example, an integrated circuit structure includes a first gate structure over a first semiconductor fin. A second gate structure is over a second semiconductor fin. A gate endcap isolation structure is between the first and second semiconductor fins and laterally between and in contact with the first and second gate structures. A gate plug is over the gate endcap isolation structure and laterally between the first gate structure and the second gate structure. A crystalline metal oxide material is laterally between and in contact with the gate plug and the first gate structure, and laterally between and in contact with the gate plug and the second gate structure.
    Type: Grant
    Filed: July 22, 2022
    Date of Patent: January 16, 2024
    Assignee: Intel Corporation
    Inventors: Sairam Subramanian, Walid M. Hafez
  • Unidirectional self-aligned gate endcap (SAGE) architectures with gate-orthogonal walls
    Patent number: 11217582
    Abstract: Unidirectional self-aligned gate endcap (SAGE) architectures with gate-orthogonal walls, and methods of fabricating unidirectional self-aligned gate endcap (SAGE) architectures with gate-orthogonal walls, are described. In an example, integrated circuit structure includes a first semiconductor fin having a cut along a length of the first semiconductor fin. A second semiconductor fin has a cut along a length of the second semiconductor fin. A gate endcap isolation structure is between the first semiconductor fin and the second semiconductor fin. The gate endcap isolation structure has a substantially uniform width along the lengths of the first and second semiconductor fins.
    Type: Grant
    Filed: March 30, 2018
    Date of Patent: January 4, 2022
    Assignee: Intel Corporation
    Inventors: Walid M. Hafez, Sridhar Govindaraju, Mark Liu, Szuya S. Liao, Chia-Hong Jan, Nick Lindert, Christopher Kenyon, Sairam Subramanian
  • Self-aligned gate endcap (SAGE) architecture having gate or contact plugs
    Patent number: 11444171
    Abstract: Self-aligned gate endcap (SAGE) architectures having gate or contact plugs, and methods of fabricating SAGE architectures having gate or contact plugs, are described. In an example, an integrated circuit structure includes a first gate structure over a first semiconductor fin. A second gate structure is over a second semiconductor fin. A gate endcap isolation structure is between the first and second semiconductor fins and laterally between and in contact with the first and second gate structures. A gate plug is over the gate endcap isolation structure and laterally between the first gate structure and the second gate structure. A crystalline metal oxide material is laterally between and in contact with the gate plug and the first gate structure, and laterally between and in contact with the gate plug and the second gate structure.
    Type: Grant
    Filed: March 6, 2019
    Date of Patent: September 13, 2022
    Assignee: Intel Corporation
    Inventors: Sairam Subramanian, Walid M. Hafez
  • Unidirectional self-aligned gate endcap (SAGE) architectures with gate-orthogonal walls
    Patent number: 11605632
    Abstract: Unidirectional self-aligned gate endcap (SAGE) architectures with gate-orthogonal walls, and methods of fabricating unidirectional self-aligned gate endcap (SAGE) architectures with gate-orthogonal walls, are described. In an example, integrated circuit structure includes a first semiconductor fin having a cut along a length of the first semiconductor fin. A second semiconductor fin has a cut along a length of the second semiconductor fin. A gate endcap isolation structure is between the first semiconductor fin and the second semiconductor fin. The gate endcap isolation structure has a substantially uniform width along the lengths of the first and second semiconductor fins.
    Type: Grant
    Filed: November 17, 2021
    Date of Patent: March 14, 2023
    Assignee: Intel Corporation
    Inventors: Walid M. Hafez, Sridhar Govindaraju, Mark Liu, Szuya S. Liao, Chia-Hong Jan, Nick Lindert, Christopher Kenyon, Sairam Subramanian
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