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  • Heterostructure field effect transistor with same channel and barrier configuration for PMOS and NMOS
    Patent number: 8933488
    Abstract: In accordance with one or more embodiments, an apparatus and method involves a channel region, barrier layers separated by the channel region and a dielectric on one of the barrier layers. The barrier layers have band gaps that are different than a band gap of the channel region, and confine both electrons and holes in the channel region. A gate electrode applies electric field to the channel region via the dielectric. In various contexts, the apparatus and method are amenable to implementation for both electron-based and hole-based implementations, such as for nmos, pmos, and cmos applications.
    Type: Grant
    Filed: December 1, 2011
    Date of Patent: January 13, 2015
    Assignee: The Board of Trustees of the Leland Stanford Junior Univerity
    Inventors: Aneesh Nainani, Krishna Chandra Saraswat
  • Germanium substrate-type materials and approach therefor
    Patent number: 7772078
    Abstract: Germanium circuit-type structures are facilitated. In one example embodiment, a multi-step growth and anneal process is implemented to grow Germanium (Ge) containing material, such as heteroepitaxial-Germanium, on a substrate including Silicon (Si) or Silicon-containing material. In certain applications, defects are generally confined near a Silicon/Germanium interface, with defect threading to an upper surface of the Germanium containing material generally being inhibited. These approaches are applicable to a variety of devices including Germanium MOS capacitors, pMOSFETs and optoelectronic devices.
    Type: Grant
    Filed: August 26, 2008
    Date of Patent: August 10, 2010
    Assignees: The Board of Trustees of the Leland Stanford Junior University, Canon Kabushiki Kaisha
    Inventors: Ammar Munir Nayfeh, Chi On Chui, Krishna C. Saraswat, Takao Yonehara
  • Germanium substrate-type materials and approach therefor
    Patent number: 7495313
    Abstract: Germanium circuit-type structures are facilitated. In one example embodiment, a multi-step growth and anneal process is implemented to grow Germanium (Ge) containing material, such as heteroepitaxial-Germanium, on a substrate including Silicon (Si) or Silicon-containing material. In certain applications, defects are generally confined near a Silicon/Germanium interface, with defect threading to an upper surface of the Germanium containing material generally being inhibited. These approaches are applicable to a variety of devices including Germanium MOS capacitors, pMOSFETs and optoelectronic devices.
    Type: Grant
    Filed: July 22, 2005
    Date of Patent: February 24, 2009
    Assignees: Board of Trustees of the Leland Stanford Junior University, Canon Kabushiki Kaisha
    Inventors: Ammar Munir Nayfeh, Chi On Chui, Krishna C. Saraswat, Takao Yonehara
  • TRANSISTOR-BASED APPARATUSES, SYSTEMS AND METHODS
    Publication number: 20130307025
    Abstract: Various aspects of the invention are directed to memory circuits and their implementation. According to an example embodiment, an apparatus includes a channel region between raised source and drain regions which are configured and arranged with respective bandgap offsets relative to the channel region to confine carriers in the channel region. The apparatus also includes front and back gates respectively separated from the channel region by gate dielectrics. The raised source and drain regions have respective portions laterally adjacent the front gate and adjacent the channel region. Carriers are stored in the channel region via application of voltage(s) to the front and back gates, and relative to bias(es) at the source and drain regions.
    Type: Application
    Filed: February 22, 2013
    Publication date: November 21, 2013
    Applicant: The Board of Trustees of the Leland Stanford Junior University
    Inventors: Ashish Pal, Aneesh Nainani, Krishna Chandra Saraswat
  • Crossed Nanobeam Structure for a Low-Threshold Germanium Laser
    Publication number: 20150372455
    Abstract: A crossed nanobeam structure for strain engineering in semiconductor devices is provided. For example, such a structure can be used for a low-threshold germanium laser. While the photonic crystal nanobeam enables light confinement in a subwavelength volume with small optical loss, another crossing nanobeam induces high tensile strain in the small region where the optical mode is tightly confined. As maintaining a small optical loss and a high tensile strain reduces the required pumping for achieving net optical gain beyond cavity losses, this technique can be used to develop an extremely low-threshold Ge laser source. Moreover, the structure can be easily integrated into electronic and photonic circuits.
    Type: Application
    Filed: June 23, 2015
    Publication date: December 24, 2015
    Inventors: Donguk Nam, Jan A. Petykiewicz, Devanand S. Sukhdeo, Shashank Gupta, Jelena Vuckovic, Krishna C. Saraswat
  • Transistor-based apparatuses, systems and methods
    Patent number: 8969924
    Abstract: Various aspects of the invention are directed to memory circuits and their implementation. According to an example embodiment, an apparatus includes a channel region between raised source and drain regions which are configured and arranged with respective bandgap offsets relative to the channel region to confine carriers in the channel region. The apparatus also includes front and back gates respectively separated from the channel region by gate dielectrics. The raised source and drain regions have respective portions laterally adjacent the front gate and adjacent the channel region. Carriers are stored in the channel region via application of voltage(s) to the front and back gates, and relative to bias(es) at the source and drain regions.
    Type: Grant
    Filed: February 22, 2013
    Date of Patent: March 3, 2015
    Assignee: The Board of Trustees of the Leland Stanford Junior University
    Inventors: Ashish Pal, Aneesh Nainani, Krishna Chandra Saraswat
  • Tandem solar cells having a top or bottom metal chalcogenide cell
    Publication number: 20210359150
    Abstract: Tandem solar cell configurations are provided where at least one of the cells is a metal chalcogenide cell. A four-terminal tandem solar cell configuration has two electrically independent solar cells stacked on each other. A two-terminal solar cell configuration has two electrically coupled solar cells (same current through both cells) stacked on each other. Carrier selective contacts can be used to make contact to the metal chalcogenide cell (s) to alleviate the troublesome Fermi level pinning issue. Carrier-selective contacts can also remove the need to provide doping of the metal chalcogenide. Doping of the metal chalcogenide can be provided by charge transfer. These two ideas can be practiced independently or together in any combination.
    Type: Application
    Filed: November 5, 2019
    Publication date: November 18, 2021
    Inventors: Koosha Nassiri Nazif, Raisul Islam, Jin-Hong Park, Krishna C. Saraswat
  • Crossed nanobeam structure for a low-threshold germanium laser
    Patent number: 9595812
    Abstract: A crossed nanobeam structure for strain engineering in semiconductor devices is provided. For example, such a structure can be used for a low-threshold germanium laser. While the photonic crystal nanobeam enables light confinement in a subwavelength volume with small optical loss, another crossing nanobeam induces high tensile strain in the small region where the optical mode is tightly confined. As maintaining a small optical loss and a high tensile strain reduces the required pumping for achieving net optical gain beyond cavity losses, this technique can be used to develop an extremely low-threshold Ge laser source. Moreover, the structure can be easily integrated into electronic and photonic circuits.
    Type: Grant
    Filed: June 23, 2015
    Date of Patent: March 14, 2017
    Assignee: The Board of Trustees of the Leland Stanford Junior University
    Inventors: Donguk Nam, Jan A. Petykiewicz, Devanand S. Sukhdeo, Shashank Gupta, Jelena Vuckovic, Krishna C. Saraswat
  • Thermal/microwave remote plasma multiprocessing reactor and method of use
    Patent number: 4913929
    Abstract: A novel cold wall single wafer rapid thermal/microwave remote plasma multiprocessing reactor comprising a vacuum chamber having means for mounting a wafer in the chamber, means for providing optical flux mounted adjacent one wall facing the back side of the wafer for optical heating of the wafer, and ports for plasma injection such that remote plasma can be generated and pumped into the chamber. Ports are provided for gas injection both through the plasma generating chamber and for non-plasma injection. The plasma and non-plasma ports are connected through separate manifolds to a plurality of gas sources. The comprehensive reactor design is such that several wafer processing steps can be done sequentially in situ, while providing for optimization of each processing step.
    Type: Grant
    Filed: April 21, 1987
    Date of Patent: April 3, 1990
    Assignee: The Board of Trustees of the Leland Stanford Junior University
    Inventors: Mehrdad M. Moslehi, Krishna C. Saraswat
  • Semiconductor device with high on current and low leakage
    Patent number: 7728387
    Abstract: Various semiconductor devices and methods of manufacture are employed. According to an example embodiment of the present invention, a MOS-compatible semiconductor device exhibits high channel mobility and low leakage. The device includes a channel region having a high-mobility strained material layer and a tunneling mitigation layer on the strained material layer to mitigate tunnel leakage. The strained material has a lattice structure that is strained to match the lattice structure of the tunneling mitigation layer. An insulator layer is on the tunneling mitigation layer, and an electrode is over the insulator and adapted to apply a voltage bias to the channel region to switch the device between conductive and nonconductive states. Current is transported in the conductive state as predominantly facilitated via the mobility of the strained material layer, and wherein tunneling current in the nonconductive state is mitigated by the tunneling mitigation layer.
    Type: Grant
    Filed: June 12, 2007
    Date of Patent: June 1, 2010
    Assignee: The Board of Trustees of the Leland Stanford Junior University
    Inventors: Tejas Krishnamohan, Krishna Chandra Saraswat
  • Tandem solar cells having a top or bottom metal chalcogenide cell
    Patent number: 11588066
    Abstract: Tandem solar cell configurations are provided where at least one of the cells is a metal chalcogenide cell. A four-terminal tandem solar cell configuration has two electrically independent solar cells stacked on each other. A two-terminal solar cell configuration has two electrically coupled solar cells (same current through both cells) stacked on each other. Carrier selective contacts can be used to make contact to the metal chalcogenide cell (s) to alleviate the troublesome Fermi level pinning issue. Carrier-selective contacts can also remove the need to provide doping of the metal chalcogenide. Doping of the metal chalcogenide can be provided by charge transfer. These two ideas can be practiced independently or together in any combination.
    Type: Grant
    Filed: November 5, 2019
    Date of Patent: February 21, 2023
    Assignee: The Board of Trustees of the Leland Stanford Junior Univesity
    Inventors: Koosha Nassiri Nazif, Raisul Islam, Jin-Hong Park, Krishna C. Saraswat
  • High-k dielectric for thermodynamically-stable substrate-type materials
    Patent number: 7271458
    Abstract: Excellent capacitor-voltage characteristics with near-ideal hysteresis are realized in a capacitive-like structure that uses an electrode substrate-type material with a high-k dielectric layer having a thickness of a few-to-several Angstroms capacitance-based SiO2 equivalent (“TOx, Eq”). According to one particular example embodiment, a semiconductor device structure has an electrode substrate-type material having a Germanium-rich surface material. The electrode substrate-type material is processed to provide this particular electrode surface material in a form that is thermodynamically stable with a high-k dielectric material. A dielectric layer is then formed over the electrode surface material with the high-k dielectric material at a surface that faces, lies against and is thermodynamically stable with the electrode surface material.
    Type: Grant
    Filed: March 31, 2003
    Date of Patent: September 18, 2007
    Assignee: The Board of Trustees of the LeLand Stanford Junior University
    Inventors: Chi On Chui, Krishna C. Saraswat, Baylor B. Triplett, Paul McIntyre
  • Layered and homogeneous films of aluminum and aluminum/silicon with titanium and tungsten for multilevel interconnects
    Patent number: 4673623
    Abstract: Layered structures (e.g., Al-Si/Ti/Al-Si . . . ) and homogeneous alloys of aluminum and aluminum/1 at. % silicon with titanium and tungsten and other refractory metals have been found to significantly reduce hillock densities in the films when small amounts of titanium or tungsten are homogeneously added. However, the resistivity of the films can become excessive. In addition, a new type of low density hillock can form. Layering of the films eliminates all hillocks and results in films of low resistivity. Such layered and homogeneous films made with Al-Si and Ti were found to be dry etchable. Electrical shorts in test structures with two levels of metal and LPCVD SiO.sub.2 as an interlayer dielectric have been characterized and layered films using Al-Si and Ti gave excellent results.
    Type: Grant
    Filed: May 6, 1985
    Date of Patent: June 16, 1987
    Assignee: The Board of Trustees of the Leland Stanford Junior University
    Inventors: Donald S. Gardner, Krishna C. Saraswat, Troy W. Barbee, Jr.
  • Low temperature germanium-silicon on insulator thin-film transistor
    Patent number: 5250818
    Abstract: MOS transistors are formed in thin films of Ge/Si alloys (Ge.sub.x Si.sub.1-x). According to the process of the present invention, polycrystalline films of Ge/Si are deposited using commercially-available LPCVD equipment, which in the preferred process uses silane and germane as the sources of Ge and Si. The deposited Ge.sub.x Si.sub.1-x films are polycrystalline at temperatures for processing down to as below 400.degree. C., and the films can be doped heavily by ion implantation and annealing at temperatures as low as 600.degree. C. to give high mobility and dopant activation yielding very low resistivity. By carrying out the annealing step in the formation of the thin film transistors in the temperature range of 400.degree. to 500.degree. C., the films provide very large grain size, minimizing the impact of grain boundaries in the polycrystalline films where the thin film transistors are to be formed. As a result, thin film MOS transistors are fabricated at temperatures below 500.degree. C.
    Type: Grant
    Filed: March 1, 1991
    Date of Patent: October 5, 1993
    Assignee: Board of Trustees of Leland Stanford University
    Inventors: Krishna C. Saraswat, Tsu-Jae King
  • Planarized multilevel interconnection for integrated circuits
    Patent number: 4888087
    Abstract: A process sequence for forming a multilevel tungsten interconnect array begins from a device level already planarized; alternate layers of silicon nitride and oxide are deposited. Via holes are then defined by masking, and anisotropically etched entirely through the nitride and oxide layers down to the device level (by reactive ion etching). Then the trenches for metal lines are defined intermediate the via holes and selectively plasma etched through the topmost layer of nitride and the topmost layer of dielectric, stopping atop the second layer of nitride. The oxide sidewalls of the metal line trenches and via holes are then etched laterally, using a wet etching process that results in much slower etching of the nitride layer so that nitride overhangs are formed that will protect the oxide sidewalls during subsequent vertical etchings.
    Type: Grant
    Filed: December 13, 1988
    Date of Patent: December 19, 1989
    Assignee: The Board of Trustees of the Leland Stanford Junior University
    Inventors: Mehrdad M. Moslehi, Krishna C. Saraswat
  • LUMINESCENT NANOMATERIAL POWDERS HAVING PREDETERMINED MORPHOLOGY AND METHOD OF MAKING
    Publication number: 20050285083
    Abstract: A method of making a luminescent nanomaterial having a plurality of nanoparticles. The luminescent nanomaterial includes at least one lanthanide group metal phosphate and at least one lanthanide series dopant, wherein each of the plurality of nanoparticles has a predetermined morphology. The luminescent nanomaterial has a high quantum efficiency and a high absorption value. The method yields a variety of morphologies and sizes of the plurality of nanoparticles. The particles size of the luminescent material varies from tens of nanometers to a few hundred of nanometers.
    Type: Application
    Filed: March 31, 2004
    Publication date: December 29, 2005
    Inventors: Kalaga Krishna, Mohan Manoharan, Geetha Karavoor, Shweta Saraswat, Sergio Loureiro
  • SYSTEMS AND METHODS FOR AUTOMATICALLY OPTIMIZING HIGH PERFORMANCE COMPUTING PROGRAMMING LANGUAGES
    Publication number: 20120131549
    Abstract: Systems and methods for replacing inferior code segments with optimal code segments. Systems and methods for making such replacements for programming languages using Message Passing Interface (MPI) are provided. For example, at the compiler level, point-to-point code segments may be identified and replaced with all-to-all code segments. Programming code may include X10, Chapel and other programming languages that support parallel for loop.
    Type: Application
    Filed: November 24, 2010
    Publication date: May 24, 2012
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Ganesh Bikshandi, Krishna Nandivada Venkata, Igor Peshansky, Vijay Anand Saraswat
  • Systems and methods for automatically optimizing high performance computing programming languages
    Patent number: 8924946
    Abstract: Systems and methods for replacing inferior code segments with optimal code segments. Systems and methods for making such replacements for programming languages using Message Passing Interface (MPI) are provided. For example, at the compiler level, point-to-point code segments may be identified and replaced with all-to-all code segments. Programming code may include X10, Chapel and other programming languages that support parallel for loop.
    Type: Grant
    Filed: November 24, 2010
    Date of Patent: December 30, 2014
    Assignee: International Business Machines Corporation
    Inventors: Ganesh Bikshandi, Krishna Nandivada Venkata, Igor Peshansky, Vijay Anand Saraswat
  • Luminescent nanomaterials powders having predetermined morphology and method of making
    Patent number: 6979415
    Abstract: A method of making a luminescent nanomaterial having a plurality of nanoparticles. The luminescent nanomaterial includes at least one lanthanide group metal phosphate and at least one lanthanide series dopant, wherein each of the plurality of nanoparticles has a predetermined morphology. The luminescent nanomaterial has a high quantum efficiency and a high absorption value. The method yields a variety of morphologies and sizes of the plurality of nanoparticles. The particles size of the luminescent material varies from tens of nanometers to a few hundred of nanometers.
    Type: Grant
    Filed: March 31, 2004
    Date of Patent: December 27, 2005
    Assignee: General Electric Company
    Inventors: Kalaga Murali Krishna, Mohan Manoharan, Geetha Karavoor, Shweta Saraswat, Sergio Paulo Martins Loureiro
  • Layered and homogeneous films of aluminum and aluminum/silicon with titanium and tungsten for multilevel interconnects
    Patent number: RE37032
    Abstract: Layered structures (e.g., Al-Si/Ti/Al-Si . . . ) and homogeneous alloys of aluminum and aluminum/1 at. % silicon with titanium and tungsten and other refractory metals have been found to significantly reduce hillock densities in the films when small amounts of titanium or tungsten are homogeneously added. However, the resistivity of the films can become excessive. In addition, a new type of low density hillock can form. Layering of the films eliminates all hillocks and results in films of low resistivity. Such layered and homogeneous films made with Al-Si and Ti were found to be dry etchable. Electrical shorts in test structures with two levels of metal and LPCVD SiO2 as an interlayer dielectric have been characterized and layered films using Al-Si and Ti gave excellent results.
    Type: Grant
    Filed: February 19, 1999
    Date of Patent: January 30, 2001
    Assignee: The Board of Trustees of the Leland Stanford Jr. University
    Inventors: Donald S. Gardner, Krishna C. Saraswat, Troy W. Barbee, Jr.
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