Search Patents
  • Maximizing potential good die per wafer, PGDW
    Patent number: 9798228
    Abstract: Consistent with an example embodiment, there is a semiconductor wafer substrate comprising a plurality of integrated circuits formed in arrays of rows and columns on the wafer substrate. A plurality of integrated circuits are in arrays of rows and columns on the wafer substrate; the rows and the columns have a first width. First and second saw lanes separate the integrated circuits, the first saw lanes are arranged parallel and equidistant with one another in a first direction defined by rows, and the second saw lanes are arranged parallel and equidistant with one another in a second direction defined by the columns. A plurality of process modules (PM) are on the wafer substrate, the PM modules defined in an at least one additional row/column having a second width. The at least one additional row/column is parallel to the plurality of device die in one direction.
    Type: Grant
    Filed: September 29, 2015
    Date of Patent: October 24, 2017
    Assignee: NXP B.V.
    Inventors: Hans Cobussen, Tonny Kamphuis, Heimo Scheucher, Laurentius de Kok
  • Integrated circuit with at least one bump
    Publication number: 20060071240
    Abstract: In an integrated circuit (1) having a substrate (3) and having a signal-processing circuit (4) which is produced at a surface (8) of the substrate (3), there is provided on the substrate surface (8) a protective layer (12) that has at least one aperture (13) through which a second contact pad (14) is electrically and mechanically connected to a first contact pad (9), wherein the second contact pad (14) is of a height of at least 15 ?m and projects laterally beyond the aperture (13) on all sides and is seated on the protective layer (12) by an overlap zone (z) that is closed on itself like a ring, wherein the overlap zone (z) has a constant width of overlap (w) of between 2 ?m and 15 ?m, and wherein at least one element of the signal-processing circuit (4), and preferably only one capacitor (5) of the signal-processing circuit (4), is provided opposite the first contact pad (9).
    Type: Application
    Filed: October 31, 2003
    Publication date: April 6, 2006
    Inventor: Heimo Scheucher
  • INTEGRATED CIRCUITS ON A WAFER AND METHODS FOR MANUFACTURING INTEGRATED CIRCUITS
    Publication number: 20100181568
    Abstract: Integrated circuits (1) on a wafer comprise a wafer substrate (2), a plurality of integrated circuits (1) formed lattice-like in rows and columns on the wafer substrate (2), and first and second saw lines (4, 5) separating the integrated circuits (1). The first saw lines (4) run parallel and equidistant with respect to each other in a first direction (x) defined by the rows and the second saw lines (5) run parallel and equidistant with respect to each other in a second direction (y)defined by the columns. The integrated circuits (1) on the wafer further comprise a plurality of process control modules (3) formed on the wafer substrate (2) such that a given process control module (3) of the plurality of process modules (3) is bounded by two consecutive first saw lines (4) as well as by two consecutive second saw lines (5).
    Type: Application
    Filed: July 10, 2008
    Publication date: July 22, 2010
    Applicant: NXP B.V.
    Inventors: Heimo Scheucher, Guido Dormans, Tonny Kamphuis
  • Integrated circuits on a wafer and methods for manufacturing integrated circuits
    Patent number: 8349708
    Abstract: Integrated circuits (1) on a wafer comprise a wafer substrate (2), a plurality of integrated circuits (1) formed lattice-like in rows and columns on the wafer substrate (2), and first and second saw lines (4, 5) separating the integrated circuits (1). The first saw lines (4) run parallel and equidistant with respect to each other in a first direction (x) defined by the rows and the second saw lines (5) run parallel and equidistant with respect to each other in a second direction (y)defined by the columns. The integrated circuits (1) on the wafer further comprise a plurality of process control modules (3) formed on the wafer substrate (2) such that a given process control module (3) of the plurality of process modules (3) is bounded by two consecutive first saw lines (4) as well as by two consecutive second saw lines (5).
    Type: Grant
    Filed: July 10, 2008
    Date of Patent: January 8, 2013
    Assignee: NXP B.V.
    Inventors: Heimo Scheucher, Guido Dormans, Tonny Kamphuis
  • Integrated circuit with at least one bump
    Patent number: 7247943
    Abstract: In an integrated circuit (1) having a substrate (3) and having a signal-processing circuit (4) which is produced at a surface (8) of the substrate (3), there is provided on the substrate surface (8) a protective layer (12) that has at least one aperture (13) through which a second contact pad (14) is electrically and mechanically connected to a first contact pad (9), wherein the second contact pad (14) is of a height of at least 15 ?m and projects laterally beyond the aperture (13) on all sides and is seated on the protective layer (12) by an overlap zone (z) that is closed on itself like a ring, wherein the overlap zone (z) has a constant width of overlap (w) of between 2 ?m and 15 ?m, and wherein at least one element of the signal-processing circuit (4), and preferably only one capacitor (5) of the signal-processing circuit (4), is provided opposite the first contact pad (9).
    Type: Grant
    Filed: October 31, 2003
    Date of Patent: July 24, 2007
    Assignee: NXP B.V.
    Inventor: Heimo Scheucher
  • Wafer with optical control modules in exposure fields
    Publication number: 20070152303
    Abstract: In a wafer (1) with a number of exposure fields (2), each of which exposure fields (2) comprising a number of lattice fields (3) with an IC (4) located therein, two groups (5, 7) of dicing paths (6, 8) are provided and four control module fields (A1, A2, A3, A4, B1, B2, B3, B4, C2, C4, D2, D4, E1, E3, F1, F3, G2, H1, J1) are assigned to each exposure field (2), each of which control module fields (A1, A2, A3, A4, B1, B2, B3, B4, C2, C4, D2, D4, E1, E3, F1, F3, G2, H1, J1) contains at least one optical control module (OCM-A1, OCMA2, OCM-A3, OCM-A4, OCM-B1, OCM-B2, OCM-B3, OCM-B4, OCM-C2, OCM-D4) and lies within the exposure field (2) in question and is provided in place of at least one lattice field (3) and is arranged at a mutual minimum distance (K).
    Type: Application
    Filed: December 9, 2004
    Publication date: July 5, 2007
    Inventors: Heimo Scheucher, Guenther Pfeiler, Rik Wenting
  • Wafer with optical control modules in ic fields
    Publication number: 20070158798
    Abstract: In a wafer (1) with a number of exposure fields (2), each of which exposure fields comprises a number of lattice fields (3) with an IC (4) located therein, two groups (5, 7) of saw paths (6, 8) are provided and two control module fields (A1, A2, B1, B2, C1, C2, D1, D2) are assigned to each exposure field, each of which control module fields contains at least one optical control module (OCM-A1, OCM-A2, OCM-B1, OCM-B2, OCM-C1, OCM-C2, OCM-D1, OCM-D2) and lies within the exposure field in question and comprises a plurality of control module field sections (A11, A12 . . . AIN and A21, A22 . . . A2N and B11, B12 . . . B1N and B21, B22 . . . B2N and C1N and C2N and D1N and D2N) and is distributed among several lattice grids (3), wherein each control module field section (A11 to D2N) is located in a lattice field and contains at least one control module component (10,11,12,13,14,15,16,17,18).
    Type: Application
    Filed: December 9, 2004
    Publication date: July 12, 2007
    Applicant: Koninklijke Philips Electronics N.V.
    Inventor: Heimo Scheucher
  • Wafer with optical control modules in exposure fields
    Patent number: 7538444
    Abstract: In a wafer (1) with a number of exposure fields (2), each of which exposure fields (2) comprising a number of lattice fields (3) with an IC (4) located therein, two groups (5, 7) of dicing paths (6, 8) are provided and four control module fields (A1, A2, A3, A4, B1, B2, B3, B4, C2, C4, D2, D4, E1, E3, F1, F3, G2, H1, J1) are assigned to each exposure field (2), each of which control module fields (A1, A2, A3, A4, B1, B2, B3, B4, C2, C4, D2, D4, E1, E3, F1, F3, G2, H1, J1) contains at least one optical control module (OCM-A1, OCMA2, OCM-A3, OCM-A4, OCM-B1, OCM-B2, OCM-B3, OCM-B4, OCM-C2, OCM-D4) and lies within the exposure field (2) in question and is provided in place of at least one lattice field (3) and is arranged at a mutual minimum distance (K).
    Type: Grant
    Filed: December 9, 2004
    Date of Patent: May 26, 2009
    Inventors: Heimo Scheucher, Guenther Pfeiler, Rik Wenting
  • Wafer with optical control modules in IC fields
    Patent number: 7456489
    Abstract: In a wafer (1) with a number of exposure fields (2), each of which exposure fields comprises a number of lattice fields (3) with an IC (4) located therein, two groups (5, 7) of saw paths (6, 8) are provided and two control module fields (A1, A2, B1, B2, C1, C2, D1, D2) are assigned to each exposure field, each of which control module fields contains at least one optical control module (OCM-A1, OCM-A2, OCM-B1, OCM-B2, OCM-C1, OCM-C2, OCM-D1, OCM-D2) and lies within the exposure field in question and comprises a plurality of control module field sections (A11, A12 . . . AIN and A21, A22 . . . A2N and B11, B12 . . . B1N and B21, B22 . . . B2N and C1N and C2N and D1N and D2N) and is distributed among several lattice grids (3), wherein each control module field section (A11 to D2N) is located in a lattice field and contains at least one control module component (10,11,12,13,14,15,16,17,18).
    Type: Grant
    Filed: December 9, 2004
    Date of Patent: November 25, 2008
    Assignee: NXP B.V.
    Inventor: Heimo Scheucher
  • Wafer with optical control modules in dicing paths
    Publication number: 20070111352
    Abstract: In a wafer (1) with a number of exposure fields (2), each of which exposure fields (2) comprises a number of lattice fields (3) with an IC (4) located therein, two groups (5, 7) of dicing paths (6, 8) are provided and two control module fields (A1, A2, B1, B2, C1, D1, D2, E1, E2, F1) are assigned to each exposure field (2), each of which control module fields extends parallel to a first direction (X) and contains at least one optical control module (OCM-A1, OCM-A2, OCM-B1, OCM-B2, OCM-C1, OCM-D1, OCM-D2, OCM-E1, OCME2, OCM-F1), wherein a first control module field (OCM-A1, OCM-B1, OCM-C1, OCMD1, OCM-E1, OCM-F1) of each exposure field (2) is located between a first edge (R1, S1, T1, U1, V1, Z1) and a row of lattice fields (3) of the exposure field (2) in question and a second control module field (OCM-A2, OCM-B2, OCM-D2, OCM-E2) is located between two rows of lattice fields (3) of the exposure field (2) in question, which are arranged adjacent to a second edge (R2, S1, U2, V2), and wherein both the first contr
    Type: Application
    Filed: December 9, 2004
    Publication date: May 17, 2007
    Applicant: KONINKLIJKE PHILIPS ELECTRONICS N.V.
    Inventor: Heimo Scheucher
  • Wafer with optical control modules in dicing paths
    Patent number: 7508051
    Abstract: In a wafer (1) with a number of exposure fields (2), each of which exposure fields (2) comprises a number of lattice fields (3) with an IC (4) located therein, two groups (5, 7) of dicing paths (6, 8) are provided and two control module fields (A1, A2, B1, B2, C1, D1, D2, E1, E2, F1) are assigned to each exposure field (2), each of which control module fields extends parallel to a first direction (X) and contains at least one optical control module (OCM-A1, OCM-A2, OCM-BI, OCM-B2, OCM-C1, OCM-D1, OCM-D2, OCM-E1, OCME2, OCM-F1), wherein a first control module field (OCM-A1, OCM-B1, OCM-C1, OCMD1, OCM-E1, OCM-F1) of each exposure field (2) is located between a first edge (R1, S1, T1, U1, V1, Z1) and a row of lattice fields (3) of the exposure field (2) in question and a second control module field (OCM-A2, OCM-B2, OCM-D2, OCM-E2) is located between two rows of lattice fields (3) of the exposure field (2) in question, which are arranged adjacent to a second edge (R2, S1, U2, V2), and wherein both the first contr
    Type: Grant
    Filed: December 9, 2004
    Date of Patent: March 24, 2009
    Assignee: NXP B.V.
    Inventor: Heimo Scheucher
Narrow Results

Filter by US Classification