Search Patents
  • Self-aligned gate endcap (SAGE) architectures without fin end gap
    Patent number: 11869889
    Abstract: Self-aligned gate endcap (SAGE) architectures without fin end gaps, and methods of fabricating self-aligned gate endcap (SAGE) architectures without fin end gaps, are described. In an example, an integrated circuit structure includes a semiconductor fin having a cut along a length of the semiconductor fin. A gate endcap isolation structure has a first portion parallel with the length of the semiconductor fin and is spaced apart from the semiconductor fin. The gate endcap isolation structure also has a second portion in a location of the cut of the semiconductor fin and in contact with the semiconductor fin.
    Type: Grant
    Filed: September 23, 2019
    Date of Patent: January 9, 2024
    Assignee: Intel Corporation
    Inventors: Szuya S. Liao, Scott B. Clendenning, Jessica Torres, Lukas Baumgartel, Kiran Chikkadi, Diane Lancaster, Matthew V. Metz, Florian Gstrein, Martin M. Mitan, Rami Hourani
  • Self-aligned gate endcap (SAGE) architecture having local interconnects
    Patent number: 11705453
    Abstract: Self-aligned gate endcap (SAGE) architectures having local interconnects, and methods of fabricating SAGE architectures having local interconnects, are described. In an example, an integrated circuit structure includes a first gate structure over a first semiconductor fin, and a second gate structure over a second semiconductor fin. A gate endcap isolation structure is between the first and second semiconductor fins and laterally between and in contact with the first and second gate structures. A gate plug is over the gate endcap isolation structure and laterally between and in contact with the first and second gate structures. A local gate interconnect is between the gate plug and the gate endcap isolation structure, the local gate interconnect in contact with the first and second gate structures.
    Type: Grant
    Filed: March 6, 2019
    Date of Patent: July 18, 2023
    Assignee: Intel Corporation
    Inventors: Sairam Subramanian, Walid M. Hafez, Sridhar Govindaraju, Kiran Chikkadi
  • SELF-ALIGNED GATE ENDCAP (SAGE) ARCHITECTURES WITH GATE-ALL-AROUND DEVICES
    Publication number: 20220102557
    Abstract: Self-aligned gate endcap (SAGE) architectures with gate-all-around devices, and methods of fabricating self-aligned gate endcap (SAGE) architectures with gate-all-around devices, are described. In an example, an integrated circuit structure includes a semiconductor fin above a substrate and having a length in a first direction. A nanowire is over the semiconductor fin. A gate structure is over the nanowire and the semiconductor fin, the gate structure having a first end opposite a second end in a second direction, orthogonal to the first direction. A pair of gate endcap isolation structures is included, where a first of the pair of gate endcap isolation structures is spaced equally from a first side of the semiconductor fin as a second of the pair of gate endcap isolation structures is spaced from a second side of the semiconductor fin.
    Type: Application
    Filed: December 13, 2021
    Publication date: March 31, 2022
    Inventors: Biswajeet GUHA, William HSU, Leonard P. GULER, Dax M. CRUM, Tahir GHANI
  • SELF-ALIGNED GATE ENDCAP (SAGE) ARCHITECTURES WITH GATE-ALL-AROUND DEVICES
    Publication number: 20190393352
    Abstract: Self-aligned gate endcap (SAGE) architectures with gate-all-around devices, and methods of fabricating self-aligned gate endcap (SAGE) architectures with gate-all-around devices, are described. In an example, an integrated circuit structure includes a semiconductor fin above a substrate and having a length in a first direction. A nanowire is over the semiconductor fin. A gate structure is over the nanowire and the semiconductor fin, the gate structure having a first end opposite a second end in a second direction, orthogonal to the first direction. A pair of gate endcap isolation structures is included, where a first of the pair of gate endcap isolation structures is spaced equally from a first side of the semiconductor fin as a second of the pair of gate endcap isolation structures is spaced from a second side of the semiconductor fin.
    Type: Application
    Filed: June 25, 2018
    Publication date: December 26, 2019
    Inventors: Biswajeet GUHA, William HSU, Leonard P. GULER, Dax M. CRUM, Tahir GHANI
  • SELF-ALIGNED GATE ENDCAP (SAGE) ARCHITECTURES WITH GATE-ALL-AROUND DEVICES
    Publication number: 20240030348
    Abstract: Self-aligned gate endcap (SAGE) architectures with gate-all-around devices, and methods of fabricating self-aligned gate endcap (SAGE) architectures with gate-all-around devices, are described. In an example, an integrated circuit structure includes a semiconductor fin above a substrate and having a length in a first direction. A nanowire is over the semiconductor fin. A gate structure is over the nanowire and the semiconductor fin, the gate structure having a first end opposite a second end in a second direction, orthogonal to the first direction. A pair of gate endcap isolation structures is included, where a first of the pair of gate endcap isolation structures is spaced equally from a first side of the semiconductor fin as a second of the pair of gate endcap isolation structures is spaced from a second side of the semiconductor fin.
    Type: Application
    Filed: September 29, 2023
    Publication date: January 25, 2024
    Inventors: Biswajeet GUHA, William HSU, Leonard P. GULER, Dax M. CRUM, Tahir GHANI
  • SELF-ALIGNED GATE ENDCAP (SAGE) ARCHITECTURES WITH GATE-ALL-AROUND DEVICES ABOVE INSULATOR SUBSTRATES
    Publication number: 20200219990
    Abstract: Self-aligned gate endcap (SAGE) architectures with gate-all-around devices above insulator substrates, and methods of fabricating self-aligned gate endcap (SAGE) architectures with gate-all-around devices above insulator substrates, are described. In an example, an integrated circuit structure includes includes a semiconductor nanowire above an insulator substrate and having a length in a first direction. A gate structure is around the semiconductor nanowire, the gate structure having a first end opposite a second end in a second direction, orthogonal to the first direction. A pair of gate endcap isolation structures is included. The first of the pair of gate endcap isolation structures is directly adjacent to the first end of the gate structure, and the second of the pair of gate endcap isolation structures is directly adjacent to the second end of the gate structure.
    Type: Application
    Filed: January 3, 2019
    Publication date: July 9, 2020
    Inventors: Biswajeet GUHA, Dax M. CRUM, Stephen M. CEA, Leonard P. GULER, Tahir GHANI
  • Use of extracts from sage for producing a deodorizing preparation
    Patent number: 6139825
    Abstract: A use of extracts from flowers and/or leaves of sage (Salvia officinalis) obtained by a CO.sub.2 extraction process for producing a deodorizing preparation e.g. a deodorant stick or a roll-on deodorant is described.
    Type: Grant
    Filed: November 17, 1999
    Date of Patent: October 31, 2000
    Assignee: Heilmittelbetreib Isernhagen GmbH
    Inventors: Max Reinhard, Jurgen Geissler
  • SMALL ANODE GERMANIUM (SAGe) WELL RADIATION DETECTOR SYSTEM AND METHOD
    Publication number: 20140264049
    Abstract: A small anode germanium well (SAGe well) radiation detector system/method providing for low capacitance, short signal leads, small area bottom-oriented signal contacts, enhanced performance independent of well diameter, and ability to determine radiation directionality is disclosed. The system incorporates a P-type bulk germanium volume (PGEV) having an internal well cavity void (IWCV). The external PGEV and IWCV surfaces incorporate an N+ electrode except for the PGEV external base region (EBR) in which a P+ contact electrode is fabricated within an isolation region. The PGEV structure is further encapsulated to permit operation at cryogenic temperatures. Electrical connection to the SAGe well is accomplished by bonding or mechanical contacting to the P+ contact electrode and the N+ electrode. The EBR of the PGEV may incorporate an integrated preamplifier inside the vacuum housing to minimize the noise and gain change due to ambient temperature variation.
    Type: Application
    Filed: March 15, 2013
    Publication date: September 18, 2014
    Inventor: Canberra Industries, Inc.
  • METHOD OF CONTROLLING LITHIUM UNIFORMITY
    Publication number: 20130015054
    Abstract: A method and apparatus for providing uniform coatings of lithium on a substrate are provided. In one aspect of the present invention is a method of selectively controlling the uniformity and/or rate of deposition of a metal or lithium in a sputter process by introducing a quantity of reactive gas over a specified area in the sputter chamber. This method is applicable to planar and rotating targets.
    Type: Application
    Filed: September 18, 2012
    Publication date: January 17, 2013
    Applicant: SAGE Electrochromics, Inc.
    Inventor: SAGE Electrochromics, Inc.
  • OXYSTEROLS AND METHODS OF USE THEREOF
    Publication number: 20190330259
    Abstract: Compounds are provided according to Formula (I), and pharmaceutically acceptable salts thereof, and pharmaceutical compositions thereof; wherein A, R1, and R5 are as defined herein. Compounds of the present invention are contemplated useful for the prevention and treatment of a variety of conditions.
    Type: Application
    Filed: March 31, 2017
    Publication date: October 31, 2019
    Applicants: Sage Therapeutics, Inc., Sage Therapeutics, Inc.
    Inventors: Albert Jean Robichaud, Francesco G. Salituro, Gabriel Martinez Botella, Boyd L. Harrison, John Gregory Reid
  • Self-aligned gate endcap (SAGE) architectures with gate-all-around devices
    Patent number: 11233152
    Abstract: Self-aligned gate endcap (SAGE) architectures with gate-all-around devices, and methods of fabricating self-aligned gate endcap (SAGE) architectures with gate-all-around devices, are described. In an example, an integrated circuit structure includes a semiconductor fin above a substrate and having a length in a first direction. A nanowire is over the semiconductor fin. A gate structure is over the nanowire and the semiconductor fin, the gate structure having a first end opposite a second end in a second direction, orthogonal to the first direction. A pair of gate endcap isolation structures is included, where a first of the pair of gate endcap isolation structures is spaced equally from a first side of the semiconductor fin as a second of the pair of gate endcap isolation structures is spaced from a second side of the semiconductor fin.
    Type: Grant
    Filed: June 25, 2018
    Date of Patent: January 25, 2022
    Assignee: Intel Corporation
    Inventors: Biswajeet Guha, William Hsu, Leonard P. Guler, Dax M. Crum, Tahir Ghani
  • Self-aligned gate endcap (SAGE) architectures with gate-all-around devices
    Patent number: 11855223
    Abstract: Self-aligned gate endcap (SAGE) architectures with gate-all-around devices, and methods of fabricating self-aligned gate endcap (SAGE) architectures with gate-all-around devices, are described. In an example, an integrated circuit structure includes a semiconductor fin above a substrate and having a length in a first direction. A nanowire is over the semiconductor fin. A gate structure is over the nanowire and the semiconductor fin, the gate structure having a first end opposite a second end in a second direction, orthogonal to the first direction. A pair of gate endcap isolation structures is included, where a first of the pair of gate endcap isolation structures is spaced equally from a first side of the semiconductor fin as a second of the pair of gate endcap isolation structures is spaced from a second side of the semiconductor fin.
    Type: Grant
    Filed: December 13, 2021
    Date of Patent: December 26, 2023
    Assignee: Intel Corporation
    Inventors: Biswajeet Guha, William Hsu, Leonard P. Guler, Dax M. Crum, Tahir Ghani
  • SELF-ALIGNED GATE ENDCAP (SAGE) ARCHITECTURE HAVING ENDCAP PLUGS
    Publication number: 20190305111
    Abstract: Self-aligned gate endcap (SAGE) architectures having gate endcap plugs or contact endcap plugs, or both gate endcap plugs and contact endcap plugs, and methods of fabricating SAGE architectures having such endcap plugs, are described. In an example, a first gate structure is over a first of a plurality of semiconductor fins. A second gate structure is over a second of the plurality of semiconductor fins. A first gate endcap isolation structure is laterally between and in contact with the first gate structure and the second gate structure and has an uppermost surface co-planar with an uppermost surface of the first gate structure and the second gate structure. A second gate endcap isolation structure is laterally between and in contact with first and second lateral portions of the first gate structure and has an uppermost surface below an uppermost surface of the first gate structure.
    Type: Application
    Filed: April 2, 2018
    Publication date: October 3, 2019
    Inventors: Sairam SUBRAMANIAN, Christopher KENYON, Sridhar GOVINDARAJU, Chia-Hong JAN, Mark LIU, Szuya S. LIAO, Walid M. HAFEZ
  • Aryl or heteroaryl quinolylphosphonic acid compounds
    Patent number: 6420386
    Abstract: The invention relates to a compound of formula (I): wherein: R1 represents halogen or a group CF3, R2 represents aryl or heteroaryl, R3 and R4 are as defined in the description and methods for using the same.
    Type: Grant
    Filed: February 14, 2001
    Date of Patent: July 16, 2002
    Assignee: Les Laboratories Servier
    Inventors: Alex Cordi, Patrice Desos, Pierre Lestage
  • MOTION CONSTRAINT-AIDED UNDERWATER INTEGRATED NAVIGATION METHOD EMPLOYING IMPROVED SAGE-HUSA ADAPTIVE FILTERING
    Publication number: 20220404152
    Abstract: A motion constraint-aided underwater integrated navigation method employing improved Sage-Husa adaptive filtering includes establishing a Doppler log error model; constructing a state equation for an underwater integrated navigation system employing Kalman filtering; according to a relationship between a centripetal acceleration and a forward velocity of an underwater vehicle, establishing a constraint condition, and constructing a complete motion constraint model; establishing two measurement equations; and establishing a filter equation, conducting calculation by using a standard Kalman filtering algorithm when an underwater glider normally runs, and conducting time updating, measurement updating and filtering updating by using an improved Sage-Husa adaptive filtering algorithm when a measurement noise varies.
    Type: Application
    Filed: July 28, 2021
    Publication date: December 22, 2022
    Applicant: SOUTHEAST UNIVERSITY
    Inventors: Xiyuan CHEN, Siyi ZHANG, Xiaotian ZHANG, Junwei WANG
  • Motion constraint-aided underwater integrated navigation method employing improved Sage-Husa adaptive filtering
    Patent number: 11754400
    Abstract: A motion constraint-aided underwater integrated navigation method employing improved Sage-Husa adaptive filtering includes establishing a Doppler log error model; constructing a state equation for an underwater integrated navigation system employing Kalman filtering; according to a relationship between a centripetal acceleration and a forward velocity of an underwater vehicle, establishing a constraint condition, and constructing a complete motion constraint model; establishing two measurement equations; and establishing a filter equation, conducting calculation by using a standard Kalman filtering algorithm when an underwater glider normally runs, and conducting time updating, measurement updating and filtering updating by using an improved Sage-Husa adaptive filtering algorithm when a measurement noise varies.
    Type: Grant
    Filed: July 28, 2021
    Date of Patent: September 12, 2023
    Assignee: SOUTHEAST UNIVERSITY
    Inventors: Xiyuan Chen, Siyi Zhang, Xiaotian Zhang, Junwei Wang
  • Process for the preparation of isoindoline
    Patent number: 6320058
    Abstract: Process for the industrial synthesis of isoindoline by catalytic hydrogenation of phthalonitrile, and its application in the synthesis of 2-(S)-benzyl-4-oxo-4-(cis-perhydroisoindol-2-yl)-butyric acid, its pharmaceutically acceptable salts and its hydrates.
    Type: Grant
    Filed: February 16, 2001
    Date of Patent: November 20, 2001
    Assignee: Adir et Compagnie
    Inventors: Jean-Claude Souvie, Claude Fugier, Jean-Pierre Lecouve
  • Self-aligned gate endcap (SAGE) architecture having endcap plugs
    Patent number: 11329138
    Abstract: Self-aligned gate endcap (SAGE) architectures having gate endcap plugs or contact endcap plugs, or both gate endcap plugs and contact endcap plugs, and methods of fabricating SAGE architectures having such endcap plugs, are described. In an example, a first gate structure is over a first of a plurality of semiconductor fins. A second gate structure is over a second of the plurality of semiconductor fins. A first gate endcap isolation structure is laterally between and in contact with the first gate structure and the second gate structure and has an uppermost surface co-planar with an uppermost surface of the first gate structure and the second gate structure. A second gate endcap isolation structure is laterally between and in contact with first and second lateral portions of the first gate structure and has an uppermost surface below an uppermost surface of the first gate structure.
    Type: Grant
    Filed: April 2, 2018
    Date of Patent: May 10, 2022
    Assignee: Intel Corporation
    Inventors: Sairam Subramanian, Christopher Kenyon, Sridhar Govindaraju, Chia-Hong Jan, Mark Liu, Szuya S. Liao, Walid M. Hafez
  • Solid thermoformable controlled-release pharmaceutical composition
    Patent number: 6319520
    Abstract: The present invention relates to a new solid controlled-release pharmaceutical composition obtained by thermoforming, in the hot state, a mixture based on polymers belonging to the polymethacrylate family and medicinal active ingredient(s).
    Type: Grant
    Filed: June 27, 2000
    Date of Patent: November 20, 2001
    Assignee: Adir et Compagnie
    Inventors: Patrick Wuthrich, Hervé Rolland, Gilles Briault, Gérald Pichon, François Tharrault
  • Small anode germanium (SAGe) well radiation detector system and method
    Patent number: 9269847
    Abstract: A small anode germanium well (SAGe well) radiation detector system/method providing for low capacitance, short signal leads, small area bottom-oriented signal contacts, enhanced performance independent of well diameter, and ability to determine radiation directionality is disclosed. The system incorporates a P-type bulk germanium volume (PGEV) having an internal well cavity void (IWCV). The external PGEV and IWCV surfaces incorporate an N+ electrode except for the PGEV external base region (EBR) in which a P+ contact electrode is fabricated within an isolation region. The PGEV structure is further encapsulated to permit operation at cryogenic temperatures. Electrical connection to the SAGe well is accomplished by bonding or mechanical contacting to the P+ contact electrode and the N+ electrode. The EBR of the PGEV may incorporate an integrated preamplifier inside the vacuum housing to minimize the noise and gain change due to ambient temperature variation.
    Type: Grant
    Filed: March 15, 2013
    Date of Patent: February 23, 2016
    Assignee: CANBERRA INDUSTRIES, INC.
    Inventors: Kenneth Michael Yocum, James F. Colaresi, Orren K. Tench
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