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  • Method and apparatus for efficient computation of moments in interconnect circuits
    Patent number: 6662149
    Abstract: A process for efficiently computing moments in an interconnected circuit begins by partitioning the circuit into sets of line-like two-port circuits. Next, capacitors are converted to equivalent current sources and inductors are converted to equivalent voltage sources. From a first port, any connected voltage source which is present in line is added to the port voltage source. Then, that voltage source combined with the connected resistor and the Thevenin equivalent circuit is converted to a Norton equivalent circuit. The current source created from the conversion is added to a current source in the circuit and the Norton equivalent circuit is converted back to a Thevenin equivalent circuit. The process is recursively performed until the opposite port is reached. The moment is then computed from the final Thevenin equivalent circuit by using the voltage and current at the port. The Thevenin-Norton-Thevenin recursive process is then repeated for the opposite port.
    Type: Grant
    Filed: May 27, 1999
    Date of Patent: December 9, 2003
    Assignee: International Business Machines Corporation
    Inventors: Anirudh Devgan, Peter Redmond O'Brien
  • Ring oscillator row circuit for evaluating memory cell performance
    Patent number: 7483322
    Abstract: A ring oscillator row circuit for evaluating memory cell performance provides for circuit delay and performance measurements in an actual memory circuit environment. A ring oscillator is implemented with a row of memory cells and has outputs connected to one or more bitlines along with other memory cells that are substantially identical to the ring oscillator cells. Logic may be included for providing a fully functional memory array, so that the cells other than the ring oscillator cells can be used for storage when the ring oscillator row wordlines are disabled. One or both power supply rails of individual cross-coupled inverter stages forming static memory cells used in the ring oscillator circuit may be isolated from each other in order to introduce a voltage asymmetry so that circuit asymmetry effects on delay can be evaluated.
    Type: Grant
    Filed: December 22, 2007
    Date of Patent: January 27, 2009
    Assignee: International Business Machines Corporation
    Inventors: Rajiv V. Joshi, Qiuyi Ye, Yuen H. Chan, Anirudh Devgan
  • Method and system for segmenting wires prior to buffer insertion
    Patent number: 6044209
    Abstract: A method and system for segmenting wires in the design stage of a integrated circuit to allow for the efficient insertion of an optimum quantity of buffers. The method begins by locating wires in the integrated circuit which interconnect transistors and then determining the characteristics of the transistor and the characteristics of the interconnecting wires. Next, the method computes a first upper limit for an optimum quantity of buffers utilizing total capacitive load wire and transistor characteristics, then the method computes a second upper limit for an optimum quantity of buffers assuming buffer insertion has decoupled the capacitive load. Finally, the method segments the wires by inserting nodes utilizing the greater of the first computation or the second computation. A determined upper limit on buffer quantity allows wires to be segmented such that the number of candidate buffer insertion topologies is manageable.
    Type: Grant
    Filed: September 15, 1997
    Date of Patent: March 28, 2000
    Assignee: International Business Machines Corporation
    Inventors: Charles Jay Alpert, Stephen Thomas Quay, Anirudh Devgan
  • Internally asymmetric methods and circuits for evaluating static memory cell dynamic stability
    Patent number: 7301835
    Abstract: Internally asymmetric methods and circuits for evaluating static memory cell dynamic stability provide a mechanism for raising the performance of memory arrays beyond present levels/yields. By altering the internal symmetry of a static random access memory (SRAM) memory cell, operating the cell and observing changes in performance caused by the asymmetric operation, the dynamic stability of the SRAM cell can be studied over designs and operating environments. The asymmetry can be introduced by splitting one or both power supply rail inputs to the cell and providing differing power supply voltages or currents to each cross-coupled stage. Alternatively or in combination, the loading at the outputs of the cell can altered in order to affect the performance of the cell. A memory array with at least one test cell can be fabricated in a production or test wafer and internal nodes of the memory cell can be probed to provide further information.
    Type: Grant
    Filed: September 13, 2005
    Date of Patent: November 27, 2007
    Assignee: International Business Machines Corporation
    Inventors: Rajiv V. Joshi, Qiuyi Ye, Anirudh Devgan
  • Method and system for extending delay and slew metrics to ramp inputs
    Publication number: 20040103379
    Abstract: A method of determining a circuit response (such as delay or slew) from a ramp input of an RC circuit calculates two circuit response parameters using a given circuit response metric based on a step input for the RC circuit, and extends the circuit response metric to a ramp input of the RC circuit by combining the first and second circuit response parameters to yield an estimated ramp response. The novel technique is based on the use of probability distribution functions and cumulative distribution functions to characterize the impulse response of the RC circuit, and the calculating steps derive the first and second circuit response parameters from such statistical distribution functions. In particular, the calculating steps may use a standard deviation or a mean of a probability distribution function corresponding to the circuit response parameter. In one application, the invention is used to estimate delay response for the ramp input of the RC circuit.
    Type: Application
    Filed: November 26, 2002
    Publication date: May 27, 2004
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Charles Jay Alpert, Anirudh Devgan, Chandramouli V. Kashyap, Ying Liu
  • Efficient method and computer program for modeling and improving static memory performance across process variations and environmental conditions
    Patent number: 8001493
    Abstract: An efficient method and computer program for modeling and improving stating memory performance across process variations and environmental conditions provides a mechanism for raising the performance of memory arrays beyond present levels/yields. Statistical (Monte-Carlo) analyses of subsets of circuit parameters are performed for each of several memory performance variables and then sensitivities of each performance variable to each of the circuit parameters are determined. The memory cell design parameters and/or operating conditions of the memory cells are then adjusted in conformity with the sensitivities, resulting in improved memory yield and/or performance. Once a performance level is attained, the sensitivities can then be used to alter the probability distributions of the performance variables to achieve a higher yield.
    Type: Grant
    Filed: August 27, 2008
    Date of Patent: August 16, 2011
    Assignee: International Business Machines
    Inventors: Rajiv V. Joshi, Anirudh Devgan
  • Method and system for extending delay and slew metrics to ramp inputs
    Patent number: 6868533
    Abstract: A method of determining a circuit response (such as delay or slew) from a ramp input of an RC circuit calculates two circuit response parameters using a given circuit response metric based on a step input for the RC circuit, and extends the circuit response metric to a ramp input of the RC circuit by combining the first and second circuit response parameters to yield an estimated ramp response. The novel technique is based on the use of probability distribution functions and cumulative distribution functions to characterize the impulse response of the RC circuit, and the calculating steps derive the first and second circuit response parameters from such statistical distribution functions. In particular, the calculating steps may use a standard deviation or a mean of a probability distribution function corresponding to the circuit response parameter. In one application, the invention is used to estimate delay response for the ramp input of the RC circuit.
    Type: Grant
    Filed: November 26, 2002
    Date of Patent: March 15, 2005
    Assignee: International Business Machines Corporation
    Inventors: Charles Jay Alpert, Anirudh Devgan, Chandramouli V. Kashyap, Ying Liu
  • Interconnect delay and slew metrics based on the lognormal distribution
    Publication number: 20040243955
    Abstract: A method of determining a circuit response (such as delay or slew) from a ramp input of an RC circuit calculates two circuit response parameters using a given circuit response metric based on a step input for the RC circuit, and extends the circuit response metric to a ramp input of the RC circuit by combining the first and second circuit response parameters to yield an estimated ramp response. The novel technique is based on the use of probability distribution functions and cumulative distribution functions to characterize the impulse response of the RC circuit, and the calculating steps derive the first and second circuit response parameters from such statistical distribution functions. In particular, the calculating steps may use a standard deviation or a mean of a probability distribution function corresponding to the circuit response parameter. In one application, the invention is used to estimate delay response for the ramp input of the RC circuit.
    Type: Application
    Filed: May 29, 2003
    Publication date: December 2, 2004
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Charles Jay Alpert, Anirudh Devgan, Chandramouli V. Kashyap, Ying Liu
  • Interconnect delay and slew metrics based on the lognormal distribution
    Patent number: 6950996
    Abstract: A method of determining a circuit response (such as delay or slew) from a ramp input of an RC circuit calculates two circuit response parameters using a given circuit response metric based on a step input for the RC circuit, and extends the circuit response metric to a ramp input of the RC circuit by combining the first and second circuit response parameters to yield an estimated ramp response. The novel technique is based on the use of probability distribution functions and cumulative distribution functions to characterize the impulse response of the RC circuit, and the calculating steps derive the first and second circuit response parameters from such statistical distribution functions. In particular, the calculating steps may use a standard deviation or a mean of a probability distribution function corresponding to the circuit response parameter. In one application, the invention is used to estimate delay response for the ramp input of the RC circuit.
    Type: Grant
    Filed: May 29, 2003
    Date of Patent: September 27, 2005
    Assignee: International Business Machines Corporation
    Inventors: Charles Jay Alpert, Anirudh Devgan, Chandramouli V. Kashyap, Ying Liu
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