Search Patents
  • MEMORY DEVICE WITH NEGATIVE THRESHOLDS
    Publication number: 20100195390
    Abstract: A method for data storage in a memory that includes a plurality of analog memory cells includes storing data in the memory by writing first storage values to the cells. One or more read reference levels are defined for reading the cells, such that at least one of the read reference levels is negative. After storing the data, second storage values are read from the cells using the read reference levels, so as to reconstruct the stored data. In another disclosed method, data is stored in the memory by mapping the data to first storage values selected from a set of the nominal storage values, and writing the first storage values to the cells. The set of nominal storage values is defined such that at least one of the nominal storage values is negative.
    Type: Application
    Filed: April 12, 2010
    Publication date: August 5, 2010
    Applicant: ANOBIT TECHNOLOGIES LTD
    Inventor: Ofir Shalvi
  • Memory device programming using combined shaping and linear spreading
    Patent number: 7466575
    Abstract: A method for data storage includes accepting data for storage in a memory (28) that includes multiple analog memory cells (32). The data is converted to input values. The input values are filtered using a non-linear filtering operation to produce respective shaped values, and the shaped values are converted to output values using a linear spreading transformation with coefficients chosen so that each of the shaped values contributes to at least two of the output values. The non-linear filtering operation is selected so as to reduce a size of an output range in which the output values lie. The output values are stored in the respective analog memory cells.
    Type: Grant
    Filed: May 10, 2007
    Date of Patent: December 16, 2008
    Assignee: Anobit Technologies Ltd.
    Inventors: Ofir Shalvi, Naftali Sommer
  • Distortion Estimation And Cancellation In Memory Devices
    Publication number: 20080198650
    Abstract: A method for operating a memory (28) includes storing data in a group of analog memory cells (32) of the memory as respective first voltage levels. After storing the data, second voltage levels are read from the respective analog memory cells. The second voltage levels are affected by cross-coupling interference causing the second voltage levels to differ from the respective first voltage levels. Cross-coupling coefficients, which quantify the cross-coupling interference among the analog memory cells, are estimated by processing the second voltage levels. The data stored in the group of analog memory cells is reconstructed from the read second voltage levels using the estimated cross-coupling coefficients.
    Type: Application
    Filed: May 10, 2007
    Publication date: August 21, 2008
    Applicant: Anobit Technologies Ltd.
    Inventors: Ofir Shalvi, Naftali Sommer, Eyal Gurgi, Ariel Maislos
  • Memory device with reduced reading latency
    Patent number: 7593263
    Abstract: A method for data storage includes providing a memory, which includes first memory cells having a first reading latency and second memory cells having a second reading latency that is higher than the first reading latency. An item of data intended for storage in the memory is divided into first and second parts. The first part is stored in the first memory cells and the second part is stored in the second memory cells. In response to a request to retrieve the item of data from the memory, the first part is read from the first memory cells and provided as output. The second part is read from the second memory cells, and provided as output subsequently to outputting the first part.
    Type: Grant
    Filed: December 17, 2007
    Date of Patent: September 22, 2009
    Assignee: Anobit Technologies Ltd.
    Inventors: Dotan Sokolov, Gil Semo, Ofir Shalvi
  • Memory cell readout using successive approximation
    Patent number: 7821826
    Abstract: A method for operating a memory (20) includes storing analog values in an array of analog memory cells (22), so that each of the analog memory cells holds an analog value corresponding to at least first and second respective bits. A first indication of the analog value stored in a given analog memory cell is obtained using a first set of sampling parameters. A second indication of the analog value stored in the given analog memory cell is obtained using a second set of sampling parameters, which is dependent upon the first indication. The first and second respective bits are read out from the given analog memory cell responsively to the first and second indications.
    Type: Grant
    Filed: October 30, 2007
    Date of Patent: October 26, 2010
    Assignee: Anobit Technologies, Ltd.
    Inventors: Ofir Shalvi, Naftali Sommer
  • Reducing Distortion Using Joint Storage
    Publication number: 20120163080
    Abstract: A method for data storage includes predefining an order of programming a plurality of analog memory cells that are arranged in rows. The order specifies that for a given row having neighboring rows on first and second sides, the memory cells in the given row are programmed only while the memory cells in the neighboring rows on at least one of the sides are in an erased state, and that the memory cells in the given row are programmed to assume a highest programming level, which corresponds to a largest analog value among the programming levels of the cells, only after programming all the memory cells in the given row to assume the programming levels other than the highest level. Data is stored in the memory cells by programming the memory cells in accordance with the predefined order.
    Type: Application
    Filed: March 6, 2012
    Publication date: June 28, 2012
    Applicant: ANOBIT TECHNOLOGIES LTD
    Inventors: Ofir Shalvi, Eyal Gurgi, Uri Perlmutter, Oren Golov
  • Reliable data storage in analog memory cells in the presence of temperature variations
    Patent number: 7773413
    Abstract: A method for data storage includes programming a first group of analog memory cells at a first time at a known first temperature, so as to cause the analog memory cells in the first group to assume respective first analog storage values. Respective second analog storage values are read from the analog memory cells in the first group at a second time at which the analog memory cells are at a second temperature. A shift is estimated between the first analog storage values and the second analog storage values, and a memory access parameter is adjusted responsively to the estimated shift. A second group of the analog memory cells is accessed at the second temperature using the adjusted memory access parameter.
    Type: Grant
    Filed: October 5, 2008
    Date of Patent: August 10, 2010
    Assignee: Anobit Technologies Ltd.
    Inventor: Ofir Shalvi
  • Use of Host System Resources by Memory Controller
    Publication number: 20100250836
    Abstract: A method for data storage includes, in a system that includes a host having a host memory and a memory controller that is separate from the host and stores data for the host in a non-volatile memory including multiple analog memory cells, storing in the host memory information items relating to respective groups of the analog memory cells of the non-volatile memory. A command that causes the memory controller to access a given group of the analog memory cells is received from the host. In response to the command, a respective information item relating to the given group of the analog memory cells is retrieved from the host memory by the memory controller, and the given group of the analog memory cells is accessed using the retrieved information item.
    Type: Application
    Filed: March 22, 2010
    Publication date: September 30, 2010
    Applicant: ANOBIT TECHNOLOGIES LTD
    Inventors: Dotan Sokolov, Barak Rotbard
  • REDUCING PROGRAMMING ERROR IN MEMORY DEVICES
    Publication number: 20090103358
    Abstract: A method for storing data in an array (28) of analog memory cells (32) includes defining a constellation of voltage levels (90A, 90B, 90C, 90D) to be used in storing the data. A part of the data is written to a first analog memory cell in the array by applying to the analog memory cell a first voltage level selected from the constellation. After writing the part of the data to the first analog memory cell, a second voltage level that does not belong to the constellation is read from the first analog memory cell. A modification to be made in writing to one or more of the analog memory cells in the array is determined responsively to the second voltage level, and data are written to the one or more of the analog memory cells subject to the modification.
    Type: Application
    Filed: May 10, 2007
    Publication date: April 23, 2009
    Applicant: Anobit Technologies Ltd.
    Inventors: Naftali Sommer, Ofir Shalvi
  • Programming of analog memory cells using a single programming pulse per state transition
    Patent number: 7924587
    Abstract: A method for data storage in analog memory cells includes defining multiple programming states for storing data in the analog memory cells. The programming states represent respective combinations of more than one bit and correspond to respective, different levels of a physical quantity stored in the memory cells. The data is stored in the memory cells by applying to the memory cells programming pulses that cause the levels of the physical quantity stored in the memory cells to transition between the programming states, such that a given transition is caused by only a single programming pulse.
    Type: Grant
    Filed: February 19, 2009
    Date of Patent: April 12, 2011
    Assignee: Anobit Technologies Ltd.
    Inventors: Uri Perlmutter, Shai Winter, Ofir Shalvi, Eyal Gurgi, Naftali Sommer, Oren Golov
  • Programming Orders for Reducing Distortion Based on Neighboring Rows
    Publication number: 20120163079
    Abstract: A method for data storage includes predefining an order of programming a plurality of analog memory cells that are arranged in rows. The order specifies that for a given row having neighboring rows on first and second sides, the memory cells in the given row are programmed only while the memory cells in the neighboring rows on at least one of the sides are in an erased state, and that the memory cells in the given row are programmed to assume a highest programming level, which corresponds to a largest analog value among the programming levels of the cells, only after programming all the memory cells in the given row to assume the programming levels other than the highest level. Data is stored in the memory cells by programming the memory cells in accordance with the predefined order.
    Type: Application
    Filed: March 6, 2012
    Publication date: June 28, 2012
    Applicant: ANOBIT TECHNOLOGIES LTD
    Inventors: Ofir Shalvi, Eyal Gurgi, Uri Perlmutter, Oren Golov
  • Memory device with negative thresholds
    Patent number: 7751240
    Abstract: A method for data storage in a memory that includes a plurality of analog memory cells includes storing data in the memory by writing first storage values to the cells. One or more read reference levels are defined for reading the cells, such that at least one of the read reference levels is negative. After storing the data, second storage values are read from the cells using the read reference levels, so as to reconstruct the stored data. In another disclosed method, data is stored in the memory by mapping the data to first storage values selected from a set of the nominal storage values, and writing the first storage values to the cells. The set of nominal storage values is defined such that at least one of the nominal storage values is negative.
    Type: Grant
    Filed: January 24, 2008
    Date of Patent: July 6, 2010
    Assignee: Anobit Technologies Ltd.
    Inventor: Ofir Shalvi
  • Parameter estimation based on error correction code parity check equations
    Patent number: 8156398
    Abstract: A method for operating a memory, which includes analog memory cells, includes encoding data with an Error Correction Code (ECC) that is representable by a plurality of equations. The encoded data is stored in a group of the analog memory cells by writing respective input storage values to the memory cells in the group. Multiple sets of output storage values are read from the memory cells in the group using one or more different, respective read parameters for each set. Numbers of the equations, which are satisfied by the respective sets of the output storage values, are determined. A preferred setting of the read parameters is identified responsively to the respective numbers of the satisfied equations. The memory is operated on using the preferred setting of the read parameters.
    Type: Grant
    Filed: February 3, 2009
    Date of Patent: April 10, 2012
    Assignee: Anobit Technologies Ltd.
    Inventor: Naftali Sommer
  • Memory device with multiple-accuracy read commands
    Patent number: 8059457
    Abstract: A method for data storage includes defining at least first and second read commands for reading storage values from analog memory cells. The first read command reads the storage values at a first accuracy, and the second read command reads the storage values at a second accuracy, which is finer than the first accuracy. A condition is evaluated with respect to a read operation that is to be performed over a given group of the memory cells. One of the first and second read commands is selected responsively to the evaluated condition. The storage values are read from the given group of the memory cells using the selected read command.
    Type: Grant
    Filed: March 17, 2009
    Date of Patent: November 15, 2011
    Assignee: Anobit Technologies Ltd.
    Inventors: Uri Perlmutter, Ofir Shalvi, Yoav Kasorla, Naftali Sommer, Dotan Sokolov
  • Command interface for memory devices
    Patent number: 8001320
    Abstract: A method for operating a memory device that includes a plurality of analog memory cells includes accepting at an input of the memory device a self-contained command to perform a memory access operation on at least one of the memory cells. The command includes an instruction specifying the memory access operation and one or more parameters that are indicative of analog settings to be applied to the at least one of the memory cells when performing the memory access operation. The self-contained command is executed in the memory device by extracting the parameters, applying the analog settings to the at least one of the memory cells responsively to the extracted parameters, and performing the specified memory access operation in accordance with the instruction on the at least one of the memory cells using the settings.
    Type: Grant
    Filed: March 10, 2008
    Date of Patent: August 16, 2011
    Assignee: Anobit Technologies Ltd.
    Inventors: Dotan Sokolov, Naftali Sommer
  • PROGRAMMING ORDERS FOR REDUCING DISTORTION IN ARRAYS OF MULTI-LEVEL ANALOG MEMORY CELLS
    Publication number: 20100157675
    Abstract: A method for data storage includes predefining an order of programming a plurality of analog memory cells that are arranged in rows. The order specifies that for a given row having neighboring rows on first and second sides, the memory cells in the given row are programmed only while the memory cells in the neighboring rows on at least one of the sides are in an erased state, and that the memory cells in the given row are programmed to assume a highest programming level, which corresponds to a largest analog value among the programming levels of the cells, only after programming all the memory cells in the given row to assume the programming levels other than the highest level. Data is stored in the memory cells by programming the memory cells in accordance with the predefined order.
    Type: Application
    Filed: March 11, 2010
    Publication date: June 24, 2010
    Applicant: ANOBIT TECHNOLOGIES LTD
    Inventors: Ofir Shalvi, Eyal Gurgi, Uri Perlmutter, Oren Golov
  • CHIEN SEARCH USING MULTIPLE BASIS REPRESENTATION
    Publication number: 20100332955
    Abstract: A method for decoding an Error Correction Code (ECC) includes accepting coefficients, including at least first and second coefficients, of an Error Locator Polynomial (ELP) that is defined over a vector space and has at least one root that is indicative of a location of an error in a set of bits, which represent data that has been encoded with the ECC. The first coefficient is represented using a first basis of the vector space, and the second coefficient is represented using a second basis of the vector space, different from the first basis. Using processing circuitry, the root of the ELP is identified by applying algebraic operations to the coefficients, such that the algebraic operations are applied to the first coefficient using the first basis, and to the second coefficient using the second basis. The error is corrected responsively to the identified root of the ELP.
    Type: Application
    Filed: June 10, 2010
    Publication date: December 30, 2010
    Applicant: ANOBIT TECHNOLOGIES LTD.
    Inventor: Micha Anholt
  • AUTOMATIC DEFECT MANAGEMENT IN MEMORY DEVICES
    Publication number: 20100115376
    Abstract: A method for storing data in a memory (28) that includes analog memory cells (32) includes identifying one or more defective memory cells in a group of the analog memory cells. An Error Correction Code (ECC) is selected responsively to a characteristic of the identified defective memory cells. The data is encoded using the selected ECC and the encoded data is stored in the group of the analog memory cells. In an alternative method, an identification of one or more defective memory cells among the analog memory cells is generated. Analog values are read from the analog memory cells in which the encoded data were stored, including at least one of the defective memory cells. The analog values are processed using an ECC decoding process responsively to the identification of the at least one of the defective memory cells, so as to reconstruct the data.
    Type: Application
    Filed: December 3, 2007
    Publication date: May 6, 2010
    Applicant: Anobit Technologies Ltd.
    Inventors: Ofir Shalvi, Dotan Sokolov
  • Reducing programming error in memory devices
    Patent number: 7697326
    Abstract: A method for storing data in an array (28) of analog memory cells (32) includes defining a constellation of voltage levels (90A, 90B, 90C, 90D) to be used in storing the data. A part of the data is written to a first analog memory cell in the array by applying to the analog memory cell a first voltage level selected from the constellation. After writing the part of the data to the first analog memory cell, a second voltage level that does not belong to the constellation is read from the first analog memory cell. A modification to be made in writing to one or more of the analog memory cells in the array is determined responsively to the second voltage level, and data are written to the one or more of the analog memory cells subject to the modification.
    Type: Grant
    Filed: May 10, 2007
    Date of Patent: April 13, 2010
    Assignee: Anobit Technologies Ltd.
    Inventors: Naftali Sommer, Ofir Shalvi
  • ERROR CORRECTION CODES FOR INCREMENTAL REDUNDANCY
    Publication number: 20120221913
    Abstract: A method includes accepting input including at least part of a codeword that has been encoded by an ECC defined by a set of parity check equations. The codeword includes data bits and parity bits. A decoding process is applied to the codeword using the data bits and only a first partial subset of parity bits in the input, and using only a second partial subset of equations. Upon a failure to decode the codeword using the partial subsets, the codeword is re-decoded using the data bits and all parity bits in the input, and using all equations. The set of parity check equations is defined such that any parity bit in the codeword appears in multiple equations, and any parity bit in the first partial subset of the parity bits appears in a plurality of equations in the second partial subset of the equations.
    Type: Application
    Filed: February 26, 2012
    Publication date: August 30, 2012
    Applicant: ANOBIT TECHNOLOGIES LTD.
    Inventors: Micha Anholt, Naftali Sommer
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