Search Patents
  • Ultrasonic loading control for centrifuge basket
    Patent number: 5900156
    Abstract: A loading control system for a centrifuge used in, for example, a sugar refining operation, optimizes the introduction of product to be centrifuged. A loading system has an ultrasonic loading probe, a sound tube for delivering the sound signals to the sugar wall and returning to the ultrasonic probe, an analog controllable feed valve and a programmable logic controller which is used to control the operation. The logic program implements a control loop which analyses the signal from the probe and controls the position of the gate accordingly. Preferably, the system also implements a control loop for automatic adjustment of the flow rate and amount of sugar in the machine in order to optimize the loading process.
    Type: Grant
    Filed: June 4, 1997
    Date of Patent: May 4, 1999
    Assignee: Savannah Foods and Industries
    Inventor: Dwayne Zeigler
  • Display device and driving method
    Patent number: 6107983
    Abstract: A display device comprises a display panel, a scanning circuit section for supplying a scanning signal to scanning lines of the display panel, and a scanning control circuit section for supplying an n-bit (n: 2 or more positive integer) input numeral signal and an inverted replica of the input numeral signal to the scanning circuit section. In the display device, a scanning circuit section comprises an input connection line group having sets of input connection lines for receiving bits of the input numeral signal and bits of the inverted replica of the input numeral signal, a plurality of logic circuit sections, less in number than the scanning lines, for responding to combinations of the input numeral signal and its inverted replica, and an output distributing unit for assigning an output from one logic circuit section to at least two scanning lines.
    Type: Grant
    Filed: March 13, 1998
    Date of Patent: August 22, 2000
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Youichi Masuda, Nozomu Harada, Hiroki Nakamura
  • Method for producing semiconductor device
    Patent number: 5650354
    Abstract: A multi-channel type intelligent power IC which solves the problems of parasitic transistor and increase in an area of isolation region, both of which are inherent problem in a pn junction isolation substrate. The power IC also enhances heat-radiation performance. An n type first semiconductor substrate and p type second semiconductor substrate are directly bonded, and a buried oxide film is formed in a portion of a bonding interface thereof. Subsequently, a plurality of isolation trenches are formed and the first semiconductor substrate is separated into an SOI isolation region and a pn isolation region. Logic elements are then formed in the SOI isolation region, and power elements are formed in the pn isolation region. In the case wherein two or more logic elements are hereby formed, the logic elements are isolated by isolation trenches. In the case wherein two or more power elements are formed, a parasitic current extracting portion is formed between mutual power elements.
    Type: Grant
    Filed: March 20, 1996
    Date of Patent: July 22, 1997
    Assignee: Nippondenso Co., Ltd.
    Inventors: Hiroaki Himi, Harutsugu Fukumoto, Seiji Fujino
  • Display device and its driving method
    Patent number: 5801672
    Abstract: A display device comprises a display panel, a scanning circuit section for supplying a scanning signal to scanning lines of the display panel, and a scanning control circuit section for supplying an n-bit (n: 2 or more positive integer) input numeral signal and an inverted replica of the input numeral signal to the scanning circuit section. In the display device, a scanning circuit section comprises an input connection line group having sets of input connection lines for receiving bits of the input numeral signal and bits of the inverted replica of the input numeral signal, a plurality of logic circuit sections, less in number than the scanning lines, for responding to combinations of the input numeral signal and its inverted replica, and an output distributing unit for assigning an output from one logic circuit section to at least two scanning lines.
    Type: Grant
    Filed: May 8, 1995
    Date of Patent: September 1, 1998
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Youichi Masuda, Nozomu Harada, Hiroki Nakamura
  • Data decoding apparatus and method and recording medium
    Patent number: 5757296
    Abstract: Even if an element such as a ROM is not used, a code reverse conversion can be realized by a sufficiently small scale circuit to be effective for integration. When code data group converted from 8-bit to 15-bit according to a predetermined rule is converted to original 8-bit code data group, an exclusive logic processor 11, a bit shift processor 12, a six-to-four decoder and an eleven-to-eight decoder 14 divides the 15(m) bit code (dividing by m at the maximum) into a plurality of areas, converts "1" (in the case of positive logic) in response to the generated bit position in the respective areas, and the numeric codes obtained by the numeric value converting means are added by an adder 15.
    Type: Grant
    Filed: April 10, 1996
    Date of Patent: May 26, 1998
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Yoshiyuki Ishizawa
  • Circuit for sensing input conditioning of keyboard
    Patent number: 5621401
    Abstract: A circuit for sensing keyboard input conditions, which includes a slot coupled to regulated signal lines, a supplementary circuit which generates a "Low" active signal in accordance with keyboard input activity after taking input signals from the slot, and a logic device or controller which performs a power-saving function by sensing input conditions from said slot with an interrupt request line or the supplementary circuit. The so-modified system can overcome the limits of a PC, in which the power-saving function can be performed only in the motherboard, by adding the power saving function to the system which has no logic device in the motherboard and also by sensing keyboard input conditions in a logic device included in an option card. This circuit can generate the appropriate signal by monitoring the regulated slot signals and has the same power-saving function that is performed in the motherboard itself when there is no keyboard inputting for a predetermined time.
    Type: Grant
    Filed: July 24, 1995
    Date of Patent: April 15, 1997
    Assignee: Samsung Electronics Co., Inc.
    Inventors: Phil-jung Jeon, Bong-lak Choi
  • Synchronous dram having a plurality of latency modes
    Patent number: 5835956
    Abstract: A synchronous dynamic random access memory capable of accessing data in a memory cell array therein in synchronism with a system clock from an external system such as a central processing unit (CPU).
    Type: Grant
    Filed: March 17, 1997
    Date of Patent: November 10, 1998
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Churoo Park, Hyun-Soon Jang, Chull-Soo Kim, Myung-Ho Kim, Seung-Hun Lee, Si-Yeol Lee, Ho-Cheol Lee, Tae-Jin Kim, Yun-Ho Choi
  • Remote control system and method having a system-specific code
    Patent number: 6181252
    Abstract: In a remote control system having a transmitter and a receiver, a rolling code is ciphered to generate a ciphered rolling code by repeating, n times, an exclusive-OR operation on a constant code in a rolling code table and the rolling code as well as an-maximum shift keying. A key code specific to each control system is used as a constant code at the k-th exclusive-OR logic operation so that the k-th exclusive-OR logic operation becomes different from system to system resulting in different ciphering method for each system. The key code is set in an EEPROM in the process of control system production so that the rolling code may not be deciphered even by a design engineer as long as the key code is kept undisclosed.
    Type: Grant
    Filed: August 22, 1997
    Date of Patent: January 30, 2001
    Assignee: Denso Corporation
    Inventor: Akio Nakano
  • Computational circuit
    Patent number: 6073149
    Abstract: A computational circuit for a multi-value addition comprising a parallel adder, an output adder, a quantizing portion and a logic conversion portion. Addition circuits in the above adders and thresholding circuits in the above quantizing portion consist of voltage-driven circuits including capacitive couplings.
    Type: Grant
    Filed: April 15, 1998
    Date of Patent: June 6, 2000
    Assignee: Yozan, Inc.
    Inventors: Guoliang Shou, Kazunori Motohashi, Ying Chen, Takashi Tomatsu, Changming Zhou, Jie Chen
  • System for selecting one of a plurality of memory banks for use in an active cycle and all other banks for an inactive precharge cycle
    Patent number: 5631871
    Abstract: A synchronous dynamic random access memory capable of accessing data in a memory cell array therein in synchronism with a system clock from an external system such as a central processing unit (CPU).
    Type: Grant
    Filed: December 29, 1995
    Date of Patent: May 20, 1997
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Churoo Park, Hyun-Soon Jang, Chull-Soo Kim, Myung-Ho Kim, Seung-Hun Lee, Si-Yeol Lee, Ho-Cheol Lee, Tae-Jin Kim, Yun-Ho Choi
  • Containers for holding materials
    Patent number: 9452857
    Abstract: The invention provides for a container that may include a liquid-holding vessel and a skeleton shell supporting the liquid holding vessel. The liquid-holding vessel may comprise a flexible polymer or plastic material for preventing contact between a liquid stored in or dispensed from the container and the skeleton. The liquid-holding vessel and the closure may be formed from a minimal amount of polymer or plastic.
    Type: Grant
    Filed: August 12, 2014
    Date of Patent: September 27, 2016
    Assignee: ECO.LOGIC BRANDS INC.
    Inventors: Julie Corbett, Romeo Graham, Robert Watters, Michael Sirois
  • Edge-trigger pulse generator
    Patent number: 5672990
    Abstract: An edge-trigger pulse generator that is suitable for use in a signal generator is disclosed, including positive and negative logic embodiments. The positive logic embodiment includes: a first time-delay circuit for delaying and inverting an input pulse; a second time-delay circuit for broadening the width of the input pulse; a NAND gate for receiving outputs of the first time-delay circuit and the second time-delay circuit, and performing a NAND logical operation for the outputs; and an inverter for receiving and inverting output of the NAND gate, so that the width of an pulse output from the edge-trigger pulse generator can be determined merely by the edge-trigger pulse generator while the width of the input pulse is not wider than a predetermined width. The negative logic embodiment replaces the NAND gate with NOR gate and has a second time-delay circuit that is different from the second time-delay circuit of the first embodiment.
    Type: Grant
    Filed: January 26, 1996
    Date of Patent: September 30, 1997
    Assignee: United Microelectronics Corporation
    Inventor: Shyh-Liang Chaw
  • Method and device for controlling a CPU stop clock interrupt
    Patent number: 5933649
    Abstract: A method and device for controlling a CPU stop clock interrupt of a computer system. The device includes an idle detector and a control processor. A CPU having a stop clock interrupt mode receives a stop clock interrupt signal and sets up and clears the stop clock interrupt mode according to a logic state of the stop clock interrupt signal. The control processor receives a signal representing an idle condition of the computer system from the idle detector, a signal for enabling idle detector control of the CPU stop clock interrupt mode and a signal for forcing the CPU to resume a normal mode by clearing the stop clock interrupt mode. The idle condition can be defined by a computer user according to a selection of predetermined times during which no user inputs are received by the computer system.
    Type: Grant
    Filed: February 9, 1996
    Date of Patent: August 3, 1999
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jung-Gyu Lim, Hee-Duck Park, Shung-Hyun Cho, Noh-Buyng Park
  • Pulp-formed wine bottle and containers for holding materials
    Patent number: 8807377
    Abstract: The invention provides for a container that may include a liquid-holding vessel and a skeleton shell supporting the liquid holding vessel. The liquid-holding vessel may comprise a flexible polymer or plastic material for preventing contact between a liquid stored in or dispensed from the container and the skeleton. The liquid-holding vessel and the closure may be formed from a minimal amount of polymer or plastic.
    Type: Grant
    Filed: March 9, 2011
    Date of Patent: August 19, 2014
    Assignee: Eco.Logic Brands Inc.
    Inventors: Julie Corbett, Romeo Graham, Robert Watters, Michael Sirois
  • System for controlling stop clock interrupt mode according to user selectable idle condition parameters and a control signal
    Patent number: 5754883
    Abstract: A method and device for controlling a CPU stop clock interrupt of a computer system. The device includes an idle detector and a control processor. A CPU having a stop clock interrupt mode receives a stop clock interrupt signal and initiates and terminates the stop clock interrupt mode according to a logic state of the stop clock interrupt signal. The control processor receives a signal representing an idle condition of the computer system from the idle detector, an alternate signal for idle detector control of the CPU stop clock interrupt mode, and a control signal for forcing the CPU to resume a normal mode by clearing the stop clock interrupt mode. The idle condition can be defined by a computer user according to a selection of predetermined times during which no user inputs are received by the computer system.
    Type: Grant
    Filed: June 20, 1995
    Date of Patent: May 19, 1998
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jung-Gyu Lim, Hee-Duck Park, Shung-Hyun Cho, Noh-Byung Park
  • Electronic device for sensing gas present in the environment
    Patent number: 6026673
    Abstract: An electronic device for sensing gas present in the environment, comprising a presence sensor for the gas concentration, a digital electronic circuit for processing data, a permanent random access memory, a bidirectional serial logic gate, at least one optical and/or acoustic warning device, and an electrical actuator or relay. During its production the electronic device receives from an external processor, via a serial line, data (gas concentration, temperature, humidity) relating to the environment in which the sensor is located, the data being analyzed by the digital electronic circuit together with the values present at the output of the sensor, for the purpose of calibrating the device.
    Type: Grant
    Filed: September 12, 1997
    Date of Patent: February 22, 2000
    Assignee: Bticino S.P.A.
    Inventor: Ernesto Santini
  • Astable multivibrator
    Patent number: 5712600
    Abstract: An astable multivibrator comprising a capacitor connected between a first output signal and a third output signal, an amplification circuit connected between the first and third output signals, a delay for delaying a signal logic-converted from the first output signal and for outputting a second output signal, and a variable resistor connected between the first output signal and an output node of the delay. High frequency oscillation performance is enhanced and a larger voltage operating range is obtained by excluding the effect of feedback current.
    Type: Grant
    Filed: September 29, 1995
    Date of Patent: January 27, 1998
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Won-Kyum Kim, Jang-Sik Won
  • Method of controlling power output by a primary power source so as to conserve power in an electronic communication device
    Patent number: 5806006
    Abstract: A system for reducing power consumption by a portable electronic communication device. Modem circuit for receiving messages and for transmitting messages from a portable electronic communication device are powered via power source control/switch coupled thereto. A logic circuit is coupled to the power source control/switch for control the power source control/switch to selectively deliver power to the modem circuit of the portable electronic communication device during a first time interval and to withhold power from the modem circuit of the portable electronic communication device during a second time interval. A low power control clock/counter is coupled to the logic circuit means for measuring the duration of the first and second time intervals. In one embodiment, the first time interval occurs while the modem circuit of the portable electronic communication device is transmitting or receiving messages.
    Type: Grant
    Filed: December 2, 1994
    Date of Patent: September 8, 1998
    Assignee: Eon Corporation
    Inventor: Gilbert M. Dinkins
  • Method and apparatus for adapting an asynchronous bus to a synchronous circuit
    Patent number: 6075830
    Abstract: Many digital processors have an asynchronous bus controlled by two control signals. To interface a synchronous memory to an asynchronous bus, interface logic is required. In an interface for transferring data from an asynchronous circuit to a synchronous circuit, data to be written are written in an intermediate register while timing control signals are being synchronized to a system clock by means of flip-flops. Correspondingly, in an interface for transferring data from the synchronous circuit to the asynchronous circuit, a signal indicating a read transaction from the synchronous circuit is synchronized to the system clock by means of a flip-flop circuit.
    Type: Grant
    Filed: November 28, 1997
    Date of Patent: June 13, 2000
    Assignee: Nokia Telecommunications Oy
    Inventor: Olli Piirainen
  • PHASE-FREQUENCY DETECTOR
    Publication number: 20200328749
    Abstract: A phase-frequency detector has two latches, two logic gates, and two delay sources. Operation includes inputting a reference clock signal to a first of two latches; inputting a feedback clock signal to a second of two latches; outputting simultaneously a first signal and a second signal. The first signal having a pulse width directly proportional to a phase difference between said reference clock signal and the feedback clock signal; the second signal having a pulse width inversely proportional to the phase difference between the reference clock signal and the feedback clock signal. The outputs of the latches indicate a differential phase difference of signals, thereby increasing the signal-to noise ratio of the phase-frequency detector.
    Type: Application
    Filed: April 12, 2019
    Publication date: October 15, 2020
    Applicant: BAE SYSTEMS Information and Electronic Systems Integration Inc.
    Inventor: Gary M. Madison
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