Search Patents
  • Portable computer which performs bus arbitration using a serial bus
    Patent number: 5819052
    Abstract: An I/o control gate array, a power supply controller, an EEPROM of a battery pack, a DS (docking station) controller, and an EEPROM of a docking station are connected to an I.sup.2 C serial BUS. This I.sup.2 C serial BUS and an ISA bus are connected by the I/O control gate array. The I/O control gate array incorporates a master control logic. Master arbitration between the power supply controller and the DS controller connected to the I.sup.2 C BUS is intensively controlled by arbitration circuitry of the I/O control gate array by using REQ# and GNT# lines of these masters.
    Type: Grant
    Filed: June 14, 1996
    Date of Patent: October 6, 1998
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Shingo Sonoda
  • SEMICONDUCTOR DEVICE ASSEMBLIES AND SYSTEMS WITH INTERNAL THERMAL BARRIERS AND METHODS FOR MAKING THE SAME
    Publication number: 20220051962
    Abstract: Semiconductor device assemblies are provided with a layer of thermal barrier material between a first semiconductor device (e.g., a logic die or other heat-generating device) and a second semiconductor device (e.g., a memory die or other device whose performance may be improved in a lower-temperature environment). The layer of thermal barrier material can reduce the conduction of the heat generated by the first semiconductor device towards the second semiconductor device. The assemblies can also include one or more thermally conductive structures disposed in the substrate under the first semiconductor device and configured to conduct the heat from the first semiconductor device out of the semiconductor device assembly.
    Type: Application
    Filed: August 12, 2020
    Publication date: February 17, 2022
    Inventors: Owen R. Fay, Madison E. Wale, James L. Voelz, Dylan W. Southern
  • Traceback-performing apparatus in viterbi decoder
    Patent number: 5712880
    Abstract: A traceback-performing apparatus includes a first storing portion which receives and stores new path metric values and minimum path metric value so that the first input value is output later and the later input value is output first. A first trace logic portion which receives outputs of the first storing portion and the minimum path metric value and generates a first state which is the next state to be traced. A second storing portion which receives and stores the output of the first storing portion so that the first input value is output first and the later input value is output later. A second trace logic portion which receives the output of the second storing portion and the first state and generates a second state which is the next state to be traced. And, a third storing portion which receives and stores the second state so that the first input value is output later and the later input value is output first so as to find the decoded bits.
    Type: Grant
    Filed: November 14, 1995
    Date of Patent: January 27, 1998
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Min-joong Rim, Young-uk Oh
  • Digital locked loop
    Patent number: 5744928
    Abstract: A digital locked loop uses feedback to maintain an output digital signal in a specific digital relationship with a reference digital signal. The digital locked loop can lock an input digital signal according to a reference digital signal by using a digital counter, a resister and an arithmetic logic circuit instead of a phase locked loop and a frequency locked loop in motor drive integrated circuit for permanent magnetic brushless DC multi-phase motor drive applications. The circuit is designed not to use a voltage-controlled oscillator VCO and can be extended to broader applications such as digital data communications, digital image processing, and in the multi-media industry.
    Type: Grant
    Filed: April 29, 1996
    Date of Patent: April 28, 1998
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Shi-ming Tang, Sang-yong Lee
  • Power conservation in synchronous SRAM cache memory blocks of a computer system
    Patent number: 5752045
    Abstract: A synchronous cache memory power conservation apparatus for conserving power of the cache SRAM memory blocks in cached computer systems. The power conservation apparatus is included as a portion of the logic of the cache controller of the computer system. The power conservation apparatus monitors the CPU bus cycles in order to shut off the clocking signals supplied to the cache SRAM memory blocks when the CPU is not accessing the cache memory, thereby reducing the power consumption of the high-power SRAM devices. The power conservation apparatus resumes standard synchronized clocking to the cache SRAM blocks when the CPU is performing a cache-hit memory access cycle for maximum cache access performance.
    Type: Grant
    Filed: July 14, 1995
    Date of Patent: May 12, 1998
    Assignee: United Microelectronics Corporation
    Inventor: David Yu Chen
  • Side impact passenger protection system for vehicle and crash determination device of same
    Patent number: 6005479
    Abstract: A crash determination device employed in a vehicle side impact passenger protection system uses logic circuits or microcomputers to correctly determine whether an impact is a crash with an obstruction such as another vehicle by making use of a phase difference between detected accelerations of a side acceleration sensor and a central acceleration sensor. By making use of the phase difference between detected accelerations of side and center acceleration sensors, a high-speed crash can be correctly distinguished from a low-speed impact and an erroneous determination resulting in the passenger protection system being operated in a side impact situation not necessitating operation of the passenger protection system can be avoided.
    Type: Grant
    Filed: January 8, 1998
    Date of Patent: December 21, 1999
    Assignee: Denso Corporation
    Inventor: Seiya Ide
  • Person lifting apparatuses including lifting straps and methods of operation based on current draw
    Patent number: 11344462
    Abstract: A person lifting apparatus includes a first lifting strap feeding device including a first drum and a first lifting strap wound on the first drum. A second lifting strap feeding device includes a second drum and a second lifting strap wound on the second drum. A controller is communicatively coupled to the first lifting strap feeding device and to the second lifting strap feeding device. The controller includes logic that controls operation of the first lifting strap feeding device and the second lifting strap feeding device based on a comparison of current draws of the first lifting strap feeding device and the second lifting strap feeding device.
    Type: Grant
    Filed: September 19, 2019
    Date of Patent: May 31, 2022
    Assignee: Liko Research & Development AB
    Inventors: Joseph Tari, Derek Strassle
  • Electronic indentification system with transponder muting
    Patent number: 5966083
    Abstract: An identification system includes an interrogator and a number of transponders. The interrogator includes a transmitter for transmitting an interrogation signal to the transponder, and a receiver for receiving a response signal from the transponder. A micro-processor identifies the transponder from data in the response signal. Each transponder includes a receiving antenna for receiving the interrogation signal, a code generator, a transmitting antenna, and a modulator connected to the code generator. On receipt of the interrogation signal the transponder repeatedly transmits a response signal containing data which identifies the transponder. The interrogator detects successful identification of any transponder and briefly interrupts the interrogation signal to indicate the successful identification. Each transponder includes a logic circuit responsive to a respective interruption in the interrogation signal to cease transmission of its own response signal.
    Type: Grant
    Filed: November 24, 1997
    Date of Patent: October 12, 1999
    Assignee: BTG International Limited
    Inventors: Michael John Camille Marsh, Andrzej Lenarcik
  • Electronic identification system confirming valid code
    Patent number: 5995017
    Abstract: An identification system having an interrogator and a number of transponders. The interrogator includes a transmitter for transmitting an interrogation signal to the transponder, and a receiver for receiving a response signal from the transponder. A micro-processor identifies the transponder from data in the response signal. Each transponder includes a receiving antenna for receiving the interrogation signal, a code generator, a transmitting antenna, and a modulator connected to the code generator. On receipt of the interrogation signal the transponder repeatedly transmits a response signal containing data which identifies the transponder. The interrogator detects successful identification of any transponder and briefly interrupts the interrogation signal to indicate the successful identification. Each transponder includes a logic circuit responsive to a respective interruption in the interrogation signal to cease transmission of its own response signal.
    Type: Grant
    Filed: November 24, 1997
    Date of Patent: November 30, 1999
    Assignee: BTG International Limited
    Inventors: Michael John Camille Marsh, Andrzej Lenarcik
  • Speed based hands-on alarm system for a steering wheel
    Patent number: 11845441
    Abstract: A speed based alarm system to be used in automobiles includes a first touch sensor, a second touch sensor, a processing unit, and a notification alarm. The first touch sensor and the second touch sensor are integrated into a steering wheel body of an automobile to detect the hands of the driver on the steering wheel. The feedback from the first touch sensor and/or the second touch sensor are received at the processing unit along with a vehicle speed, wherein the vehicle speed is retrieved from a vehicle logic board. The processing unit determines if the automobile is at a speed which requires both hands of the driver for better control of the automobile. If the automobile is at a speed that requires both hands of the driver, and only one hand is detected on the steering wheel, the processing unit activates the notification alarm to notify the driver.
    Type: Grant
    Filed: November 2, 2020
    Date of Patent: December 19, 2023
    Assignee: Imam Abdulrahman Bin Faisal University
    Inventor: Ahmed Salah M. Alkhoudiri
  • Code table reduction apparatus for variable length decoder
    Patent number: 5619200
    Abstract: A code table apparatus for a variable length decoder (VLD) is disclosed. The code table apparatus is connected to a barrel shifter to obtain an input code which consists of a code word portion and a sign bit. The code table apparatus comprises a coefficient table for generating a level code and a length code by the code word portion, and a mask circuit for generating a sign bit by a logic operation of the input code and the length code. The coefficient table can decode input codes with opposite sign bits, thus reducing the dimensions of the coefficient table as well as the VLD. Furthermore, since the dimensions of the coefficient table are reduced, the operation time delay of the DCT coefficient table can be shorter, thus improving the performance of the VLD.
    Type: Grant
    Filed: September 12, 1995
    Date of Patent: April 8, 1997
    Assignee: United Microelectronics Corporation
    Inventor: Po-Chuan Huang
  • Clock synthesizer for low EMI applications
    Patent number: 5710524
    Abstract: The object of the present invention is to provide a clock synthesizer IC which can produce clock signals with much lower radiated EMI.
    Type: Grant
    Filed: April 9, 1996
    Date of Patent: January 20, 1998
    Assignee: Myson Technology, Inc.
    Inventors: Chun-Ming Chou, Jia-Der Hsieh, Tsen-Shau Yang
  • Error-preventing system having a signal correction unit
    Patent number: 5713026
    Abstract: An error preventing system for card service interrupt signals in a personal computer using a plurality of card interface controllers, which includes at least two PCMCIA (Personal Computer Memory Card International Association) cards, at least two PCICs (PCMCIA Card Interface Controllers) which each output an interrupt signal to service the respective PCMCIA card and operate a portable computer through this process, and a signal-correction unit which inputs the interrupt signal output from the PCICs and outputs the corresponding signals after processing the outputted interrupt signals of logic OR. For preventing an error and a system-halt while prohibiting the collision between signals to transmit the accurate card service interrupt signal in case each PCIC outputs a respective card service interrupt signal.
    Type: Grant
    Filed: June 9, 1995
    Date of Patent: January 27, 1998
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Seung-Kee Shin, Tae-Wook Kim
  • Time diversity communications system
    Patent number: 5794124
    Abstract: A system wherein time diversity reception is performed for each error-corrected or error-detected code word without distinguishing between the address signal and the message signal, the code words being the units which make up the address and message signals. A received signal comprising correctly decoded code words is obtained by selecting code words that are judged to have been correctly decoded in accordance with error detecting/correcting logic from among code words with the same content that have been received a plurality of times. When a code word has been correctly decoded, part of the selective radio paging receiver is inhibited from working during the time intervals when correctly received code words would be received, thereby decreasing battery consumption.
    Type: Grant
    Filed: November 13, 1995
    Date of Patent: August 11, 1998
    Assignee: NTT Mobile Communications Network Inc.
    Inventors: Shogo Ito, Yasushi Yamao, Shinzo Ohkubo
  • Data loading circuit for partial program of nonvolatile semiconductor memory
    Patent number: 5712818
    Abstract: The present invention provides a nonvolatile semiconductor memory comprising a plurality of floating gate-type memory cells arranged in a matrix form of rows and columns; a plurality of bit lines connected the memory cells arranged in the direction of said column; a plurality of data lines respectively connected to the plurality of bit lines; a plurality of latch circuits respectively connected to said plurality of data lines; a preset unit for presetting the plurality of latch circuits to predetermined logic states during a presetting operation; a unit for loading data to selected ones of the plurality of latch circuits through data input/output terminals during a data loading operation after the presetting operation; and unit for programming to the memory cells arranged and erased in one selected row, data loaded to the latch circuits of the selected portion and data presetted to remaining latch circuits except for the latch circuits of the selected portion during a programming operation after the data load
    Type: Grant
    Filed: October 2, 1995
    Date of Patent: January 27, 1998
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Sung-Soo Lee, Jin-Ki Kim
  • Logic operation circuit and carry look ahead adder
    Patent number: 5877973
    Abstract: An 8-bit CLA adder is constructed for inputting 4 lower bits a3:0,b3:0 and 4 upper bits a7:4,b7:4 of two input signals to the two 4-bit full adders 2,12 and a carry c-1 to the lowest bit the full adder of the first-stage 2 to generate carries c3,c7 correspondint to the third and seventh bit of the input signals from a carry generation signal g7:0 and a carry propagation signal p7:0 generated by the both adders 2,12 and the carry c-1. The full adder of the second-stage 12 is constructed to add the 4 upper bits a7:4,b7:4 with setting a carry-in as 0 so as to generate a temporary summing signal sz7:4. A logical circuit 14 generates a true sum of 4 upper bits from a carry c3 to the third bit to the forth bit, a temporary sum sz7:4 and a carry propagation signal p7:4 generated by the full adder of the second-stage 12.
    Type: Grant
    Filed: February 26, 1997
    Date of Patent: March 2, 1999
    Assignee: Denso Corporation
    Inventors: Koji Kato, Harutsugu Fukumoto, Hiroaki Tanaka
  • Continuous tuning of digitally switched voltage-controlled oscillator frequency bands
    Patent number: 11012079
    Abstract: A phase locked loop (PLL) control system includes a voltage-controlled oscillator (VCO) circuit including an inductor and a plurality of capacitors arranged in parallel with the inductor. Digitally enabling or disabling the capacitors in a thermometer coded manner via switches creates tuning states that provide additional frequency range, and each has a limited range of VCO frequency tuning. Slowly ramping the switched capacitance, by implementing the capacitor as a varactor, from one thermal code to the next, provides a wider continuous VCO frequency tuning range for use in the PLL. The slow transition between tuning states allows the PLL to remain in lock, useful under changing operating conditions. Specifically, under changing operating conditions, digital logic detects the PLL tuning control voltage approaching the edge of a VCO band and will add/reduce VCO capacitance effectively transitioning into the adjacent VCO band while the PLL maintains lock via its normal feedback loop.
    Type: Grant
    Filed: December 19, 2019
    Date of Patent: May 18, 2021
    Assignee: BAE Systems Information and Electronic Systems Integration Inc.
    Inventors: Joseph D. Cali, Curtis M. Grens, Richard L. Harwood, Gary M. Madison
  • Processor having a scalable, uni/multi-dimensional, and virtually/physically addressed operand register file
    Patent number: 6081880
    Abstract: A processor is implemented with an operand register file having N operand registers, instructions that reference these operand registers with virtual and physical source and destination addresses of variable up to n addressing dimensions, and at least one address mapping circuit that maps the uni-dimensional virtual and the multi-dimensional virtual/physical source and destination addresses to their uni-dimensional equivalents. Whether a source/destination address is a virtual or a physical address may be implicitly inferred from the instruction type, or explicitly specified. Source and destination addresses of an instruction may be either all virtual addresses, or all physical addresses, or virtual as well as physical addresses. The addressing dimension of an instruction's source and destination addresses may be specified in the instruction, or specified in a control register of the processor.
    Type: Grant
    Filed: March 9, 1995
    Date of Patent: June 27, 2000
    Assignee: LSI Logic Corporation
    Inventor: Donald Sollars
  • Data communication device and method of a smart card
    Patent number: 5729004
    Abstract: An input/output device of a smart card according to the present invention comprises a first register having a serial input terminal connected to a terminal serial input/output; a second register having parallel detection terminals, parallel input/output terminals connected to a data bus, and a serial input terminal connected to a serial output terminal of the first register; a third register having a parallel input terminal connected to a ground, a serial input terminal connected to a serial output terminal of the second register, and a serial output terminal connected to the terminal serial input/output; a parity generator which receives parallel output data from the parallel detection terminals of the second register, logically operates upon the parallel output data to generate an operation parity bit which is applied to a parallel input indicator terminal of the first register; and a parity detector which receives a reception parity bit from the first register and the operation parity bit from the parity g
    Type: Grant
    Filed: October 2, 1995
    Date of Patent: March 17, 1998
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jong-Chul Kim, Sang-Joe Ra
  • Liquid crystal display
    Patent number: 6049321
    Abstract: A liquid crystal display includes a matrix array of liquid crystal pixels, data lines formed along columns of the pixels, TFTs assigned to the pixels for causing the data lines to be electrically connected to the pixels of a selected row, and a data line driver which drives the data lines and has a first video bus for transmitting analog pixel signals of the positive polarity for the pixels of one of odd and even columns in a selected row, a second video bus for transmitting analog pixel signals of the negative polarity for the pixels of the other one of the odd and even columns in the selected row, sample-hold units each assigned to adjacent two of the data lines to simultaneously sample-hold the pixel signals on the first and second video buses, and a shift register circuit for enabling the operations of the sample-hold units sequentially.
    Type: Grant
    Filed: September 25, 1997
    Date of Patent: April 11, 2000
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Minoru Sasaki
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