Search Patents
  • Measuring response time for a computer accessing information from a network
    Publication number: 20020112049
    Abstract: A method, computer program product and apparatus are disclosed for generating response time data for a client accessing information from a network. In one of the embodiments first instructions are attached to a first block of information. The block of information is available for requesting by the client from the network. The first instructions are for causing the client to read a first reference time, responsive to the client initiating access to a second block of information from the network. Second instructions are attached to the second block of information. The second instructions are for causing the client to read a second reference time responsive to the client loading the second block of information, and for causing the client to retrieve the first reference time and compute a time difference between the first and second reference times.
    Type: Application
    Filed: December 14, 2000
    Publication date: August 15, 2002
    Applicant: International Business Machines Corporation
    Inventors: Elmootazbellah Nabil Elnozahy, Ramakrishnan Rajamony
  • Architecture Support for Debugging Multithreaded Code
    Publication number: 20110258421
    Abstract: Mechanisms are provided for debugging application code using a content addressable memory. The mechanisms receive an instruction in a hardware unit of a processor of the data processing system, the instruction having a target memory address that the instruction is attempting to access. A content addressable memory (CAM) associated with the hardware unit is searched for an entry in the CAM corresponding to the target memory address. In response to an entry in the CAM corresponding to the target memory address being found, a determination is made as to whether information in the entry identifies the instruction as an instruction of interest. In response to the entry identifying the instruction as an instruction of interest, an exception is generated and sent to one of an exception handler or a debugger application. In this way, debugging of multithreaded applications may be performed in an efficient manner.
    Type: Application
    Filed: April 19, 2010
    Publication date: October 20, 2011
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Elmootazbellah N. Elnozahy, Ahmed Gheith
  • Fast remote communication and computation between processors using store and load operations on direct core-to-core memory
    Patent number: 9934079
    Abstract: A system, and computer usable program product for fast remote communication and computation between processors are provided in the illustrative embodiments. A direct core to core communication unit (DCC) is configured to operate with a first processor, the first processor being a remote processor. A memory associated with the DCC receives a set of bytes, the set of bytes being sent from a second processor. An operation specified in the set of bytes is executed at the remote processor such that the operation is invoked without causing a software thread to execute.
    Type: Grant
    Filed: May 27, 2010
    Date of Patent: April 3, 2018
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: John Bruce Carter, Elmootazbellah Nabil Elnozahy, Ahmed Gheith, Eric Van Hansbergen, Karthick Rajamani, William Evan Speight, Lixin Zhang
  • RECOVERY IN SHARED MEMORY ENVIRONMENT
    Publication number: 20120226870
    Abstract: A method for recovery in a shared memory environment is provided in the illustrative embodiments. A core in a multi-core processor is designated as a user level core (ULC), which executes an instruction to modify a memory while executing an application. A second core is designated as a operating system core (OSC), which manages checkpointing of several segments of the shared memory. A set of flags is accessible to a memory controller to manage a shared memory. A flag in the set of flags corresponds to one segment in the segments of the shared memory. A message or instruction for modification of a segment is received. A cache line tracking determination is made whether a cache line used for the modification has already been used for a similar modification. If not, a part of the segment is checkpointed. The modification proceeds after checkpointing.
    Type: Application
    Filed: March 7, 2012
    Publication date: September 6, 2012
    Applicant: International Business Machines Corporation
    Inventor: Elmootazbellah Nabil Elnozahy
  • Accelerating recovery in MPI environments
    Patent number: 8381028
    Abstract: A computer usable program product for accelerating recovery in an MPI environment is provided in the illustrative embodiments. A first portion of a distributed application executes using a first processor and a second portion using a second processor in a distributed computing environment. After a failure of operation of the first portion, the first portion is restored to a checkpoint. A first part of the first portion is distributed to a third processor and a second part to a fourth processor. A computation of the first portion is performed using the first and the second parts in parallel. A first message is computed in the first portion and sent to the second portion, the message having been initially computed after a time of the checkpoint. A second message is replayed from the second portion without computing the second message in the second portion.
    Type: Grant
    Filed: April 16, 2012
    Date of Patent: February 19, 2013
    Assignee: International Business Machines Corporation
    Inventor: Elmootazbellah Nabil Elnozahy
  • METHOD OF EXPLOITING SPARE PROCESSORS TO REDUCE ENERGY CONSUMPTION
    Publication number: 20110154348
    Abstract: A method, system, and computer program product for reducing power and energy consumption in a server system with multiple processor cores is disclosed. The system may include an operating system for scheduling user workloads among a processor pool. The processor pool may include active licensed processor cores and inactive unlicensed processor cores. The method and computer program product may reduce power and energy consumption by including steps and sets of instructions activating spare cores and adjusting the operating frequency of processor cores, including the newly activated spare cores to provide equivalent computing resources as the original licensed cores operating at a specified clock frequency.
    Type: Application
    Filed: December 17, 2009
    Publication date: June 23, 2011
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: ELMOOTAZBELLAH N. ELNOZAHY, HEATHER L. HANSON, FREEMAN L. RAWSON, III, MALCOLM S. WARE
  • Methods and arrangements to manage on-chip memory to reduce memory latency
    Publication number: 20060155886
    Abstract: Methods, systems, and media for reducing memory latency seen by processors by providing a measure of control over on-chip memory (OCM) management to software applications, implicitly and/or explicitly, via an operating system are contemplated. Many embodiments allow part of the OCM to be managed by software applications via an application program interface (API), and part managed by hardware. Thus, the software applications can provide guidance regarding address ranges to maintain close to the processor to reduce unnecessary latencies typically encountered when dependent upon cache controller policies. Several embodiments utilize a memory internal to the processor or on a processor node so the memory block used for this technique is referred to as OCM.
    Type: Application
    Filed: January 11, 2005
    Publication date: July 13, 2006
    Inventors: Dilma da Silva, Elmootazbellah Elnozahy, Orran Krieger, Hazim Shafi, Xiaowei Shen, Balaram Sinharoy, Robert Tremaine
  • FRAMEWORK FOR SCHEDULING MULTICORE PROCESSORS
    Publication number: 20120227048
    Abstract: A method for a framework for scheduling tasks in a multi-core processor or multiprocessor system is provided in the illustrative embodiments. A thread is selected according to an order in a scheduling discipline, the thread being a thread of an application executing in the data processing system, the thread forming the leader thread in a bundle of threads. A value of a core attribute in a set of core attributes is determined according to a corresponding thread attribute in a set of thread attributes associated with the leader thread. A determination is made whether a second thread can be added to the bundle such that the bundle including the second thread will satisfy a policy. If the determining is affirmative, the second thread is added to the bundle. The bundle is scheduled for execution using a core of the multi-core processor.
    Type: Application
    Filed: March 7, 2012
    Publication date: September 6, 2012
    Applicant: International Business Machines Corporation
    Inventors: Elmootazbellah Nabil Elnozahy, Heather Lynn Hanson, James Lyle Peterson, Freeman Leigh Rawson, III, Malcolm Scott Ware
  • Single Thread Performance in an In-Order Multi-Threaded Processor
    Publication number: 20110265068
    Abstract: A mechanism is provided for improving single-thread performance for a multi-threaded, in-order processor core. In a first phase, a compiler analyzes application code to identify instructions that can be executed in parallel with focus on instruction-level parallelism and removing any register interference between the threads. The compiler inserts as appropriate synchronization instructions supported by the apparatus to ensure that the resulting execution of the threads is equivalent to the execution of the application code in a single thread. In a second phase, an operating system schedules the threads produced in the first phase on the hardware threads of a single processor core such that they execute simultaneously. In a third phase, the microprocessor core executes the threads specified by the second phase such that there is one hardware thread executing an application thread.
    Type: Application
    Filed: April 27, 2010
    Publication date: October 27, 2011
    Applicant: International Business Machines Corporation
    Inventors: Elmootazbellah N. Elnozahy, Ahmed Gheith
  • RECOVERY IN SHARED MEMORY ENVIRONMENT
    Publication number: 20110296113
    Abstract: A method, system, and computer usable program product for recovery in a shared memory environment are provided in the illustrative embodiments. A core in a multi-core processor is designated as a user level core (ULC), which executes an instruction to modify a memory while executing an application. A second core is designated as a operating system core (OSC), which manages checkpointing of several segments of the shared memory. A set of flags is accessible to a memory controller to manage a shared memory. A flag in the set of flags corresponds to one segment in the segments of the shared memory. A message or instruction for modification of a segment is received. A cache line tracking determination is made whether a cache line used for the modification has already been used for a similar modification. If not, a part of the segment is checkpointed. The modification proceeds after checkpointing.
    Type: Application
    Filed: May 27, 2010
    Publication date: December 1, 2011
    Applicant: International Business Machines Corporation
    Inventor: ELMOOTAZBELLAH NABIL ELNOZAHY
  • Power aware adaptive polling
    Patent number: 7093141
    Abstract: A method for adapting the periodicity of polling for pending service requests, by polling system devices for pending service requests, recording whether or not there was a pending service request and, based on accumulated data, determining whether or not the system devices are idle. Based on this determination, the system may elect to enter a power conservation mode until device activity is signaled, or an adjustable period of time elapses. The adaptation mechanism may alter the periodicity of the timer interrupt, disable or enable device interrupts, and modify variables used to determine system idleness (including minimum latency and minimum idleness thresholds). In this manner, the system can conserve power while maintaining system performance and responsiveness.
    Type: Grant
    Filed: December 18, 2002
    Date of Patent: August 15, 2006
    Assignee: International Business Machines Corporation
    Inventors: Elmootazbellah N. Elnozahy, Eric Van Hensbergen
  • Accelerating recovery in MPI environments
    Patent number: 8250405
    Abstract: A method and system for accelerating recovery in an MPI environment are provided in the illustrative embodiments. A first portion of a distributed application executes using a first processor and a second portion using a second processor in a distributed computing environment. After a failure of operation of the first portion, the first portion is restored to a checkpoint. A first part of the first portion is distributed to a third processor and a second part to a fourth processor. A computation of the first portion is performed using the first and the second parts in parallel. A first message is computed in the first portion and sent to the second portion, the message having been initially computed after a time of the checkpoint. A second message is replayed from the second portion without computing the second message in the second portion.
    Type: Grant
    Filed: May 27, 2010
    Date of Patent: August 21, 2012
    Assignee: International Business Machines Corporation
    Inventor: Elmootazbellah Nabil Elnozahy
  • Method of exploiting spare processors to reduce energy consumption
    Patent number: 9292662
    Abstract: A method, system, and computer program product for reducing power and energy consumption in a server system with multiple processor cores is disclosed. The system may include an operating system for scheduling user workloads among a processor pool. The processor pool may include active licensed processor cores and inactive unlicensed processor cores. The method and computer program product may reduce power and energy consumption by including steps and sets of instructions activating spare cores and adjusting the operating frequency of processor cores, including the newly activated spare cores to provide equivalent computing resources as the original licensed cores operating at a specified clock frequency.
    Type: Grant
    Filed: December 17, 2009
    Date of Patent: March 22, 2016
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Elmootazbellah N. Elnozahy, Heather L. Hanson, Freeman L. Rawson, III, Malcolm S. Ware
  • ON-CHIP CONTROL OF THERMAL CYCLING
    Publication number: 20120223764
    Abstract: A method, system, and computer program product for on-chip control of thermal cycling in an integrated circuit (IC) are provided in the illustrative embodiments. A first circuit is configured on the IC for adjusting a first voltage being applied to a first part of the IC. A first temperature of the first part is measured at a first time. A determination is made that the first temperature is outside a temperature range defined by an upper temperature threshold and a lower temperature threshold. The first voltage is adjusted by reducing the first voltage when the first temperature exceeds the upper temperature threshold and by increasing the first voltage when the first temperature is below the lower temperature threshold, thereby causing the first temperature of the first part to attain a value within the temperature range.
    Type: Application
    Filed: March 3, 2011
    Publication date: September 6, 2012
    Applicant: International Business Machines Corporation
    Inventors: Malcolm Scott Allen-Ware, John Bruce Carter, Elmootazbellah Nabil Elnozahy, Wei Huang
  • On-chip control of thermal cycling
    Patent number: 10049957
    Abstract: A method, system, and computer program product for on-chip control of thermal cycling in an integrated circuit (IC) are provided in the illustrative embodiments. A first circuit is configured on the IC for adjusting a first voltage being applied to a first part of the IC. A first temperature of the first part is measured at a first time. A determination is made that the first temperature is outside a temperature range defined by an upper temperature threshold and a lower temperature threshold. The first voltage is adjusted by reducing the first voltage when the first temperature exceeds the upper temperature threshold and by increasing the first voltage when the first temperature is below the lower temperature threshold, thereby causing the first temperature of the first part to attain a value within the temperature range.
    Type: Grant
    Filed: March 3, 2011
    Date of Patent: August 14, 2018
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Malcolm Scott Allen-Ware, John Bruce Carter, Elmootazbellah Nabil Elnozahy, Wei Huang
  • Total cost based checkpoint selection
    Patent number: 8127154
    Abstract: A cost associated with taking a checkpoint is determined. The cost includes an energy cost. An interval between checkpoints is computed so as to minimize the cost. An instruction is sent to schedule the checkpoints at the computed interval. The energy cost may further include a cost of energy consumed in collecting and saving data at a checkpoint, a cost of energy consumed in re-computing a computation lost due to a failure after taking the checkpoint, or a combination thereof. The cost may further include, converted to a cost equivalent, administration time consumed in recovering from a checkpoint, computing resources expended in taking a checkpoint, computing resources expended after a failure in restoring information from a checkpoint, performance degradation of an application while taking a checkpoint, or a combination thereof.
    Type: Grant
    Filed: October 2, 2008
    Date of Patent: February 28, 2012
    Assignee: International Business Machines Corporation
    Inventor: Elmootazbellah N Elnozahy
  • Client request handling in a NAS- based server environment
    Publication number: 20030033383
    Abstract: A method and system for responding to a client request for information from a service device in a data processing network. Initially, the server receives the information request from the client and determines that the requested information is not in the server's cache. The server then generates a storage request and sends the storage request to a network attached storage device. The storage device retrieves the requested information and generates a set of packets containing the requested information. The storage device then sending the generated packets simultaneously to the client to satisfy the client request and to the server to refresh the server cache. The storage request may include protocol information corresponding to the client-server connection that the storage device uses to replicate the client-server protocol stack in the generated packet. Sending the generated packet may comprise including a multicast address in the packet.
    Type: Application
    Filed: July 26, 2001
    Publication date: February 13, 2003
    Applicant: International Business Machines Corporation
    Inventors: Elmootazbellah Nabil Elnozahy, Michael David Kistler
  • Methods and Arrangements to Manage On-Chip Memory to Reduce Memory Latency
    Publication number: 20080263284
    Abstract: Methods, systems, and media for reducing memory latency seen by processors by providing a measure of control over on-chip memory (OCM) management to software applications, implicitly and/or explicitly, via an operating system are contemplated. Many embodiments allow part of the OCM to be managed by software applications via an application program interface (API), and part managed by hardware. Thus, the software applications can provide guidance regarding address ranges to maintain close to the processor to reduce unnecessary latencies typically encountered when dependent upon cache controller policies. Several embodiments utilize a memory internal to the processor or on a processor node so the memory block used for this technique is referred to as OCM.
    Type: Application
    Filed: June 24, 2008
    Publication date: October 23, 2008
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Dilma Menezes da Silva, Elmootazbellah Nabil Elnozahy, Orran Yaakov Krieger, Hazim Shafi, Xiaowei Shen, Balaram Sinharoy, Robert Brett Tremaine
  • Error detection in a data processing system
    Publication number: 20060156156
    Abstract: A compiler for incorporating error detection into executable code generates conventional assembler language object code from a source code file. The compiler identifies an error detection segment (EDS) in the assembler code, where the EDS includes a subset of basic blocks in the assembler code. The compiler also identifies register and memory references in the EDS and inserts a set of instructions into the EDS. The inserted instructions record an entry state and an exit state of the referenced registers and memory locations. The state information is stored in a checkpoint portion of system memory. The compiler may generate shadow EDS code including instructions mirroring the instructions in the main EDS and verifying instructions that compare results produced by the mirroring instructions with results produced by the main EDS. The shadow EDS initiates an error recovery process if results produced by the shadow EDS and the main EDS differ.
    Type: Application
    Filed: January 13, 2005
    Publication date: July 13, 2006
    Inventor: Elmootazbellah Elnozahy
  • Deterministic and preemptive thread scheduling and its use in debugging multithreaded applications
    Patent number: 6625635
    Abstract: A computer system which permits deterministic and preemptive scheduling of threads in a software application. In one embodiment, a scheduler is utilized to schedule the threads in a queue. Once the threads are scheduled, they are divided up into instruction slices each consisting of a predetermined number of instructions. The scheduler executes each instruction slice. An instruction counter is utilized to keep track of the number of instructions executed. The thread is permitted to run the instruction slice until the predetermined number of instructions has been executed. Alternatively, the thread stops if it is blocked while waiting for an input, for example. The next thread is then executed for the same number of instructions. This process permits for the efficient debugging of software which utilizes traditional cyclic debugging.
    Type: Grant
    Filed: November 2, 1998
    Date of Patent: September 23, 2003
    Assignee: International Business Machines Corporation
    Inventor: Elmootazbellah Nabil Elnozahy
Narrow Results

Filter by US Classification