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  • Total cost based checkpoint selection
    Publication number: 20100088494
    Abstract: A method, system, and computer usable program product for total cost based checkpoint selection are provided in the illustrative embodiments. A cost associated with taking a checkpoint is determined. The cost includes an energy cost. An interval between checkpoints is computed so as to minimize the cost. An instruction is sent to schedule the checkpoints at the computed interval. The energy cost may further include a cost of energy consumed in collecting and saving data at a checkpoint, a cost of energy consumed in re-computing a computation lost due to a failure after taking the checkpoint, or a combination thereof. The cost may further include, converted to a cost equivalent, administration time consumed in recovering from a checkpoint, computing resources expended in taking a checkpoint, computing resources expended after a failure in restoring information from a checkpoint, performance degradation of an application while taking a checkpoint, or a combination thereof.
    Type: Application
    Filed: October 2, 2008
    Publication date: April 8, 2010
    Applicant: International Business Machines corporation
    Inventor: Elmootazbellah N. Elnozahy
  • Energy-efficient failure detection and masking
    Patent number: 8448027
    Abstract: A method, system, and computer usable program product for energy-efficient soft error failure detection and masking are provided in the illustrative embodiments. A soft error is injected to occur during execution of a set of instructions. If an output of the execution of the set of instructions is incorrect, a record is made of the instruction that was affected by the injected soft error and led to the incorrect result. This identified instruction is designated as vulnerable to the soft error. Several soft errors are injected with different input data sets over several executions of the same set of instructions, and a probability of each instruction in the instruction set is computed, the probability of an instruction accounting for the vulnerability of the execution of the instruction sets to errors that affect the instruction. A report including several probabilities of instruction vulnerabilities is produced.
    Type: Grant
    Filed: May 27, 2010
    Date of Patent: May 21, 2013
    Assignee: International Business Machines Corporation
    Inventors: Elmootazbellah Nabil Elnozahy, Mark William Stephenson
  • Optimistic processing of network frames to reduce latency
    Patent number: 7203722
    Abstract: A system and method in which the server device processes the lower level layers, referred to herein as the “network portion”, of a frame substantially in parallel with the processing of the application portion of the frame. The application portion of the frame, which may include an HTTP request is forwarded to the server application such as a web server, while the network portion of the frame is processed. If the processing of the network portion determines that the frame was mis-delivered or is corrupted, the response to the HTTP request is aborted, otherwise the response is processed and returned to the client. By optimistically assuming that the request was delivered correctly, the present invention leverages the parallel processing capabilities available on many server appliances and improve response time without incurring any substantial performance penalty.
    Type: Grant
    Filed: May 24, 2001
    Date of Patent: April 10, 2007
    Assignee: International Business Machines Corporation
    Inventor: Elmootabellah Nabil Elnozahy
  • Recovery in shared memory environment
    Patent number: 8312224
    Abstract: A system, and computer usable program product for recovery in a shared memory environment are provided in the illustrative embodiments. A core in a multi-core processor is designated as a user level core (ULC), which executes an instruction to modify a memory while executing an application. A second core is designated as a operating system core (OSC), which manages checkpointing of several segments of the shared memory. A set of flags is accessible to a memory controller to manage a shared memory. A flag in the set of flags corresponds to one segment in the segments of the shared memory. A message or instruction for modification of a segment is received. A cache line tracking determination is made whether a cache line used for the modification has already been used for a similar modification. If not, a part of the segment is checkpointed. The modification proceeds after checkpointing.
    Type: Grant
    Filed: May 27, 2010
    Date of Patent: November 13, 2012
    Assignee: International Business Machines Corporation
    Inventor: Elmootazbellah Nabil Elnozahy
  • Processing of requests for static objects in a network server
    Publication number: 20030023766
    Abstract: A method and system for responding to requests for static web documents including saving the response as a packet train comprising one or more IP compliant packets. Upon a subsequent request for the static web document, the saved packet train may be retrieved and the header information updated. In this manner, the network protocol processing required to respond to the request is reduced. The server may include code for determining whether a referenced web object is a static object and a directory of recently accessed static web objects and a copy of the corresponding packet trains. The web server may be configured to consult the directory to determine if an object is a static object that has been recently accessed. If the object has been recently accessed, the server may retrieve the corresponding packet train from its system memory or from disk and update the packet headers prior to transmission.
    Type: Application
    Filed: July 26, 2001
    Publication date: January 30, 2003
    Applicant: International Business Machines Corporation
    Inventor: Elmootazbellah Nabil Elnozahy
  • Method and system for clustering instructions within executable code for compression
    Patent number: 6317867
    Abstract: In accordance with a method and system of the present invention, a compression scheme for program executables is disclosed. First, instruction clustering starts by placing each instruction in a cluster by itself. The method and system then compute in an iterative fashion the distance between clusters, and merge the nearest clusters to form larger clusters. Therefore, instructions are clustered into groups, such that instructions belonging to the same cluster show similar bit patterns. This process stops when the number of clusters reaches a pre-specified goal. This goal is defined empirically, and may be adjusted if better compression can result. After all clusters have been defined, a suitable compressor is applied to each cluster to produce the compressed executable.
    Type: Grant
    Filed: January 29, 1999
    Date of Patent: November 13, 2001
    Assignee: International Business Machines Corporation
    Inventor: Elmootazbellah Elnozahy
  • Debugging multithreaded code by generating exception upon target address CAM search for variable and checking race condition
    Patent number: 8838939
    Abstract: Mechanisms are provided for debugging application code using a content addressable memory. The mechanisms receive an instruction in a hardware unit of a processor of the data processing system, the instruction having a target memory address that the instruction is attempting to access. A content addressable memory (CAM) associated with the hardware unit is searched for an entry in the CAM corresponding to the target memory address. In response to an entry in the CAM corresponding to the target memory address being found, a determination is made as to whether information in the entry identifies the instruction as an instruction of interest. In response to the entry identifying the instruction as an instruction of interest, an exception is generated and sent to one of an exception handler or a debugger application. In this way, debugging of multithreaded applications may be performed in an efficient manner.
    Type: Grant
    Filed: April 4, 2012
    Date of Patent: September 16, 2014
    Assignee: International Business Machines Corporation
    Inventors: Elmootazbellah N. Elnozahy, Ahmed Gheith
  • Apparatus and method for providing remote access redirect capability in a channel adapter of a system area network
    Publication number: 20060155880
    Abstract: A method and apparatus for providing remote access redirect in a host channel adapter of a system area network are provided. The apparatus and method provide a mechanism by which a host channel adapter, in response to receiving a marker message, places selected channel(s) of the host channel adapter in a remote access redirect (RAR) mode of operation. During the RAR mode of operation, memory access messages received by the host channel adapter that are destined for portions of an application memory space marked as being protected are converted to RAR receive messages and redirected to a queue pair associated with an operating system rather than the queue pair for the application. The operating system is responsible for serializing access to application memory pages outside of the host channel adapter. The mechanisms of the present invention may be used to perform a checkpoint data integrity operation.
    Type: Application
    Filed: January 13, 2005
    Publication date: July 13, 2006
    Inventors: Elmootazbellah Elnozahy, Peter Walker
  • Framework for scheduling multicore processors
    Patent number: 8990831
    Abstract: A method for a framework for scheduling tasks in a multi-core processor or multiprocessor system is provided in the illustrative embodiments. A thread is selected according to an order in a scheduling discipline, the thread being a thread of an application executing in the data processing system, the thread forming the leader thread in a bundle of threads. A value of a core attribute in a set of core attributes is determined according to a corresponding thread attribute in a set of thread attributes associated with the leader thread. A determination is made whether a second thread can be added to the bundle such that the bundle including the second thread will satisfy a policy. If the determining is affirmative, the second thread is added to the bundle. The bundle is scheduled for execution using a core of the multi-core processor.
    Type: Grant
    Filed: March 7, 2012
    Date of Patent: March 24, 2015
    Assignee: International Business Machines Corporation
    Inventors: Elmootazbellah Nabil Elnozahy, Heather Lynn Hanson, James Lyle Peterson, Freeman Leigh Rawson, III, Malcolm Scott Ware
  • FRAMEWORK FOR SCHEDULING MULTICORE PROCESSORS
    Publication number: 20110296423
    Abstract: A method, system, and computer usable program product for a framework for scheduling tasks in a multi-core processor or multiprocessor system are provided in the illustrative embodiments. A thread is selected according to an order in a scheduling discipline, the thread being a thread of an application executing in the data processing system, the thread forming the leader thread in a bundle of threads. A value of a core attribute in a set of core attributes is determined according to a corresponding thread attribute in a set of thread attributes associated with the leader thread. A determination is made whether a second thread can be added to the bundle such that the bundle including the second thread will satisfy a policy. If the determining is affirmative, the second thread is added to the bundle. The bundle is scheduled for execution using a core of the multi-core processor.
    Type: Application
    Filed: May 27, 2010
    Publication date: December 1, 2011
    Applicant: International Business Machines Corporation
    Inventors: ELMOOTAZBELLAH NABIL ELNOZAHY, Heather Lynn Hanson, James Lyle Peterson, Freeman Leigh Rawson, III, Malcolm Scott Ware
  • Conserving energy in a data processing network
    Patent number: 8370517
    Abstract: A data processing network and method for conserving energy in which an initial negotiation between a network server and a switch to which the server is connected is performed to establish an initial operating frequency of the server-switch link. An effective data rate of the server is determined based on network traffic at the server. Responsive to determining that the effective data rate is materially different than the current operating frequency, a subsequent negotiation is performed to establish a modified operating frequency where the modified operating frequency is closer to the effective data rate than the initial operating frequency. The determination of the effective date rate and the contingent initiation of a subsequent negotiation may be repeated periodically during the operating of the network. In one embodiment, the initial and subsequent negotiation are compliant with the IEEE 802.3 standard.
    Type: Grant
    Filed: September 27, 2001
    Date of Patent: February 5, 2013
    Assignee: International Business Machines Corporation
    Inventors: Patrick Joseph Bohrer, Bishop Chapman Brock, Elmootazbellah Nabil Elnozahy, Ramakrishnan Rajamony, Freeman Leigh Rawson, III
  • Single thread performance in an in-order multi-threaded processor
    Patent number: 8650554
    Abstract: A mechanism is provided for improving single-thread performance for a multi-threaded, in-order processor core. In a first phase, a compiler analyzes application code to identify instructions that can be executed in parallel with focus on instruction-level parallelism and removing any register interference between the threads. The compiler inserts as appropriate synchronization instructions supported by the apparatus to ensure that the resulting execution of the threads is equivalent to the execution of the application code in a single thread. In a second phase, an operating system schedules the threads produced in the first phase on the hardware threads of a single processor core such that they execute simultaneously. In a third phase, the microprocessor core executes the threads specified by the second phase such that there is one hardware thread executing an application thread.
    Type: Grant
    Filed: April 27, 2010
    Date of Patent: February 11, 2014
    Assignee: International Business Machines Corporation
    Inventors: Elmootazbellah N. Elnozahy, Ahmed Gheith
  • System and method for retrieving data from disk in a network environment
    Publication number: 20030004948
    Abstract: A system and method of retrieving data from a disk includes determining the network transfer rate of a network connection between a client and a server. A first portion of the requested data is retrieved from the disk responsive to a data request received by the server from the client via a network connection and transmission of the first portion of data to the client via the network is initiated. The time required to transmit the first portion of data to the client is calculated based upon the network transfer rate and a determination of when to retrieve a subsequent portion of the requested data from disk is made based, in part, on whether the calculated time is expired. The determination of when to retrieve subsequent portions of data from disk may be further based on a desire to minimize a system parameter such as memory usage or disk energy consumption and heat dissipation.
    Type: Application
    Filed: June 29, 2001
    Publication date: January 2, 2003
    Applicant: International Business Machines Corporation
    Inventors: Patrick Joseph Bohrer, Bishop Chapman Brock, Elmootazbellah Nabil Elnozahy, Ramakrishnan Rajamony
  • Data storage on a multi-tiered disk system
    Publication number: 20040243761
    Abstract: A method and a computer usable medium including a program for operating disks having units, comprising: providing a first tier of at least one disk, the first tier storing at least one popular unit, providing a second tier of at least one disk, the second tier storing at least one unpopular unit, powering on at least one first tier disk, powering down the second tier, determining whether a request for a unit requires processing on the first tier or second tier, accessing the requested unit if the requested unit requires processing on the first tier, and powering on a second tier disk to copy the requested unit from the second tier disk to a first tier disk, if the requested unit is stored on the second tier.
    Type: Application
    Filed: July 12, 2001
    Publication date: December 2, 2004
    Applicants: International Business Machines Corporation, IBM Corporation
    Inventors: Patrick J. Bohrer, Elmootazbellah N. Elnozahy, Charles R. Lefurgy, Ramakrishnan Rajamony, Bruce A. Smith
  • Stackable Module for Energy-Efficient Computing Systems
    Publication number: 20110292597
    Abstract: A modular processing module is provided. The modular processing module comprises a set of processing module sides. Each processing module side comprises a circuit board, a plurality of connectors coupled to the circuit board, and a plurality of processing nodes coupled to the circuit board. Each processing module side in the set of processing module sides couples to another processing module side using at least one connector in the plurality of connectors such that, when all of the set of processing module sides are coupled together, the modular processing module is formed. The modular processing module comprises an exterior connection to a power source and a communication system.
    Type: Application
    Filed: May 28, 2010
    Publication date: December 1, 2011
    Applicant: International Business Machines Corporation
    Inventors: John B. Carter, Wael R. El-Essawy, Elmootazbellah N. Elnozahy, Wesley M. Felter, Madhusudan K. Iyengar, Thomas W. Keller, JR., Karthick Rajamani, Juan C. Rubio, William E. Speight, Lixin Zhang
  • Architectural Support for Automated Assertion Checking
    Publication number: 20110173592
    Abstract: A mechanism is provided for automatic detection of assertion violations. An application may write assertion tuples to the assertion checking mechanism. An assertion tuple forms a Boolean expression (predicate or invariant) that the developer of the application wishes to check. If the assertion defined by the tuple remains true, then the application does not violate the assertion. For any instruction that stores a value to a memory location or register at a target address, the assertion checking mechanism compares the target address to the addresses specified in the assertion tuples. If the target address matches one of the tuple addresses, then the assertion checking mechanism reads a value from the other address in the tuple. The assertion checking mechanism then recomputes the assertion using the retrieved value along with the value to be stored. If the assertion checking mechanism detects an assertion violation, the assertion checking mechanism raises an exception.
    Type: Application
    Filed: January 13, 2010
    Publication date: July 14, 2011
    Applicant: International Business Machines Corporation
    Inventors: Elmootazbellah N. Elnozahy, Mark W. Stephenson
  • Framework for scheduling multicore processors
    Patent number: 8510749
    Abstract: A system, and computer usable program product for a framework for scheduling tasks in a multi-core processor or multiprocessor system are provided in the illustrative embodiments. A thread is selected according to an order in a scheduling discipline, the thread being a thread of an application executing in the data processing system, the thread forming the leader thread in a bundle of threads. A value of a core attribute in a set of core attributes is determined according to a corresponding thread attribute in a set of thread attributes associated with the leader thread. A determination is made whether a second thread can be added to the bundle such that the bundle including the second thread will satisfy a policy. If the determining is affirmative, the second thread is added to the bundle. The bundle is scheduled for execution using a core of the multi-core processor.
    Type: Grant
    Filed: May 27, 2010
    Date of Patent: August 13, 2013
    Assignee: International Business Machines Corporation
    Inventors: Elmootazbellah Nabil Elnozahy, Heather Lynn Hanson, James Lyle Peterson, Freeman Leigh Rawson, III, Malcolm Scott Ware
  • Scalable Space-Optimized and Energy-Efficient Computing System
    Publication number: 20110292594
    Abstract: A scalable space-optimized and energy-efficient computing system is provided. The computing system comprises a plurality of modular compartments in at least one level of a frame configured in a hexadron configuration. The computing system also comprises an air inlet, an air mixing plenum, and at least one fan. In the computing system the plurality of modular compartments are affixed above the air inlet, the air mixing plenum is affixed above the plurality of modular compartments, and the at least one fan is affixed above the air mixing plenum. When at least one module is inserted into one of the plurality of modular compartments, the module couples to a backplane within the frame.
    Type: Application
    Filed: May 28, 2010
    Publication date: December 1, 2011
    Applicant: International Business Machines Corporation
    Inventors: John B. Carter, Wael R. El-Essawy, Elmootazbellah N. Elnozahy, Madhusudan K. Iyengar, Thomas W. Keller, JR., Jian Li, Karthick Rajamani, Juan C. Rubio, William E. Speight, Lixin Zhang
  • Optimized file cache organization in a network server
    Publication number: 20030061352
    Abstract: A data processing server and method in which the server device stores a first fragment of a requested file in a first tier of storage while retaining subsequent fragments of the file in a lower tier of storage. The first tier is typically the server's volatile system memory while the second tier may represent a local disk, a networked storage device, or a remote system memory. When the server receives a client request for a file, the server transmits a first fragment of the file stored in the file cache to the client. Simultaneously, the server retrieves a subsequent fragment of the file from a lower tier of storage. By the time the first fragment is transmitted and acknowledged, the subsequent fragment is ready for transmission. In this manner, the server is able to maintain responsiveness while minimizing the amount of data cached in valuable system memory.
    Type: Application
    Filed: September 27, 2001
    Publication date: March 27, 2003
    Applicant: International Business Machines Corporation
    Inventors: Patrick Joseph Bohrer, Elmootazbellah Nabil Elnozahy, Thomas Walter Keller, Ramakrishnan Rajamony
  • Conserving energy in a data processing network
    Publication number: 20030074464
    Abstract: A data processing network and method for conserving energy in which an initial negotiation between a network server and a switch to which the server is connected is performed to establish an initial operating frequency of the server-switch link. An effective data rate of the server is determined based on network traffic at the server. Responsive to determining that the effective data rate is materially different than the current operating frequency, a subsequent negotiation is performed to establish a modified operating frequency where the modified operating frequency is closer to the effective data rate than the initial operating frequency. The determination of the effective date rate and the contingent initiation of a subsequent negotiation may be repeated periodically during the operating of the network. In one embodiment, the initial and subsequent negotiation are compliant with the IEEE 802.3 standard.
    Type: Application
    Filed: September 27, 2001
    Publication date: April 17, 2003
    Applicant: International Business Machines Corporation
    Inventors: Patrick Joseph Bohrer, Bishop Chapman Brock, Elmootazbellah Nabil Elnozahy, Ramakrishnan Rajamony, Freeman Leigh Rawson
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