Search Patents
  • Patent number: 8250405
    Abstract: A method and system for accelerating recovery in an MPI environment are provided in the illustrative embodiments. A first portion of a distributed application executes using a first processor and a second portion using a second processor in a distributed computing environment. After a failure of operation of the first portion, the first portion is restored to a checkpoint. A first part of the first portion is distributed to a third processor and a second part to a fourth processor. A computation of the first portion is performed using the first and the second parts in parallel. A first message is computed in the first portion and sent to the second portion, the message having been initially computed after a time of the checkpoint. A second message is replayed from the second portion without computing the second message in the second portion.
    Type: Grant
    Filed: May 27, 2010
    Date of Patent: August 21, 2012
    Assignee: International Business Machines Corporation
    Inventor: Elmootazbellah Nabil Elnozahy
  • Publication number: 20030074464
    Abstract: A data processing network and method for conserving energy in which an initial negotiation between a network server and a switch to which the server is connected is performed to establish an initial operating frequency of the server-switch link. An effective data rate of the server is determined based on network traffic at the server. Responsive to determining that the effective data rate is materially different than the current operating frequency, a subsequent negotiation is performed to establish a modified operating frequency where the modified operating frequency is closer to the effective data rate than the initial operating frequency. The determination of the effective date rate and the contingent initiation of a subsequent negotiation may be repeated periodically during the operating of the network. In one embodiment, the initial and subsequent negotiation are compliant with the IEEE 802.3 standard.
    Type: Application
    Filed: September 27, 2001
    Publication date: April 17, 2003
    Applicant: International Business Machines Corporation
    Inventors: Patrick Joseph Bohrer, Bishop Chapman Brock, Elmootazbellah Nabil Elnozahy, Ramakrishnan Rajamony, Freeman Leigh Rawson
  • Publication number: 20030023766
    Abstract: A method and system for responding to requests for static web documents including saving the response as a packet train comprising one or more IP compliant packets. Upon a subsequent request for the static web document, the saved packet train may be retrieved and the header information updated. In this manner, the network protocol processing required to respond to the request is reduced. The server may include code for determining whether a referenced web object is a static object and a directory of recently accessed static web objects and a copy of the corresponding packet trains. The web server may be configured to consult the directory to determine if an object is a static object that has been recently accessed. If the object has been recently accessed, the server may retrieve the corresponding packet train from its system memory or from disk and update the packet headers prior to transmission.
    Type: Application
    Filed: July 26, 2001
    Publication date: January 30, 2003
    Applicant: International Business Machines Corporation
    Inventor: Elmootazbellah Nabil Elnozahy
  • Publication number: 20110292594
    Abstract: A scalable space-optimized and energy-efficient computing system is provided. The computing system comprises a plurality of modular compartments in at least one level of a frame configured in a hexadron configuration. The computing system also comprises an air inlet, an air mixing plenum, and at least one fan. In the computing system the plurality of modular compartments are affixed above the air inlet, the air mixing plenum is affixed above the plurality of modular compartments, and the at least one fan is affixed above the air mixing plenum. When at least one module is inserted into one of the plurality of modular compartments, the module couples to a backplane within the frame.
    Type: Application
    Filed: May 28, 2010
    Publication date: December 1, 2011
    Applicant: International Business Machines Corporation
    Inventors: John B. Carter, Wael R. El-Essawy, Elmootazbellah N. Elnozahy, Madhusudan K. Iyengar, Thomas W. Keller, JR., Jian Li, Karthick Rajamani, Juan C. Rubio, William E. Speight, Lixin Zhang
  • Publication number: 20040243761
    Abstract: A method and a computer usable medium including a program for operating disks having units, comprising: providing a first tier of at least one disk, the first tier storing at least one popular unit, providing a second tier of at least one disk, the second tier storing at least one unpopular unit, powering on at least one first tier disk, powering down the second tier, determining whether a request for a unit requires processing on the first tier or second tier, accessing the requested unit if the requested unit requires processing on the first tier, and powering on a second tier disk to copy the requested unit from the second tier disk to a first tier disk, if the requested unit is stored on the second tier.
    Type: Application
    Filed: July 12, 2001
    Publication date: December 2, 2004
    Applicants: International Business Machines Corporation, IBM Corporation
    Inventors: Patrick J. Bohrer, Elmootazbellah N. Elnozahy, Charles R. Lefurgy, Ramakrishnan Rajamony, Bruce A. Smith
  • Publication number: 20110173592
    Abstract: A mechanism is provided for automatic detection of assertion violations. An application may write assertion tuples to the assertion checking mechanism. An assertion tuple forms a Boolean expression (predicate or invariant) that the developer of the application wishes to check. If the assertion defined by the tuple remains true, then the application does not violate the assertion. For any instruction that stores a value to a memory location or register at a target address, the assertion checking mechanism compares the target address to the addresses specified in the assertion tuples. If the target address matches one of the tuple addresses, then the assertion checking mechanism reads a value from the other address in the tuple. The assertion checking mechanism then recomputes the assertion using the retrieved value along with the value to be stored. If the assertion checking mechanism detects an assertion violation, the assertion checking mechanism raises an exception.
    Type: Application
    Filed: January 13, 2010
    Publication date: July 14, 2011
    Applicant: International Business Machines Corporation
    Inventors: Elmootazbellah N. Elnozahy, Mark W. Stephenson
  • Patent number: 8589895
    Abstract: A mechanism is provided for automatic detection of assertion violations. An application may write assertion tuples to the assertion checking mechanism. An assertion tuple forms a Boolean expression (predicate or invariant) that the developer of the application wishes to check. If the assertion defined by the tuple remains true, then the application does not violate the assertion. For any instruction that stores a value to a memory location or register at a target address, the assertion checking mechanism compares the target address to the addresses specified in the assertion tuples. If the target address matches one of the tuple addresses, then the assertion checking mechanism reads a value from the other address in the tuple. The assertion checking mechanism then recomputes the assertion using the retrieved value along with the value to be stored. If the assertion checking mechanism detects an assertion violation, the assertion checking mechanism raises an exception.
    Type: Grant
    Filed: January 13, 2010
    Date of Patent: November 19, 2013
    Assignee: International Business Machines Corporation
    Inventors: Elmootazbellah N. Elnozahy, Mark W. Stephenson
  • Publication number: 20090144383
    Abstract: A method and apparatus for providing remote access redirect in a host channel adapter of a system area network are provided. The apparatus and method provide a mechanism by which a host channel adapter, in response to receiving a marker message, places selected channel(s) of the host channel adapter in a remote access redirect (RAR) mode of operation. During the RAR mode of operation, memory access messages received by the host channel adapter that are destined for portions of an application memory space marked as being protected are converted to RAR receive messages and redirected to a queue pair associated with an operating system rather than the queue pair for the application. The operating system is responsible for serializing access to application memory pages outside of the host channel adapter. The mechanisms of the present invention may be used to perform a checkpoint data integrity operation.
    Type: Application
    Filed: December 19, 2008
    Publication date: June 4, 2009
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Elmootazbellah Nabil Elnozahy, Peter Anthony Walker
  • Publication number: 20030061352
    Abstract: A data processing server and method in which the server device stores a first fragment of a requested file in a first tier of storage while retaining subsequent fragments of the file in a lower tier of storage. The first tier is typically the server's volatile system memory while the second tier may represent a local disk, a networked storage device, or a remote system memory. When the server receives a client request for a file, the server transmits a first fragment of the file stored in the file cache to the client. Simultaneously, the server retrieves a subsequent fragment of the file from a lower tier of storage. By the time the first fragment is transmitted and acknowledged, the subsequent fragment is ready for transmission. In this manner, the server is able to maintain responsiveness while minimizing the amount of data cached in valuable system memory.
    Type: Application
    Filed: September 27, 2001
    Publication date: March 27, 2003
    Applicant: International Business Machines Corporation
    Inventors: Patrick Joseph Bohrer, Elmootazbellah Nabil Elnozahy, Thomas Walter Keller, Ramakrishnan Rajamony
  • Publication number: 20080263284
    Abstract: Methods, systems, and media for reducing memory latency seen by processors by providing a measure of control over on-chip memory (OCM) management to software applications, implicitly and/or explicitly, via an operating system are contemplated. Many embodiments allow part of the OCM to be managed by software applications via an application program interface (API), and part managed by hardware. Thus, the software applications can provide guidance regarding address ranges to maintain close to the processor to reduce unnecessary latencies typically encountered when dependent upon cache controller policies. Several embodiments utilize a memory internal to the processor or on a processor node so the memory block used for this technique is referred to as OCM.
    Type: Application
    Filed: June 24, 2008
    Publication date: October 23, 2008
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Dilma Menezes da Silva, Elmootazbellah Nabil Elnozahy, Orran Yaakov Krieger, Hazim Shafi, Xiaowei Shen, Balaram Sinharoy, Robert Brett Tremaine
  • Publication number: 20060156156
    Abstract: A compiler for incorporating error detection into executable code generates conventional assembler language object code from a source code file. The compiler identifies an error detection segment (EDS) in the assembler code, where the EDS includes a subset of basic blocks in the assembler code. The compiler also identifies register and memory references in the EDS and inserts a set of instructions into the EDS. The inserted instructions record an entry state and an exit state of the referenced registers and memory locations. The state information is stored in a checkpoint portion of system memory. The compiler may generate shadow EDS code including instructions mirroring the instructions in the main EDS and verifying instructions that compare results produced by the mirroring instructions with results produced by the main EDS. The shadow EDS initiates an error recovery process if results produced by the shadow EDS and the main EDS differ.
    Type: Application
    Filed: January 13, 2005
    Publication date: July 13, 2006
    Inventor: Elmootazbellah Elnozahy
  • Publication number: 20030033383
    Abstract: A method and system for responding to a client request for information from a service device in a data processing network. Initially, the server receives the information request from the client and determines that the requested information is not in the server's cache. The server then generates a storage request and sends the storage request to a network attached storage device. The storage device retrieves the requested information and generates a set of packets containing the requested information. The storage device then sending the generated packets simultaneously to the client to satisfy the client request and to the server to refresh the server cache. The storage request may include protocol information corresponding to the client-server connection that the storage device uses to replicate the client-server protocol stack in the generated packet. Sending the generated packet may comprise including a multicast address in the packet.
    Type: Application
    Filed: July 26, 2001
    Publication date: February 13, 2003
    Applicant: International Business Machines Corporation
    Inventors: Elmootazbellah Nabil Elnozahy, Michael David Kistler
  • Publication number: 20110296423
    Abstract: A method, system, and computer usable program product for a framework for scheduling tasks in a multi-core processor or multiprocessor system are provided in the illustrative embodiments. A thread is selected according to an order in a scheduling discipline, the thread being a thread of an application executing in the data processing system, the thread forming the leader thread in a bundle of threads. A value of a core attribute in a set of core attributes is determined according to a corresponding thread attribute in a set of thread attributes associated with the leader thread. A determination is made whether a second thread can be added to the bundle such that the bundle including the second thread will satisfy a policy. If the determining is affirmative, the second thread is added to the bundle. The bundle is scheduled for execution using a core of the multi-core processor.
    Type: Application
    Filed: May 27, 2010
    Publication date: December 1, 2011
    Applicant: International Business Machines Corporation
    Inventors: ELMOOTAZBELLAH NABIL ELNOZAHY, Heather Lynn Hanson, James Lyle Peterson, Freeman Leigh Rawson, III, Malcolm Scott Ware
  • Patent number: 8838939
    Abstract: Mechanisms are provided for debugging application code using a content addressable memory. The mechanisms receive an instruction in a hardware unit of a processor of the data processing system, the instruction having a target memory address that the instruction is attempting to access. A content addressable memory (CAM) associated with the hardware unit is searched for an entry in the CAM corresponding to the target memory address. In response to an entry in the CAM corresponding to the target memory address being found, a determination is made as to whether information in the entry identifies the instruction as an instruction of interest. In response to the entry identifying the instruction as an instruction of interest, an exception is generated and sent to one of an exception handler or a debugger application. In this way, debugging of multithreaded applications may be performed in an efficient manner.
    Type: Grant
    Filed: April 4, 2012
    Date of Patent: September 16, 2014
    Assignee: International Business Machines Corporation
    Inventors: Elmootazbellah N. Elnozahy, Ahmed Gheith
  • Publication number: 20060155880
    Abstract: A method and apparatus for providing remote access redirect in a host channel adapter of a system area network are provided. The apparatus and method provide a mechanism by which a host channel adapter, in response to receiving a marker message, places selected channel(s) of the host channel adapter in a remote access redirect (RAR) mode of operation. During the RAR mode of operation, memory access messages received by the host channel adapter that are destined for portions of an application memory space marked as being protected are converted to RAR receive messages and redirected to a queue pair associated with an operating system rather than the queue pair for the application. The operating system is responsible for serializing access to application memory pages outside of the host channel adapter. The mechanisms of the present invention may be used to perform a checkpoint data integrity operation.
    Type: Application
    Filed: January 13, 2005
    Publication date: July 13, 2006
    Inventors: Elmootazbellah Elnozahy, Peter Walker
  • Patent number: 8990831
    Abstract: A method for a framework for scheduling tasks in a multi-core processor or multiprocessor system is provided in the illustrative embodiments. A thread is selected according to an order in a scheduling discipline, the thread being a thread of an application executing in the data processing system, the thread forming the leader thread in a bundle of threads. A value of a core attribute in a set of core attributes is determined according to a corresponding thread attribute in a set of thread attributes associated with the leader thread. A determination is made whether a second thread can be added to the bundle such that the bundle including the second thread will satisfy a policy. If the determining is affirmative, the second thread is added to the bundle. The bundle is scheduled for execution using a core of the multi-core processor.
    Type: Grant
    Filed: March 7, 2012
    Date of Patent: March 24, 2015
    Assignee: International Business Machines Corporation
    Inventors: Elmootazbellah Nabil Elnozahy, Heather Lynn Hanson, James Lyle Peterson, Freeman Leigh Rawson, III, Malcolm Scott Ware
  • Patent number: 6317867
    Abstract: In accordance with a method and system of the present invention, a compression scheme for program executables is disclosed. First, instruction clustering starts by placing each instruction in a cluster by itself. The method and system then compute in an iterative fashion the distance between clusters, and merge the nearest clusters to form larger clusters. Therefore, instructions are clustered into groups, such that instructions belonging to the same cluster show similar bit patterns. This process stops when the number of clusters reaches a pre-specified goal. This goal is defined empirically, and may be adjusted if better compression can result. After all clusters have been defined, a suitable compressor is applied to each cluster to produce the compressed executable.
    Type: Grant
    Filed: January 29, 1999
    Date of Patent: November 13, 2001
    Assignee: International Business Machines Corporation
    Inventor: Elmootazbellah Elnozahy
  • Publication number: 20080270726
    Abstract: A method and apparatus for providing remote access redirect in a host channel adapter of a system area network are provided. The apparatus and method provide a mechanism by which a host channel adapter, in response to receiving a marker message, places selected channel(s) of the host channel adapter in a remote access redirect (RAR) mode of operation. During the RAR mode of operation, memory access messages received by the host channel adapter that are destined for portions of an application memory space marked as being protected are converted to RAR receive messages and redirected to a queue pair associated with an operating system rather than the queue pair for the application. The operating system is responsible for serializing access to application memory pages outside of the host channel adapter. The mechanisms of the present invention may be used to perform a checkpoint data integrity operation.
    Type: Application
    Filed: July 17, 2008
    Publication date: October 30, 2008
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Elmootazbellah Nabil Elnozahy, Peter Anthony Walker
  • Patent number: 8510749
    Abstract: A system, and computer usable program product for a framework for scheduling tasks in a multi-core processor or multiprocessor system are provided in the illustrative embodiments. A thread is selected according to an order in a scheduling discipline, the thread being a thread of an application executing in the data processing system, the thread forming the leader thread in a bundle of threads. A value of a core attribute in a set of core attributes is determined according to a corresponding thread attribute in a set of thread attributes associated with the leader thread. A determination is made whether a second thread can be added to the bundle such that the bundle including the second thread will satisfy a policy. If the determining is affirmative, the second thread is added to the bundle. The bundle is scheduled for execution using a core of the multi-core processor.
    Type: Grant
    Filed: May 27, 2010
    Date of Patent: August 13, 2013
    Assignee: International Business Machines Corporation
    Inventors: Elmootazbellah Nabil Elnozahy, Heather Lynn Hanson, James Lyle Peterson, Freeman Leigh Rawson, III, Malcolm Scott Ware
  • Patent number: 8463456
    Abstract: A mechanism is provided for minimizing system power in a data processing system. A management control unit determines whether a convergence has been reached in the data processing system. If convergence fails to be reached, the management control unit determines whether a maximum fan flag is set to indicate that a fan is operating at a maximum speed. Responsive to the maximum fan flag failing to be set, a thermal threshold of the data processing system is either increased or decreased and thereby a fan speed of the data processing system is either increased or decreased based on whether the system power of the data processing system has either increased or decreased and based on whether a temperature of the data processing system has either increased or decreased. Thus, a new thermal threshold and a new fan speed are formed. The process is then repeated until convergence has been met.
    Type: Grant
    Filed: March 18, 2010
    Date of Patent: June 11, 2013
    Assignee: International Business Machines Corporation
    Inventors: John B. Carter, Elmootazbellah N. Elnozahy, Malcolm S. Ware, Wei Huang
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