Abstract: A method for manufacturing a semiconductor device in accordance with an embodiment of the present invention includes a step of forming a TiN film 2 on an underlying film 1; a step of coating a photoresist film on the TiN film 2, and exposing and developing the photoresist film; a step of etching the TiN film 2 using the photoresist film 4a as a mask, by using an etching apparatus that etches an Al alloy film; a step of introducing a mixed gas containing O2 gas and N2 gas adjacent to the photoresist film, and plasmatizing the gas to thereby ash the photoresist film, and a step of introducing H2O gas adjacent to the TiN film, and plasmatizing the gas to thereby ash foreign matters on the TiN film.

Abstract: Embodiments include a method for forming a head suspension assembly. A spacer layer is formed in or on a silicon wafer. A transfer film including an opening defining the shape of a slider support membrane is provided, and the opening is filled with a resin material. The transfer film with the resin material therein is positioned over the silicon wafer so that at least a portion of the resin material is positioned adjacent to the spacer layer. The resin material is baked to form a glassy carbon material. The spacer layer is etched to form a trench in the silicon wafer adjacent to the glassy carbon material, and a slider is positioned on the glassy carbon material over the trench.

Abstract: Certain embodiments of the present invention relate to a semiconductor device that has a pad section having an excellent coherency with an interlayer dielectric layer, and a method for manufacturing the same. A semiconductor device 1000 has a pad layer 30A formed over an interlayer dielectric layer 20. The pad section 30A includes a wetting layer 32 and a metal wiring layer 37. The metal wiring layer 37 includes an alloy layer 34 that contacts the wetting layer 32. The alloy layer 34 is formed from a material composing the wetting layer 32 and a material composing the metal wiring layer 37.

Abstract: Embodiments include a semiconductor device having a non-volatile memory transistor, the semiconductor device including a plurality of field effect transistors operated at a plurality of different voltage levels. The semiconductor device has a memory region 4000, and first second and third transistor regions 1000, 2000 and 3000 respectively including field effect transistors that operate at different voltage levels. The memory region 4000 includes a split-gate non-volatile memory transistor 400. The first transistor region 1000 includes a first voltage-type transistor 100 that operates at a first voltage level. The second transistor region 2000 includes a second voltage-type transistor 200 that operates at a to second voltage level. The third transistor region 3000 includes a third voltage-type transistor that operates at a third voltage level. The second voltage-type transistor 200 has a gate insulation layer 22 that is formed from at least two insulation layers 22a and 22b.

Abstract: A method for manufacturing a semiconductor device that mix mounts non-volatile memories and analog IC's may include the steps of: (a) forming a gate insulation layer 20, a floating gate 22, and a selective oxide insulation layer 24 on a semiconductor substrate 10; (b) forming an insulation layer 12 and a lower electrode 32 that composes a capacitor 300; (d) forming, in a capacitor region 3000, an insulation layer 31 by thermally oxidizing an upper surface section of the lower electrode 32; and (f) forming an intermediate insulation layer 26 and a control gate 23 that form a memory transistor 200, and a dielectric layer 30 and an upper electrode 34 that form the capacitor 300.

Abstract: Methods for fabricating semiconductor devices are described, including methods which improve an etching selection ratio of a film to be etched against metal silicide, Si, and photoresist. One method for fabricating a semiconductor device includes the steps of forming Ti silicide films 9a-9c on the gate electrode 3 and the diffusion layers 6 and 7 of source/drain regions, forming an interlayer dielectric film 10 on the Ti silicide films, and dry-etching the interlayer dielectric film to form in the interlayer dielectric film 10 a contact hole 10a located above the gate electrode, and contact holes 10b and 10c located above the diffusion layers of the source/drain regions, wherein etching gas used for the dry-etching is gas including at least fluorocarbon gas and one of O2 gas and O3 gas, and the temperature of the semiconductor substrate is 30° C. or lower when the dry-etching is conducted.

Abstract: In a method for manufacturing a semiconductor device in which wiring layers are formed by a damascene method, certain embodiments relate to a manufacturing method and a semiconductor device, in which a bonding pad section having a multiple-layered structure can be formed by a simple method without increasing the number of process steps. One embodiment includes a method for manufacturing a semiconductor device in which at least an uppermost wiring layer is formed by a damascene method.

Abstract: Certain embodiments relate to methods for making a semiconductor device that inhibit the formation of a parasitic device. A method for making a semiconductor device includes a delimiting step and a dopant implantation step. The delimiting step partially oxidizes a single-crystal silicon layer provided on a semiconductor substrate 11 with an insulating layer therebetween to form a plurality of isolated single-crystal-silicon-layer segments 13a delimited by the insulating layer 16. In the implantation step, dopant ions 18 are implanted into the single-crystal-silicon-layer segments 13a to activate the single-crystal-silicon-layer segments 13a. In this implantation step, the dopant is implanted into the single-crystal-silicon-layer segments 13a by an implantation energy which is set so that the position of the maximum of the dopant concentration lies at bottom edges Ea and Eb of each single-crystal-silicon-layer segment 13a.

Abstract: A semiconductor device may include a first wiring layer 30, an interlayer dielectric layer 40 formed above the first wiring layer 30, a second wiring layer 50 formed above the interlayer dielectric layer 40, a through hole 60 formed in the second wiring layer 50 and the interlayer dielectric layer 40, and a contact layer 70 that is formed in the through hole 60 and electrically connects the first wiring layer 30 and the second wiring layer 50.

Abstract: A lubricating perfluoropolyether (PFPE) composition for lubricating one or more disks in a disk drive system may be formed by providing a first component of PFPE molecules having an aggregate vapor pressure in the range of 1×10−6 to 1×10−11 atm and a second component of PFPE molecules comprising at least 5% of the total number of molecules of the first component, wherein the second component includes an aggregate vapor pressure lower than that of the first component. The first and second components are mixed together to form a homogeneous composition, which may be in the liquid form. The composition may be introduced into a reservoir in a vapor phase lubricant reservoir system in a disk drive enclosure.

Abstract: A semiconductor device in certain embodiments includes an insulating layer provided above the upper surface of a semiconductor substrate, and a capacitive element section and a resistance element section formed above the insulating layer. In the capacitive element section, a gate electrode serving as an opposite electrode for the capacitive element is formed above the insulating layer. The gate electrode is covered with a dielectric layer comprising silicon oxide, silicon nitride or tantalum oxide, and an electrode for the capacitive element comprising MoSix is provided above the dielectric layer. The resistance element section has a resistance element comprising MoSix formed simultaneously with the electrode for the capacitive element in the same process.

Abstract: A method for manufacturing a semiconductor device having a non-volatile memory transistor may include the steps of forming a floating gate 22 over a semiconductor layer 10 through a first insulation layer 20, forming a second insulation layer 26 that contacts the floating gate 22, forming a control gate 28 over the second insulation layer 26, forming a source region 14 and a drain region 16 in the semiconductor layer 10, depositing a insulation layer 40 over the semiconductor layer 10, and etching the insulation layer 40 to form a sidewall insulation layer, wherein the etching of the insulation layer 40 is conducted such that the insulation layer 40 remains above the floating gate 40, and the floating gate 22 is not exposed.

Abstract: A semiconductor device may include an element isolation region 14, an npn-type bipolar transistor 200, and a p-type field effect transistor 100, which are formed on a SOI substrate. The bi-polar transistor 200 and the field effect transistor 100 are formed in the same element forming region 16. An n-type body region 52a is electrically connected to an n-type collector region 230. A p-type source region 210 is electrically connected to the n-type collector region 230. A p-type drain region 130 is electrically connected to a p-type base region 220.

Abstract: When a non-volatile memory cell is manufactured, in order to make a semiconductor process for forming a cell transistor to conform to a ferroelectric process for forming a ferroelectric capacitor, in accordance with the present invention, when a non-volatile memory device having a ferroelectric capacitor 18 that is formed from an organic thin film 8 capable of a polarization inversion by an external electric field and provided between a lower electrode 7 and an upper electrode 9, a material solution 80 for the organic thin film 8 is coated over the lower electrode 7 using an ink jet type recording head 15, and is solidified by a heat treatment or the like to thereby form the organic thin film 8. By the manufacturing method, the film forming temperature of the organic thin film 8 becomes to be lower than 150° C.˜200° C., and therefore damages are not inflicted on the cell transistor 17, and a ferroelectric process that conforms to a semiconductor process is provided.

Abstract: A semiconductor device may have an insulating layer comprising a silicon oxide film or the like formed so as to cover an entire upper surface of a semiconductor substrate. A resistance element comprising MoSix is formed on the insulating layer. An insulating film is provided on the surface of the semiconductor substrate above the insulating layer. A through-hole is provided in the insulating film located above the resistance element, and an electrode provided above the insulating film is electrically connected to the resistance element through this through-hole.

Abstract: Examples including non-volatile semiconductor memory devices in which digitized image data and voice data can be more efficiently written and read, and methods for manufacturing the same, are described. In one example, a non-volatile semiconductor memory device 300 may include a first memory element 100 and a second memory element 200 formed in a wafer 11 and mutually isolated by an element isolation region 38, a first impurity diffusion layer 16 and a second impurity diffusion layer 14. The first and second memory elements 100 and 200 include gate dielectric layers 20 and 120, floating gates 22 and 122, selective oxide dielectric layers 24 and 124 and third impurity diffusion layers 15 and 25, respectively, and also include a common intermediate dielectric layer 26 and a common control gate 28, and connected to the first and second impurity diffusion layers 16 and 14 that are commonly shared.

Abstract: An implantable apparatus may include a plug member having a lumen and a valve adapted to open and close the lumen in response to a signal. The apparatus may also include at least one sensor and a controller adapted to control the valve. The controller may be programmable to open the valve to permit the flow of urine under at least one mode of operation selected from a predetermined time interval operation, a sensor operation, and a manual actuation operation.

Abstract: Methods for adjusting the curvature of a slider may include providing a first slider including an air bearing surface and a back surface opposite the air bearing surface. The camber and crown of the first slider are measured, and a plurality of scribes are made at positions on the back surface of the first slider. The change in camber and crown due to each scribe on the first slider is measured. The scribe position and change in crown and camber per position is recorded in a data structure. A second slider is provided, the second slider including an air bearing surface and a back surface opposite the air bearing surface. The camber and crown of the second slider are measured. A desired amount of change in crown and camber is determined. Scribe positions are selected based on information from the data structure so that the desired amount of change in crown and camber will be obtained. The back surface of the second slider is scribed at the selected scribe positions.

Abstract: Certain embodiments relate to a process for forming a multilayer electrical device. The process includes providing a multilayer structure including layers of a dielectric material and an electrode material. The electrode material may include at least one material selected from the group consisting of nickel and copper. A variety of dielectric materials may be used, such as barium titanate. The method also includes sintering the dielectric material by heating the structure using microwaves in an industrial nitrogen atmosphere, which contains an oxygen partial pressure of 10−2 to 10−12 atm.

Abstract: Certain embodiments relate to semiconductor devices having an improved dielectric strength and methods for manufacturing the same. A semiconductor device 1000 may have a field effect transistor 100. The field effect transistor 100 includes a gate dielectric layer 30, a source region 32 and a drain region 34. A semi-recessed LOCOS layer 40 may be provided between the gate dielectric layer 30 and the drain region 34. An offset impurity layer 42 may be provided below the semi-recessed LOCOS layer 40.