Abstract: In a method for manufacturing a semiconductor device in which wiring layers are formed by a damascene method, certain embodiment relate to a manufacturing methods and semiconductor devices, in which a bonding pad section having a multiple-layered structure can be formed by a simple method without increasing the number of process steps.

Abstract: In a memory module arranged with the connection terminals located on both sides of the circuit board, the connection terminals for transmitting a common signal to all memory modules conducts with the connection terminals that are directly facing each other on the opposite sides of the circuit board, and the connection terminals for transmitting an intrinsic signal to the respective memory modules conduct with connection terminals that are not directly facing each other through the circuit board.

Abstract: Certain embodiments provide a method for fabricating a semiconductor device in which a conductive layer containing silicon can be etched in a predetermined shape without adversely affecting a gate insulating film. A method for fabricating a semiconductor device in accordance with the present invention includes forming an oxide film 24 on a p-type silicon substrate 10 and forming a polysilicon layer 26 on the oxide film 24. A stopper layer 28 is formed on the surface of the polysilicon layer 26 and an organic antireflection coating 30 is formed on the surface of the stopper layer 28. A resist layer R is formed on the surface of the organic antireflection coating 30. The method also includes etching the organic antireflection coating 30 using the resist layer R as a mask and etching the stopper layer 28. The polysilicon layer 26 is also etched in a predetermined pattern to form a gate electrode.

Abstract: Embodiments include a semiconductor device including a well structure such that well areas can be formed with a higher density of integration and a plurality of high-voltage endurable transistors can be driven independently of one another with different voltages, and a method of manufacturing the semiconductor device. The semiconductor device may include a triple well comprising a first well formed in a silicon substrate and having a first conductivity type (P-type), a second well formed in adjacent relation to the first well and having a second conductivity type (N-type), and a third well formed in the second well and having the first conductivity type (P-type). A high-voltage endurable MOSFET is provided in each of the wells. Each MOSFET has an offset area in the corresponding well around a gate insulating layer. The offset area is formed of a low-density impurity layer which is provided under an offset LOCOS layer on the silicon substrate.

Abstract: A semiconductor memory device may be formed from a pair of transfer MOS transistors 1, 2 controlled by a word line 11 and a pair of data retaining flip-flop circuit formed from serially connected load elements 5, 6 and drive MOS transistors 3, 4. In the semiconductor memory device, the transfer MOS transistors 1, 2 have a threshold voltage greater than a threshold voltage of the drive MOS transistors 3, 4. The memory device may display an improved &bgr; ratio, and reduce the size of the drive MOS transistors to thereby reduce the cell area.

Abstract: Embodiments include a manufacturing method for a semiconductor device which can suppress a concave from being generated in an upper area of a wiring layer at a position above plug. The method may include the steps of (a) forming an impurity diffusion layer 34; (b) forming, on the impurity diffusion layer 34, an interlayer insulating layer 40 having at least one. through hole 42; (c) forming a plug 50 in the through hole 42; (d) forming an underlying layer 62 on the plug 50 and the interlayer insulating layer 40, and (e) forming an aluminum layer 64 on the underlying layer 62, the aluminum layer 64 being formed at a substrate temperature not lower than 250° C. and under a reduced pressure.

Abstract: Embodiments relate to a non-volatile semiconductor memory device in which the interface state between the tunnel insulation layer and the floating gate and the interface state between the tunnel insulation layer and the control gate are lower, the operation characteristics are stable, and the data writing/erasing cycle life is long. A non-volatile semiconductor memory device (memory transistor) 400 may include a non-volatile semiconductor memory device with a split-gate structure having a source 16, a drain 14, a gate insulation layer 26, a floating gate 40, an intermediate insulation layer 50 that functions as a tunnel insulation layer, and a control gate 36. The intermediate insulation layer 50 is composed of at least three insulation layers 50a, 50b and 50c. The first and the second outermost layers 50a and 50c of the three insulation layers respectively contact the floating gate 40 and the control gate 36, and are composed of silicon oxide layers that are formed by a thermal oxidation method.

Abstract: Embodiments include a method for forming a glass which displays visible cracking prior to failure when subjected to predetermined stress level that is greater than a predetermined minimum stress level and less than a failure stress level. The method includes determining a critical flaw size in the glass and introducing a residual stress profile to the glass so that a plurality of visible cracks are formed prior to failure when the glass is subjected to a stress that is greater than the minimum stress level and lower than the critical stress. One method for forming the residual stress profile includes performing a first ion exchange so that a first plurality of ions of a first element in the glass are exchanged with a second plurality of ions of a second element that have a larger volume than the first ions. A second ion exchange is also performed so that a plurality of the second ions in the glass are exchanged back to ions of the first element.

Abstract: One embodiment enables detection of MI/I and emerging infarction in an implantable system. A plurality of devices may be used to gather and interpret data from within the heart, from the heart surface, and/or from the thoracic cavity. The apparatus may further alert the patient and/or communicate the condition to an external device or medical caregiver. Additionally, the implanted apparatus may initiate therapy of MI/I and emerging infarction.

Abstract: In a method for manufacturing a semiconductor device in which wiring layers are formed by a damascene method, certain embodiments relate to a manufacturing method and a semiconductor device, in which a bonding pad section having a multiple-layered structure can be formed by a simple method without increasing the number of process steps. One embodiment includes a method for manufacturing a semiconductor device in which at least an uppermost wiring layer is formed by a damascene method.

Abstract: Embodiments include semiconductor devices and methods of manufacture, one of which includes a capacitor unit formed on a silicon substrate. The capacitor unit is divided into a plurality of capacitor subunits which are partitioned from each other by a separating insulation layer. Each of the capacitor subunits includes a first electrode layer composed of an impurity diffusion layer formed in the silicon substrate, a second electrode layer composed of a conductive polysilicon layer and a dielectric layer composed of a silicon oxide layer interposed between the first electrode layer and the second electrode layer. The respective capacitor subunits are connected in parallel to each other through a connector.

Abstract: Certain embodiments provide a plasma etching apparatus and a method for detecting the end point of plasma etching, which can more accurately detect the end point of plasma etching. A radiofrequency wave generated in a radiofrequency generating system 5 propagates through a lead line 30 and is applied to a cathode 9 in a plasma chamber 1. Plasma 11 thereby is generated in the plasma chamber and selectively etches a semiconductor wafer 12. A RF probe 8 measures the voltage and current of the radiofrequency wave flowing in the lead line 30. A determination system 15 may determine the end point of the plasma etching on the basis of either the voltage or current, whichever changes first.

Abstract: In certain embodiments a plasma is supplied from a plasma chamber 10 into a reaction chamber 18 of a plasma CVD apparatus. An electrode 22 is disposed in the reaction chamber 18. A semiconductor wafer on which a thin film is to be formed is placed on the electrode 22. A radio-frequency wave is generated by a radio-frequency wave generator 28 and supplied to the electrode 22 via a radio-frequency matching network 30, a blocking capacitor 32, and an RF probe 34 so as to control the plasma in the plasma chamber 10. A judgment device 38 is electrically connected to the RF probe 34. The voltage and current are be measured by the RF probe and the judgment device 38 is used to judge the state of the plasma in the plasma chamber 10.

Abstract: Embodiments relate to reduced VOC hair spray compositions. One composition includes a concentrate and propellant. The concentrate includes 25-45 weight percent alcohol, 30-50 weight percent methyl acetate, 5-15 weight percent resin, 0.2-1.3 weight percent neutralizer, and 5-25 weight percent water. The propellant comprises dimethyl ether. The composition includes 50 to 90 weight percent concentrate and 10 to 50 weight percent propellant.

Abstract: Embodiments include a method for manufacturing a semiconductor device including a plurality of non-volatile memory transistors that include field effect transistors operated at a plurality of different voltage levels. The method includes the following steps: (a) forming a gate insulation layer 26 and a floating gate 40 of a non-volatile memory transistor 400 on a silicon substrate 10 in a memory region 4000; (b) forming, on the wafer, a first silicon oxide layer 50aL by a thermal oxidation method and a second silicon oxide layer 50bL by a CVD method; (c) removing the first and the second silicon oxide layers in the first transistor region; and (d) forming a silicon oxide layer 20L on the wafer by a thermal oxidation method. The silicon oxide layer formed in step (d) compose at least a portion of a gate insulation layer of a first voltage-type transistor and a gate insulation layer of a second voltage-type transistor.

Abstract: Embodiments include a liquid colorant composition having an acrylates/octylacrylamide copolymer, a cellulose material, alcohol and a colorant. The cellulose material may be hydroxypropylcellulose. Isostearyl alcohol and silica may be included in the composition to enhance properties such as the spreadability and feel of the composition on the lips. Additional additives such as fragrance and botanical extracts may also be added. Such compositions can be easily applied to the lips and offer long wear characteristics.

Abstract: Certain embodiments provide a manufacturing method for a semiconductor device, in which an organic antireflection film can be etched while a resist layer maintains dimensions thereof. The method includes forming an oxide layer 24 on a p-type silicon substrate 10, and forming a polysilicon layer 26 on the oxide layer 24. An organic antireflection film 30 is formed on the polysilicon layer 26, and a resist layer R having a predetermined pattern is formed on a surface of the organic antireflection film 30. The method as includes etching the organic antireflection film 30 by using the resist layer R, in which an etching gas includes at least one of an oxygen-based gas and a chlorine-based gas, and forming a gate electrode by etching the polysilicon layer 26 with a predetermined pattern.

Abstract: Embodiments include a method for fabricating a nanograined component from a nanograined powder composition. A compact is formed from the nanograined powder composition and sufficient heat is applied to the compact to generate at least one exothermic reaction while the compact is at a temperature lower than its eutectic temperature. Pressure is applied to the powder compact during the heating operation to consolidate the powder compact. The application of heat and pressure are controlled to inhibit grain growth and form a component having a nanograined microstructure that is at least 98 percent dense at a temperature lower than the eutectic temperature.

Abstract: A semiconductor device 100 has a substrate 11 including a high breakdown voltage transistor region where transistors with high breakdown voltage and high dielectric strength Qn and Qp are formed and a low breakdown voltage transistor region where transistors with low breakdown voltage and low dielectric strength are formed. The transistors with high voltage breakdown and high dielectric strength Qn and Qp and the transistors with low voltage breakdown and low dielectric strength operate at different voltages. In the high breakdown voltage transistor region, the semiconductor device has metal wiring layers 19a and 19b that are fed with a high potential. The metal wiring layers 19a and 19b are provided over the transistors with high voltage breakdown and high dielectric strength Qn and Qp through a first interlayer dielectric film 16 and a second interlayer dielectric film 17. An element isolation dielectric region 14 is provided over the substrate 11.

Abstract: In a method for manufacturing a semiconductor device in which wiring layers are formed by a damascene method, certain embodiment relate to a manufacturing methods and semiconductor devices, in which a bonding pad section having a multiple-layered structure can be formed by a simple method without increasing the number of process steps.