Abstract: In a loudspeaking telephone it is necessary to ensure that pick-up by the microphone of sound from the loudspeaker does not set up a howling condition. To do this it is usual to disable either the transmitting or the receiving speech channel.To do this, the signal from each channel is applied to an analogue-digital signal envelope converter (30,31), which generates a multi-bit word representative of the current speech amplitude in its channel. Those words are applied to a comparator (32) whose output is indicative of which channel passes speech. Such a converter follows the envelope of the speech signal in its channel to produce the multi-bit word representing the current speech amplitude in its channel. The comparator's output goes via control logic (33) to two attenuators (34, 35), one in each channel. Thus only the channel which is actually passing speech, or the one with the higher speech amplitude, is enabled.

Abstract: A line switch for a digital telephone switching system utilizes distributed processing. The line switch comprises one or more switch modules. Each switch module is coupled to a central office switching system via one or more PCM lines which utilize common channel signaling. Each switch module comprises groups of line circuits, each line circuit being coupled to a subscriber line. Three separate distributed processor functions are provided in each line switch module. A first processor is utilized to communicate with the central office switching system and to coordinate the operations within the line switch module. A second processor is provided to control clock generation and rate conversion circuits. Each group of line circuits includes a third processor to control the operations of the line circuits and to gather information from the line circuit. A busing arrangement is provided within the line switch such that both control information and PCM voice data are routed throughout the line switch.

Abstract: Circuit for controlling the operation of a handsfree or loudspeaking telephone instrument. The circuit includes an integrated circuit dual tone multifrequency (DTMF) generator. When a button of the generator is depressed, and the instrument is in its handsfree mode, power feed to the generator and the speech network is activated. The tone generation circuitry and speech network are thereby connected in parallel with the handsfree hybrid. When the DTMF button is released, power to the speech network is discontinued. Further, when the instrument is in the handsfree mode, and in the non-dialing condition, the confidence tone muting resistance is shunted so that no voice signal attenuation to the handsfree hybrid can occur. The switching is protected against surges both in the handsfree and hookswitch on and off hook conditions and is protected against leakage at the start of the DTMF output.

Abstract: A conference circuit for controlling one or more conferences within a digital time division telecommunications system. The conference circuit uses the generally known loudest speaker approach. Within the circuit, the address and loudness level of the loudest speaker for each conference in progress in the system during each time division frame is stored in memory. If the loudness level of a conference is not exceeded during a succession of frames, the level is allowed to decay by a percentage of the loudness indication stored at the end of that succession.

Abstract: The electrodes of an electron-gun system of a color-picture tube are heated less as their distance from the cathode of the system increases. The electrode materials are so chosen with respect to their coefficients of expansion that no mechanical stresses are caused in the system structure despite the different temperatures.

Abstract: A line switch for a digital telephone switching system utilizes distributed processing. The line switch comprises one or more switch modules. Each switch module is coupled to a central office switching system via one or more PCM lines which utilize common channel signaling. Each switch module comprises groups of line circuits, each line circuit being coupled to a subscriber line. Three separate distributed processor functions are provided in each line switch module. A first processor is utilized to communicate with the central office switching system and to coordinate the operations within the line switch module. A second processor is provided to control clock generation and rate conversion circuits. Each group of line circuits includes a third processor to control the operations of the line circuits and to gather information from the line circuit. A busing arrangement is provided within the line switch such that both control information and PCM voice data are routed throughout the line switch.

Abstract: An asynchronous digital TDM multiplexer-demultiplexer combination at one communication terminal is capable of multiplexing N asynchronous input data signals having a random mixture of different bit rates into a transmitted synchronous data stream having a predetermined fixed data format and a given bit rate greater than the sum of the rates of the different rates and to demultiplex N asynchronous output data signals having the same random mixture of the different bit rates from a received synchronous data stream having the data format and the given bit rate, where N is an integer greater than 1.

Abstract: The arrangement to support a waveguide for transportation and handling and to support and protect a horizontal waveguide having a plurality of waveguide sections connected to each other in tandem suspended between two given spaced points comprises a plurality of shrouds each encasing a substantial length of a different one of the plurality of sections for support and protection thereof and a suspension means fastened to each end of each of the plurality of shrouds to suspend each of the plurality of waveguide sections from a cable extending between the two given spaced points.

Abstract: The source wavelength dependent delay produced in a single mode fiber is equalized by causing the emergent light beam therefrom to be incident on a dispersion element which is such as to transmit the beam of light at an angle or position dependent on the source wavelength. The transmitted beam of light is launched into a length of multimode fiber such that the beam emergent therefrom is equivalent to the single mode fiber emergent beam but with the delay thereof equalized. If the multimode fiber is step index fiber the transmitted light at which the delay is the least is launched thereinto at the maximum angle, whereas the transmitted light at which the delay is the most is launched thereinto along the axis thereof. Alternatively, a graded index fiber can be employed for the multimode fiber.

Abstract: Feedback equalization is employed for digital repeaters of transmission systems having twisted-wire pairs, in order to reduce intersymbol interference while minimizing near-end crosstalk gain. Previously the incoming signal was selectively amplified at the higher frequencies in order to negate intersymbol interference, with subsequent near-end crosstalk gain. According to the present invention the intersymbol interference element of an incoming signal is cancelled, prior to amplification in an adder by a compensation signal derived from the output signal of a regenerator and a retimer. An output stage serves to amplify and shape the resultant signal to a form suitable for transmission. The compensation signal comprises the inverted output of a filtering and scaling network.

Abstract: A digital filter arrangement in which an input pulse stream is entered in consecutive non-overlapping groups into a first shift register. The contents of the first register are transferred in parallel into a plurality of shift registers. Bits are read-out from selected positions of the plurality of shift registers to form address words for individual read-only memories (ROM). Each ROM has stored therein weighted impulse response outputs which are read out in accordance with the address words. The outputs from the ROM's are added in logic circuitry and the combined output is fed into a latch. The contents of the latch are entered into a buffer from where they are read out serially. If the input clock rate is 28 MHz and the plurality of shift registers number eight, the plurality of shift registers, the ROM's and the logic circuitry operate at 3.5 MHz.

Abstract: The digital demodulation of frequency modulated signals produces a pulse duration modulated signal proportional to the analog modulation signal component of the FM input signal from the FM input signal and a delayed version thereof and the pulse duration modulated signal is then converted to a digital signal representative of the analog modulation signal component of the FM signal by a delta sigma modulator and a decimator which also provides equalization of the FM signal to remove pre-emphasis applied to the FM signal prior to its transmission.

Abstract: Ashing rates of encapsulants exposed to an oxygen plasma in a reactor are increased by simultaneously exposing a solid halogen-substituted hydrocarbon polymer to a plasma jet formed within a cavity in a grounded conductive surface of the reactor. Advantageously the solid reactant may be polyvinyl chloride or polytetrafluorethylene in solid form.

Abstract: In a PCM system, it is desirable for the two ends to remain in synchronization, and for this purpose both channel associated and non-channel associated synchronizations are used.The PCM code combinations are eight bit codes, each with a ninth bit for sync and a tenth bit for data. When sync search is in progress, either at switch on or after sync has failed, the seventh and eighth bits of the PCM code bits are used to convey additional sync thus reducing the risk of simulation. To locate the sync, all other bits except the sixth and tenth bits are set to zero, the sixth and tenth bits being at one. Thus, two ones are separated by five zeros to form a pointer used to locate the sync pattern. The sync pattern is located by storing a data frame on reception and shifting it to find the combination of two ones separated by five zeros. The shift needed to find the combination indicates the extent of misalignment and is used to bring the receiver clock into alignment with the incoming bit streams.

Abstract: A common controller in the form of a programmed digital sequencer executes a series of instructions to control multiplexing-demultiplexing overhead channel format generation, frame synchronization stuff-destuff operation and automatic channel assignment in a digital TDM multiplexer-demultiplexer combination at one communication terminal to enable multiplexing N input data signals each having a predetermined bit rate into a transmitted synchronous data stream having a predetermined fixed data format and a given bit rate greater than the sum of the predetermined bit rates and to demultiplex N output data signals each having the predetermined bit rate from a received synchronous data stream having the data format and the given bit rate, where N is an integer greater than one.

Abstract: A sensor arrangement is disclosed for detecting the presence of an axle of a rail vehicle in a short length of a track. The arrangement includes a bridge coupled to and including resistances of the rail upon which the vehicle travels. This bridge is unbalanced by wheels of an axle shunting resistance of the bridge with the bridge unbalance producing an output indicative of the presence of the axle. Two such arrangements displaced relative to each other will enable detecting the direction of movement of the vehicle. This sensor arrangement contains no electric components on the rail and is insensitive to interference from rail currents and electromagnetic rail brakes.

Abstract: A facility for fail-safe data transmission between trackside equipment of a guideway and vehicles moving therealong is disclosed which transmits two identical data records held in two independent storage arrangements in the trackside equipment to a data receiver in the vehicle according to fail-safe principles. Error protection of the data is provided by means of a cyclic code. To enable monitoring the transmitting equipment for component failures from the receiving equipment, a special bit group is transmitted whose bits are checked for equivalence in the receiving equipment.

Abstract: The switching network includes in one or more planes MN switching means arranged in M rows and N columns, where M and N are even integers, first intermediate switching devices associated with the M rows and second intermediate switching devices associated with the N columns. Each intermediate switching device associated with a given column is coupled to a different one of the M rows and each intermediate switching group of the second intermediate switching device is coupled to a different one of the N columns. Each of the MN switching means has a first plurality of ports coupled to a plurality of digital terminals, a second plurality of ports associated with a different one of the M rows and a third plurality of ports associated with a different one of the N columns.

Abstract: The digital supervisory circuit comprises an amplitude comparator and EXCLUSIVE-OR gate to provide an output signal indicating the difference in time an input signal is above and below a predetermined reference potential. This output signal is integrated in an up-down binary counter and also is coupled to a first logic circuit under control of the counter which provides a ring present supervisory signal when a first threshold is exceeded and a second logic circuit under control of the counter which provides a switch hook detection supervisory signal when a second threshold is exceeded. A hit-timing circuit is provided coupled to the counter and the first and second logic circuits to prevent response of the counter and second logic circuit to line transients.

Abstract: A binary data transmission system uses a code consisting of n-bit code words of a quasi-cyclic code with k information bits and n-k check bits. An encoder and a decoder with an error-detection and -correction facility are provided which use a quasi-cyclic code that has a high error-correcting capacity and requires little storage space.