Abstract: Generally and in one form of the invention this is a periodic surface filter comprising at least one element at a surface of the filter and electronic controls to change the optical characteristics of the element. Other methods and devices are disclosed.

Abstract: An analog signal monitoring (ASM) circuit (40, 42) non-intrusively monitors an analog circuit (20) within an electronic system. The ASM circuit (40,42) comprises input circuitry (80) that receives a plurality of analog signal inputs while the analog circuit (20) operates in a functional mode. Translation circuitry (142) associates with the input circuitry (80) for converting the analog signal inputs into digital signal representations of the analog signal inputs. Output circuitry (58) associates with the translation circuitry to output the digital representations. Control circuitry (114) controls the translation and output circuitry while the analog circuit (20) is in a functional mode. The ASM circuit (40, 42) also include an event qualification circuit (68) that includes input circuitry (236) to receive the digital signal representations, compare circuitry (104) to compare the received digital representations to an expected value and output a matched signal when a compared condition is identified.

Abstract: A protocol and associated circuitry operable for efficiently extending serial bus capability into multi-level system environments is disclosed. The protocol is designed to coexist and be fully compatible with existing serial bus approaches, or being used as a standalone serial communications bus. The circuitry and protocol described enable the use of a common serial bus in a hierarchically arranged system or network, so that a primary serial bus master device can selectively access any device at any level or position in the network, and send and receive messages and commands to and from the device. The invention disclosed accomplishes this without modifying the existing serial bus protocol, without adding additional signals and without affecting the throughput rate of the serial bus it may be used with. Alternative embodiments applying the invention to a cabled system are described. Additional preferred embodiments are also disclosed.

Abstract: A method of manufacturing semiconductor devices with increased operating voltages is described. A dopant of a second conductivity type is implanted into a region of a first epitaxial layer of the first conductivity type to form a buried layer. A substantially smaller dosage of a faster-diffusing dopant of the second conductivity type is then implanted into the buried layer region. The second epitaxial layer of the first conductivity type is formed over the first epitaxial layer. A region of the second epitaxial layer overlying the doped region of the first epitaxial layer is implanted with a dopant of the second conductivity type and diffused to form a doped well. The faster-diffusing dopant diffuses upward to make good electrical contact with the doped well diffusing downward from the surface. The lateral diffusion of the faster-diffusing dopant can be contained, so that lateral spacing design rules do not have to be increased.

Abstract: A method of fabricating a focal plane array having an integral slot shield which comprises fabricating a focal plane array having a plurality of detector elements. A layer of electrically insulating material, preferably a spun on epoxy, having a planar top surface is then formed over the array. A reflective layer is then formed over the layer of electrically insulating material and the electrically insulating layer and reflective layer are etched only in the regions thereof over the detector elements to form slots over said detector elements. The electrically insulating layer is etched with a directional etchant. The etched layer of electrically insulating material defines side walls in the slots, material from the side walls being removed to define non-planar sidewalls. The non-planar side walls preferably have an essentially sawtooth shape.

Abstract: A function array system includes a controller, a test function and specific memories to accelerate the execution of a VLSI device test program by preloading register files associate with each hardware function in the tester with test set-up information. Test information is transferred to the register files only once when the test program is initially downloaded into the tester. A simple controller sequences a test set-up pointer during test execution.

Abstract: A technique is described for improving the sampled current accuracy in current mirror circuits such as are often used to monitor the current output to a load. A reference voltage is established to feedback the load voltage conditions at the output to the current reference circuitry, thereby greatly reducing the error in the reference current over that which is produced by prior art circuits. The technique is shown as applied to a current limiting circuit for driving an output load. An alternative embodiment is also disclosed.

Abstract: The present invention relates to a method of manufacturing a semiconductor integrated device and, more particularly, to a semiconductor integrated device having NPN and PNP power and logic devices combined with complementary MOS and DMOS devices. The present invention is a multipitaxial process for fabricating a high power/logic complementary bipolar/MOS/DMOS (CBiCMOS) integrated circuit. The process steps for fabricating the novel integrated circuit combines on the same substrate complementary high power, logic/analog bipolar transistors with complementary MOSGVm devices and DMOSFET devices. The present invention optimizes the characteristics of these different transistors in a single process flow. The present high power/logic CBiCMOS multiepitaxial process results in device structures having distinct technical advantages over prior art processes and structures heretofore known.

Abstract: A sequential memory (10) uses interleaved memories (12a-b) with associated output buffers (22a-b) accomplish high data rates. Data access control circuitry (18) and bank select circuitry (20) control the order in which the memory banks (12a-b) are written to and read from. Output buffer circuits (22a-b) allow a data word to be read instantaneously after it is written to the sequential memory (10).

Abstract: An infrared or x-ray imaging CCD array, including deep trench isolation (56) for capturing electron carriers formed deep in the substrate (46) as a result of long wavelength radiation or high energy particles. In virtual phase CCD circuits, the trench has formed on the sidewalls thereof a diffusion (58, 60) defining a vertical conductor for allowing hole carrier conduction between the substrate (46) and the virtual phase electrode (38).

Abstract: A method and circuitry are provided for latching a logic state. A first signal (64) indicates a logic state of an input signal (D) in response to a first transition of a clock signal (72). A second signal (68) indicates a logic state of the first signal (64) in response to a second transition of the clock signal (72). An output signal (Q) indicates the logic state of the first signal (64) in response to the second transition and indicates a logic state of the second signal (68) in response to the first transition.

Abstract: A data access controller (10) is comprised of a control circuit (12) and an output data latch (14). The control circuit (12) receives a READ and WRITE signal (30,32) and produces a plurality of control signals (22). The output data latch (14) allows either incoming data (24) or data from a memory (16) to be propagated to the output for data access depending on the state of the control signals. The data access controller (10) enables faster data access of first in, first out memory structures.

Abstract: An (10) and method is provided for bonding wire (12) to the bond sites (28) of integrated circuits (14). In preferred embodiments gold wire (12) is bonded to aluminum bond pad (28). Apparatus (10) includes a high frequency ultrasonic energy source (20) designed to provide ultrasonic energy at frequencies above about 125 kHz. The ultrasonic energy is imparted to the bonding interface (32) via transducer (18) and capillary (16). The transducer is modified in length and tool clamp point (40) is sited on transducer (18) so that the wavelength of the high frequency ultrasonic energy is at the antinodal point in its application to interface (32) and thus is optimized. In the preferred embodiments of the process the ultrasonic energy is applied at about 350 kHz at ambient temperature. In this fashion, the bond formed between bond end (30) and bond pad (28) is optimized in terms of shear strength, bonding time and processing temperatures.

Abstract: A clock stability circuit (10, 20, 30, 40) assures stable clock generator operation after oscillator start-up, such as during re-entry after a low-power Halt mode in a microprocessor or microcomputer. The clock stability circuit detects stable clock cycles that transition between a selected high amplitude threshold (near VDD) and a selected low amplitude threshold (near VSS), and provides a clock stable signal after a selected number of stable clock cycles, indicating that the oscillator has stabilized. The clock stability circuit includes four modules: input sampler (10), pulse generator (20), pulse counter (30) and control logic (40). The input sampler module includes CMOS NAND gates (11, 14) respectively fabricated with p/n-channel ratios to provide a CLOCK A signal that transitions at the selected high amplitude threshold of an oscillator cycle, and a CLOCK B signal that transitions at the selected low amplitude threshold.

Abstract: A lead over chip packaged device that is less prone to package cracking during surface mounting is disclosed. The lead over chip lead frame overlies the active face of a semiconductor circuit. The backside of the semiconductor circuit is covered with an aminopropyltriethoxysilane coating. The aminopropyltriethoxysilane coating promotes adhesion between the backside of the semiconductor circuit and the mold compound used to encapsulate the device. This reduces package cracking resulting from delamination between the inactive face of the chip and the mold compound during reflow solder.

Abstract: The method is provided for selectively fabricating erasable read-only memory and read-only memory cells at a face of a layer of semiconductor of a first conductivity type. Active areas on the face of the layer of semiconductor are selectively defined by masking the face of the layer of semiconductor and patterning and etching the mask to expose first and second areas of the layer of semiconductor. A layer of conductor is formed insulatively adjacent the active area of each cell being fabricated. The layer of conductor is patterned and etched to define a first level gate conductor adjacent at least a portion of the active area of each cell being fabricated, the first level gate of each read-only memory cell set to a logic zero being fabricated disposed adjacent a one of the insulator regions adjacent a corresponding one of the third exposed areas. A layer of interlevel insulator is formed adjacent the first level gate of each erasable read-only memory cell being fabricated.

Abstract: A floating point processor (10) is provided having a multiplier (48) and an ALU (54) for performing arithmetic calculations simultaneously. The output of the multiplier (48) and ALU (54) are stored in a product register (64) and a sum register (66), respectively. Multiplexers (40,42,44,46) are provided at the inputs to the multiplier (48) and the ALU (54). The multiplexers choose between data in input registers (32,34), product and sum registers (64,66), and an output register (76). Since the multiplier (48) and ALU (54) operate simultaneously, and since the outputs of the multiplier (48) and ALU (54) are available to the multiplexers (40-46), product of sums calculations and sum of products calculations may be performed rapidly. An input stage (12) uses a temporary register (18) to store data from a data bus on the first clock edge, and configuration logic (28) for directing data from the data bus and the temporary register (18) to the input registers (32,34) on a second clock edge.

Abstract: A vacuum storage cassette for semiconductor wafers has one or more valves to allow the cassette to be evacuated, backfilled, and opened to the surround atmosphere and resealed without the need for a vacuum load-lock chamber.

Abstract: Via patterns (16, 18) are applied to a first interlevel oxide layer (58) down to a metal layer (52) to define a plurality of orifices. These orifices (61, 63) are filled with tungsten by selective chemical vapor deposition. A first level conductor pattern (10, 12, 14) is then used to etch away the first insulator layer (58) and portions of plugs (62, 64) that are outside the first level conductor pattern. This first level conductor pattern is also used for a subsequent first level metal etch. The entire structure is then covered with a self-planarizing oxide layer (82), which is subsequently etched back to expose the top surfaces (66, 68) of tungsten plugs (62, 64).

Abstract: A multiple frequency oscillator responds to a control signal to selectively produce an output signal having a first frequency or a second frequency. The oscillator includes a plurality of inverter stages (48.sub.1 -48.sub.5) with the input of each inverter stage coupled to the output of another inverter stage. At least one of the inverter stages includes first and second transistors (50,51) having current paths connected in parallel, a third transistor (52) having a current path connected in series with the current paths of the first and second transistors (50, 51) between a first voltage source (Vdd) and the inverter stage output, and a fourth transistor (53) having a current path connected between the inverter stage output and a second voltage source (Vss). The control electrodes of the first, third, and fourth transistors (50, 52, 53) are connected to the input of the inverter stage.