Abstract: An improved digital-to-analog conversion circuit (10) comprises digital circuitry (12) for receiving digital input signals from a digital input signal source, conversion circuitry (42) receiving the digital input signals and producing analog output signals and analog output circuitry (44) for sending analog output signals to an analog output signal load. The conversion circuit (10) includes calibration circuitry (46) that samples analog output signals from analog output circuitry (44) and includes a reference signal source (52) for producing a plurality of reference signals. A comparator (50) compares a predetermined aspect of the analog output signals to the reference signals to produce therefrom a plurality of difference signals. Correction circuitry includes error detection circuit (95) that includes a successive approximation register (62) and a digital controller (66) for receiving the difference signals and a digital interpolator (26) for generating a plurality of correction signals.

Abstract: An integrated circuit is formed on an N-type semiconductor wafer having a first N-type epitaxial layer on the substrate, a P-type epitaxial layer over the first N-type epitaxial layer, and a second N-type epitaxial layer over the P-type epitaxial layer. There are also a plurality of sets of P-type isolation regions separating the P-type epitaxial region and the surface of the second N-type epitaxial region into epitaxial tank regions for formation of bipolar and CMOS devices, combining high power, low power, logic, switching, analog, high current, low current, digital, and linear bipolar transistors along with CMOS transistors. The characteristics of the different type of devices are combined into a single process flow.

Abstract: An output buffer (12) is provided for producing an output signal varying between a voltage on a first lien (22) and a voltage on a second line (36). First output circuitry (3, 4) is provided for pulling an output terminal (26) to the voltage on first line (22). Second output circuitry (6, 7) is provided for pulling output terminal (26) to the voltage on second line (36) in response to an input thereto. First feedback circuitry (2, 8) is provided for detecting a voltage spike on first line (22) and varying the input to first output circuitry (3 4) in response. Second feedback circuitry (5, 9) is provided for detecting a voltage spike on second line (36) and varying the input to second output circuitry (6, 7) in response.

Abstract: A pattern sequence control system utilizing a control RAM to provide pattern control information only when a change in pattern sequence control is required, thereby significantly reducing the amount of pattern control memory required. The pattern sequence control system utilizes a single pattern address counter for sequential patterns and a single loop address counter for looping pattern. The pattern address counter and loop address counter provide the pattern memory address for all pattern memory regardless of the number of tester channels. A cycle counter determines the number of test cycles that a sequential pattern or repeating pattern will be applied. A loop length counter and loop counter are used to control pattern looping.

Abstract: A synchronized pulsed look-ahead circuit (10 in FIG. 1) effects look-ahead operations for a flip-flop (20). It includes a LAPP section (12) and a DATA sense and control section (14). To initiate a look-ahead operation, the LAPP section triggers in synchronism with the control edge of CLK, swtiching the LAPP line active and enabling the DATA sense and control section. While enabled, the DATA sense and control section receives DATA IN, and depending on its phase, provides the appropriate logic levels to the DATA output driver, which then provides the appropriate DATA OUT. When the flip-flop has latched the DATA and is ready to assume control of the DATA OUT line, i.e., after the associated propagation delay, the LAPP pulse is terminated and the DATA sense and control section is disabled, terminating the look-ahead operation.

Abstract: A bipolar transistor and method of making the same is disclosed. The transistor has an emitter region which is diffused from polysilicon into the intrinsic base region, where the polysilicon is doped with two dopant species of different diffusivity. The impurity concentration of the higher diffusivity species, for example phosphorous, can be selected to define the emitter junction depth, which is preferably shallow, while the impurity concentration of the lower diffusivity species, for example arsenic, can be selected to provide a high conductivity emitter electrode, as well as reduce the sensitivity of the emitter electrode to counterdoping from the implantation of the extrinsic base region. The structure is compatible with BiCMOS processing, as the same anneal can be used to diffuse the emitter and the source/drains of the MOS transistors, with the emitter junction depth optimized via the implant conditions of the higher diffusivity species.

Abstract: A transistor for VLSI devices employs a phosphorus implant and lateral diffusion performed after the sidewall oxide etch to thereby reduce the impurity concentration and provide a graded junction for the reach-through implanted region between heavily-doped N+ source/drain regions and the channel, beneath the oxide sidewall spacer.

Abstract: A floating gate junction filed-effect transistor image sensor element (10) is formed in a semiconductor layer (14). a drain region (20) of a first conductivity type of the elements (14) is formed adjacent a gate region (26). A potential barrier (98) is formed in the gate region (26) fo rcollecting carriers (102) of the second conductivity type, the barrier (98) also acting as a probing current well. A capacitor (28, 32, 48) is coupled to the gate region (26) and is operable to deliver a pulse to gate region (26) for sweeping out the carriers (102) to the substrate (12). The difference in gate bias voltage caused by the absence of the collected carriers (102) is sensed at a sense node (116) coupled to a source region (30).

Abstract: A plurality of power driver modules are removably mounted on a circuit board which interfaces with a computer control system. The input/power driver output switches in each module use optical coupling. A controller sets the power switches according to instructions from the computer control system, and the system can determine the set state of the power switches by reading a set state memory or directly determining the actual state of the switches by reading the switch state from an input circuit on the input/output power driver module.

Abstract: A CMOS process wherein lightly doped drain extensions are fabricated in the N-channel devices without any additional masking steps. The present invention requires a specific sequence of steps, after all steps through patterning of the polysilicon gate level have been completed: first, a light shallow N-type implant is performed overall. Next, oxide is deposited overall. Second, photoresist is patterned according to the P-type source/drain mask. The exposed conformal oxide is etched away completely, and the P-type source/drain implant is performed. Third, after the P-type source/drain photoresist is removed, the conformal oxide is anisotropically etched to leave sidewall oxide filaments, the N+ source/drain masking layer is applied, and the N+ source/drain implant is performed. This process results in short lightly doped drain extensions on the source/drain regions of the N-type devices only and not of the P-type devices.

Abstract: A processing apparatus and method wherein a wafer is exposed to activated species generated by a first plasma which is separate from the wafer, but is in the process gas flow stream upstream of the wafer, and is also exposed to plasma bombardment generated by a second plasma which has a dark space which substantially adjoins the surface of the wafer. The in situ plasma is relatively low-power, so that the remote plasma can generate activated species, and therefore the in situ plasma power level can be adjusted to optimize the plasma bombardment. Ultraviolet light to illuminate the face of a wafer being processed is generated by a plasma which is within the vacuum chamber but is remote from the face of the wafer and controlled independent of the in situ plasma. It is useful to design the gas flow system such that the ultraviolet-generating plasma has its own gas feed, and the reaction products from the ultraviolet-generating plasma do not substantially flow or diffuse to the wafer face.

Abstract: A vacuum storage cassette for semiconductor wafers has one or more valves to allow the cassette to be evacuated, backfilled, and opened to the surround atmosphere and resealed without the need for a vacuum load-lock chamber.

Abstract: An amplification circuit in accordance with the present invention includes an amplifier comprising four inputs. Each of the four inputs is operable to receive a respective analog signal and a respective DC bias signal. Also included is supply circuitry for providing a first and second controlled DC bias signal. Each of the DC bias signals is operable to couple to selected ones of the four inputs of the amplifier.

Abstract: A semiconductor device and package includes a tape mounted semiconductor chip using bumped contacts, the top side of the chip is covered with a thin layer of ultra violet transmissive material, and a plastic removable frame surrounds the device and is removed after testing the device and prior to mounting the device on a printed circuit board.

Abstract: A hybrid CMOS-bipolar memory cell for a high speed memory includes a CMOS latch which has two storage nodes (104) and (106) for storing two logic states. The CMOS latch is disposed between a high voltage node (110) and a low voltage node (114). The two nodes are maintained at a predetermined voltage to maintain a static state. A bipolar current drive transistor (120) is provided which is connected to one of the storage nodes (106) to provide a low source impedance for output from the memory cell. A work line (44) is connected to the high voltage node (110) for selection thereof by varying between two predetermined voltages. The cell is written to be selectively discharging either node (104) or (106) to a low voltage node (114) through bipolar transistors (122) and (124). The bipolar transistor (122) and (124) provide high transconductance switches for selectively discharging the storage nodes (104) and (106).

Abstract: A CCD imager cell (36, 38) is formed at a face of a semiconductor substrate (10) and has first (36) and second (38) phase regions. A first clocked well (14) is provided for receiving charge integrated in the first phase region (36). A second clocked well (16) is provided for receiving charge integrated in a second phase region (38) adjacent the first phase region (36). A first gate (20) is insulatively disposed over the first clocked well (14), and a second gate (22) is insulatively disposed over the second clocked well (16). A controller controls .phi..sub.1 and .phi..sub.2 pulses such that the charge is transferred from a selected one of the first and second clocked wells (14, 16) to the other, thus integrating all of the charge in the cell into one clocked well thereof. This unified charge is then transferred out from clocked well to clocked well.

Abstract: A circuit capable of driving inductive loads below a chip substrate voltage level while minimizing on-chip power dissipation and eliminating parasitic effects. Two negative voltage drive modes are included in the circuit design. The first drive circuit forces a low negative voltage referenced to the circuit output voltage across an inductive load referenced to ground to provide a slow recirculation of the current in the inductive load. The second drive circuit forces a large negative voltage referenced to the circuit output voltage across the inductive load to provide a fast collapse of the inductive load. The switching regulator switches off when the current to the inductive load reaches a first value and switches on when the recirculating current from back e.m.f. reaches a second value. The switching regulator initially provides a higher level of power when first tuned on.

Abstract: A technique is described for improving the sampled current accuracy in current mirror circuits such as are often used to monitor the current output to a load. A reference voltage is established to feedback the load voltage conditions at the output to the current reference circuitry, thereby greatly reducing the error in the reference current over that which is produced by prior art circuits. The technique is shown aas applied to a current limiting circuit for driving an output load. An alternative embodiment is also disclosed.

Abstract: A PFC controller (FIG. 5) provides power factor correction and peak current limiting for a switch-mode power converter of any topology (buck, boost or buck-boost), without having to directly sense inductor current. The PFC control technique involves using a piecewise-polynomial analog computer (AC) to compute power transistor on-times in accordance with separate polynomial transfer functions for power-factor control and peak-current-linking using as inputs current representations of line input voltage (VLN), load output voltage (VLD), and long-term current demand (VCD). A conduction cycle is initiated by sensing when the rate of change in the inductor current reaches zero using an auxiliary winding on the current storage inductor (Wzd), and terminated after the computed on-time to implement either power-factor control or peak-current-limiting.

Abstract: A thin film package is formed using a lost cost TAB interconnection on a semiconductor device and sandwiching the device between thin films of plastic to form a sealed, thin, light weight package for the semiconductor device.