Abstract: A field programmable gate array having anti-fuse crosspoints. The input and output circuits of the gate array are especially designed so that the low voltage logic modules are not affected by high programming voltages. Each logic module is designed to be part of the programming circuit, rather than being isolated from it.

Abstract: A method and structure for protecting an integrated circuit from electrostatic discharges are disclosed. A Schottky diode (22) is connected to an input bond pad (12) and to a MOSFET transistor (17) which is desired to be protected. The normally high breakdown voltage required to drive the Schottky diode (22) into conduction is reduced by providing a trigger transistor (24) for prematurely triggering the diode (22). When the base-collector junction of the common emitter configured trigger transistor (24) is driven into avalanche breakdown by the electrostatic discharge, charged carriers (60) are generated, and attracted by the Schottky diode (22). The base (54) of the trigger transistor (24) is biased during normal operations with a supply voltage, and during electrostatic discharges to a higher voltage by an inherent Zener diode (64).

Abstract: The distance between a semiconductor wafer and a bake/chill plate is determined by a feed back system using a flow meter. The wafer forms part of the feed back system by limiting the flow of air or gas between the wafer and bake/chill plate, the distance between the wafer and bake/chill plate determining the amount of flow of air or gas through the flow meter.

Abstract: A register file for a bit slice ALU includes a static RAM array (86) which is addressable by two input read addresses. The addresses decoded by decoders (104) and (106) for input to the array (86). The array (86) simultaneously outputs two data words in response to two read addresses to sense amps (94) and (98). Data can be written into the memory by storing it in a data latch (100) and addressing it with a separate write address. The separate write address is latched in a write address (108) which is enabled on the rising clock edge by control circuit (114).

Abstract: The planarity of semiconductor device pins is measured simultaneously by multiple pneumatic comparator circuits by detecting pressure changes proportional to pin position.

Abstract: One embodiment of the present invention is a one transistor DRAM cell having enhanced capacitance and minimized soft error rate by providing an ungrounded cell capacitor plate which is insulated from the substrate. The structure includes a vertical transistor on the sides of a vertical depression or trench in a substrate. In the bottom of the trench, a memory cell capacitor is fabricated. This capacitor includes a conductive polycrystalline silicon post through the middle of the capacitor, thereby increasing the surface area of the capacitor plates. This increases the capacitance of the memory cell capacitor.The ungrounded plate of the memory cell capacitor is fabricated in the trench and is insulated from the substrate. This ungrounded plate is connected to the vertical transistor via a polycrystalline silicone plug. Thus this embodiment of the present invention reduces soft error rate by providing a fully insulated ungrounded memory cell capacitor plate.

Abstract: A sputter-etch process is used to etch vias having substantially vertical sidewalls, such that a sloped sidewall is formed. Using a silicon dioxide layer in which to form the vias, slopes of approximately 45.degree. may be obtained. A second insulator layer may be provided to protect the leads and other portions of the device during the sputter-etch to prevent damage.

Abstract: An improved SOI structure 40 is provided. SOI structure 40 includes a semiconductor mesa 42 formed over a buried insulating layer 46 which overlies a substrate 48. Sidewall insulator regions 50 and 52 are formed along sidewalls 54 and 56, respectively, of semiconductor mesa 42. Sidewall spacers 62 and 64 are formed along sidewall insulator regions 50 and 52, respectively. Sidewall spacers 62 and 64 each include respective foot regions 66 and 68. Foot regions 66 and 68 effectively shift undercut areas 74 and 76 laterally away from semiconductor mesa 42.

Abstract: An N-bit conditional sum adder 8 includes first and second conditional sum adders 10a and 10b. Each of the adders may be built from a plurality of one-bit conditional sum adders 110. In one embodiment, each one-bit adder 110 comprises a XNOR gate 50, a XOR gate 52, a NAND gate 54 and a NOR gate 56. The carry outputs CO.sub.a and CO.sub.b of the first conditional sum adder 10.sub.a are coupled to BiCMOS drivers 12 and 14 which in turn are coupled to the select inputs of a plurality of multiplexers 16 and 18. The multiplexers may be CMOS multiplexers built from transmission gates.

Abstract: A buried P-N junction photodiode is obtained in LinBiCMOS process with junctions formed between N+DUF diffused region and both first P-EPI layer and second P-EPI layer. Contact to N+DUF diffused region is made by a small area deep N+collector diffusion or N well diffusion. This novel buried-junction photodiode can be used for several types of unique photodetector structures including: single photodiode with low surface leakage current, multi-junction photodiodes for incident light spectral distribution information and higher efficiency visible response photodetectors. The disclosed structures are compatible with bipolar and CMOS processes for providing on-chip integration of optical photodetectors with Linear ASIC standard cells and other circuit functions.

Abstract: A scanning electron microscope (28) is connected to a test structure (48) formed on a semiconductor wafer. The test structure (48) comprises a plurality of first parallel structures (54) and a plurality of second parallel structure (56) transverse to and interlocking with the first structures (54). An island (60) is formed within a grid (58) formed by the structures (54-56) and is separated therefrom. An electron beam (38) from the scanning electron microscope (28) is aimed at the structure (48) and secondary electrons emitted therefrom are visually displayed on a monitor (44). The visual display (47) provides information on whether the island (60) is electrically separated from the mesh (58) or shorted thereto by comparing the intensity of the various islands (60).

Abstract: A semiconductor over insulator transistor is provided preferably of a lightly doped drain ("LDD") profile. LDD transistor (74) includes a semiconductor mesa (76) formed over an insulating layer (94) which overlies a semiconductor substrate (96). Semiconductor mesa (76) includes a source region (78) and a drain region (80) at opposite ends thereof. A body node (82) is disposed between source and drain regions (78,80). A low resistance contact region (98) lies along substantially the entire width of body region (82) and contacts a vertical contact which permits electrical contact from the top surface of semiconductor mesa (76) to low resistance contact region (98). Low resistance contact region (98) may be extended to fully underlie source region (78) such that the vertical contact may be moved away from body node (82).

Abstract: Measurements for inductance and capacitance at various frequencies have been made on semiconductor device to determine inductance of the leads of the device. The measurement methods involve a Time Domain Reflectometer in a unique application in which the leads of the device being measured are submerged in a liquid during measurements.

Abstract: One method of the present invention provides a method of connecting a flange to a cylinder. This method includes securing the cylinder in a first chuck of a lathe and securing the flange in a second chuck of the lathe. The method also includes rotating the first and second chuck such that the cylinder and flange are rotated while bringing an end of the cylinder and the flange in proximity of a heating element associated with the lathe contemporaneously with the rotating step. Finally, there is the step of bringing the end of the cylinder in contact with the flange. Novel apparatus consistent with the present invention are also disclosed.

Abstract: A floating-gate memory cell with an improved doping profile. After the substrate background doping has been set to a desired level (e.g. by a high dose implant and long drive in), two implant of opposite type are used to shape the doping profile of the floating-gate transistor. A boron implant is used to provide significantly increased p-type doping underneath the channel, at depths near the midpoint of the source/drain diffusions. A shallow arsenic implant partially compensates this boron implant at the surface, to set the threshold voltage as desired. The region of substantially increased p-type doping helps to suppress the lateral parasitic bipolar transistor which can otherwise suppress programmation, and also (by providing increased doping at the drain boundary) increases hot electron generation.

Abstract: A memory cell comprises a semiconductor pillar and an insulator on a sidewall of the pillar. A conductive capacitor of the memory cell comprises a first electrode adjacent the insulator. A transistor of the memory cell is formed in the pillar and comprises a first source/drain region, a gate, and a second source/drain region coupled to the first electrode.

Abstract: An improved local electrical interconnect device fabrication and method are provided. Reacted refractory metal contacts and local interconnect lines (54) and (56) are formed by reacting a deposited refractory metal layer (53) with selectively grown semiconductor regions (48) and (50). Regions (48) and (50) are formed after a masked ion implantation which forms loosely bonded surface regions (44) and (46) within field insulating regions (12). As a result of the ion implantation, semiconductor regions (48a) and (50a) are able to form over field insulating regions (12).

Abstract: A method for detecting defects in solder coatings on leads for electronic components maps the surface of the lead, detects light from the coated lead, and distinguishes defects in the coating based on the amount of reflected light.

Abstract: An electron beam imaging system (10) includes a photoemitter plate (12). An optical image beam (15) is directed through a pattern mask (18), which is imaged onto the photoemitter (12). The photoemitter (12) emits electrons from those unmasked regions illuminated by the optical image beam, emitting an extended-source electron beam that carries the mask image. The extended-source electron beam is focused (34) onto a device under fabrication (40), providing a single-stage electron lithographic patterning function. The optical source (16) is chosen so that the optical image beam energy is nearly identical to the work function for the photoemissive coating (14) of the photoemitter (12). As a result, the photoemitter (12) emits electrons with substantially zero kinetic energy, allowing the emitted electrons to be accelerated through the electron beam focusing elements (34) with very nearly identical electron velocities, thereby minimizing chromatic aberrations.

Abstract: A multi-point non-invasive, real-time pyrometry-based temperature sensor (200) for simultaneously sensing semiconductor wafer (22) temperature and compensating for wafer emissivity effects. The pyrometer (200) measures the radiant energy that a heated semiconductor wafer (22) emits and coherent beams of light (224) that the semiconductor wafer (22) reflects. As a result, the sensor (200) generates accurate, high-resolution multi-point measurements of semiconductor wafer (22) temperature during a device fabrication process. The pyrometer (200) includes an infrared laser source (202) that directs coherent light beam (203) into beam splitter (204). From the beam splitter (204), the coherent light beam (203) is split into numerous incident coherent beams (210). Beams (210) travel via optical fiber bundles (218) to the surface of semiconductor wafer (22) within the fabrication reactor (80). Each optical fiber bundle (218) collects reflected coherent light beam and radiant energy from wafer (22).