Abstract: A modem communication system with receiving and transmission paths includes a direct equalizer system having an adaptive filter (1532) in the transmission path to compensate for frequency distortion of the communication channel. The transmitter filter coefficients are adapted by a filter coefficient calculator (1528), under control of a data detector (1526) which detects incoming data in the receiving path. A switch (1534) is controlled by status of a transmit output data buffer to multiplex either the training sequence or output data into the transmission path. When the buffer is idle, the training sequence generator (1540) is linked to a digital-to-analog (D/A) converter (1536) and line driver (1538). The receiving path includes an isolation switch (1520), a receiver amplifier (1522) and a slicer (1524). The receiver correlates the received training sequence with a known training sequence and updates the equalizer filter coefficients using an adaptation algorithm, such as a least mean squared algorithm.

Abstract: An MDSL modem is provided that is inter-operable with an ADSL modem. The present invention provides a method for modem operation, by dividing available bandwidth for the modem into a plurality of subsets, selecting at least one of the plurality of subsets for use as a communication path, reducing the SNR value used for bit loading for the selected subsets by a predetermined amount, undersampling any received data, and fast fourier transforming the received data to recover the data transmitted. An MDSL modem is provided having circuitry for dividing available bandwidth for the modem into a plurality of subsets, circuitry for selecting at least one of the plurality of subsets for use as a communication path, circuitry for reducing the SNR value used for bit loading for the selected subsets by a predetermined amount, circuitry for undersampling any received data, and circuitry for fast fourier transforming the received data to recover the data transmitted.

Abstract: A modem communication system with receiving and transmission paths includes a direct equalizer system having an adaptive filter (1532) in the transmission path to compensate for frequency distortion of the communication channel. The transmitter filter coefficients are adapted by a filter coefficient calculator (1528), under control of a data detector (1526) which detects incoming data in the receiving path. A switch (1534) is controlled by status of a transmit output data buffer to multiplex either the training sequence or output data into the transmission path. When the buffer is idle, the training sequence generator (1540) is linked to a digital-to-analog (D/A) converter (1536) and line driver (1538). The receiving path includes an isolation switch (1520), a receiver amplifier (1522) and a slicer (1524). The receiver correlates the received training sequence with a known training sequence and updates the equalizer filter coefficients using an adaptation algorithm, such as a least mean squared algorithm.

Abstract: A modem selectively operated in the voice and higher frequency band which supports multiple line codes. The modem uses a digital signal processor so that different existing ADSL line codes can be implemented on the same hardware platform. The modem negotiates in real-time for a desired line transmission rate to accommodate line condition and service-cost requirement. The line code and rate negotiation process may be implemented at the beginning of each communication session through the exchange of tones between the modems. A four-step MDSL modem initialization process is provided for line code and rate compatibility. A synchronization startup procedure for DMT based MDSL modems is provided. The handshake protocol and receiver algorithm allow reliable standard telephone twisted-pair wire. The algorithm makes use of a short length sequence to train a synchronizing equalizer at the receiver. After training to this sequence, a matched filter or correlator is used to detect the inverted sync sequence.

Abstract: A modem operating selectively in the voice frequency and higher frequency bands which supports multiple line codes. A DSP is used to implement different existing ADSL line codes on the same hardware platform. The modem negotiates in real time for a desired line transmission rate to accommodate line condition and service cost requirements which may be implemented at the beginning of each communication session by exchange of tones between modems. A four step MDSL modem initialization process provides line code and rate compatibility. The handshake protocol and receiver algorithm for CAP based MDSL modems allows reliable modem synchronization over severely amplitude distorted channels and makes use of a short length sequence to train a synchronizing equalizer at the receiver. The algorithm and corresponding training sequence to train the transmitter filter are provided. After training to this sequence, a matched filter or correlator detects the inverted sync sequence.

Abstract: A modem that operates selectively in the voice-band frequency band and at higher frequency bands is provided. This modem supports multiple line codes, like DMT and CAP.The modem uses a Digital Signal Processor (DSP), so that different existing ADSL line codes, such as Discrete MultiTone (DMT) and Carrierless AM/PM (CAP), can be implemented on the same hardware platform. The modem negotiates in real-time, for a desired line transmission rate to accommodate line condition and service-cost requirement.The line code and rate negotiation process may be implemented at the beginning of each communication session through the exchange of tones between the modems. A four-step MDSL modem initialization process is provided for line code and rate compatibility.

Abstract: A modem that operates selectively in the voice-band frequency band and at higher frequency bands is provided. This modem supports multiple line codes, like DMT and CAP. The modem uses a Digital Signal Processor (DSP), so that different existing ADSL line codes, such as Discrete MultiTone (DMT) and Carrierless AM/PM (CAP), can be implemented on the same hardware platform. The modem negotiates in real-time, for a desired line transmission rate to accommodate line condition and service-cost requirement. The line code and rate negotiation process may be implemented at the beginning of each communication session through the exchange of tones between the modems. A four-step MDSL modem initialization process is provided for line code and rate compatibility.

Abstract: A central office xDSL modem pool has N logical xDSL modems. Each modem consists of a transmitter part and a receiver part and is connected to a twisted pair subscriber loop. A central office clock synchronizes the modem transmitters. A reverse channel near-end crosstalk (NEXT) canceller bank is implemented within the modem pool. The NEXT canceller bank has N NEXT cancellers corresponding to the N MDSL modems. Each canceller has N adaptive filters of size M. Outputs of all N adaptive filters are combined to form the NEXT cancellation signal for the corresponding modem. Each adaptive filter is adapted according to the error signal between the received signal and the NEXT cancellation signal and the corresponding transmit signal as the correlation vector.

Abstract: A modem that operates selectively in the voice-band frequency band and higher frequency bands is provided. This modem supports multiple line codes, like DMT and CAP. The modem uses a Digital Signal Processor (DSP), so that different existing ADSL line codes, such as Discrete MultiTone (DMT) and Carrierless AM/PM (CAP), can be implemented on the same hardware platform. The modem employs a method for interfacing the modem hardware with a host operating system. The method calls a defined set of host interface functions for command/control, calls a defined set of host interface functions for link correction management, calls a defined set of host interface functions for data sending/receiving, calls a defined set of host interface functions for synchronization between voice-band audio and above voice-band audio, and calls a defined set of host interface functions to use the voice-band as control channel and above voice-band as a data channel.

Abstract: A data processing device includes a circuit having status conditions wherein a particular set of the status conditions can occur in operation of the circuit. An instruction register operates to hold a branch instruction conditional on a particular set of the status conditions. A decoder is connected to the instruction register and the circuit. A program counter is coupled to the decoder wherein the decoder is operable to enter a branch address into the program counter in response to the branch instruction when the particular set of the status conditions of the circuit are present.

Abstract: A system for real-time digital signal processing employs a single-chip microcomputer device having separate on-chip program ROM and data RAM, with separate address and data paths for program and data. An external program address bus allows off-chip program fetch in an expansion mode, with the opcode returned by an external data bus. A bus interchange module allows transfer between the separate internal program and data busses in special circumstances. The internal busses are 16-bit, while the ALU and accumulator are 32-bit. A multiplier circuit produces a single state 16.times.16 multiply function separate from the ALU, with 32-bit output to the ALU. One input to the ALU passes through a 0-to-15 bit shifter with sign extension.

Abstract: A circuit for interfacing a processor with a host processor is provided that has a memory associated with the processor that is selectively accessible by either both the processors or by the host processor, a plurality of storage devices selectively interconnectable with the memory and host processor, and a logic circuit interconnected with the storage devices and processors for interconnecting at least a portion of the storage devices to the memory in response to signals from the processors. An integrated circuit is provided that has a microprocessor, a memory associated with said processor that is selectively accessible by said microprocessor or a host processor, a plurality of storage devices selectively interconnectable with said memory and said host processor, and a logic circuit interconnected with said storage devices and interconnectable with said processors for interconnecting at least a portion of said storage devices to said memory in response to signals from said processors.

Abstract: An electronic device includes an electronic circuit having points for introducing power supply voltage, ground return, and at least one output. A keyless device package holds the electronic circuit, and the keyless device package is subject to misorientation. Terminals, including terminals for power supply voltage, the ground return and the output, are connected to the electronic circuit and secured to the device package. The terminals are distributed on the device package so that a turning reorientation of the entire electronic device translates the terminals to each other only in a way which prevents electrical stress to the electronic circuit due to possible misorientation of the electronic device under test. Other devices, systems and methods are also disclosed.

Abstract: A system for real-time digital signal processing employs a single-chip microcomputer device (10) having separate on-chip program ROM (14) and data RAM (15), with separate address and data paths for program and data. An external program address bus (RA) allows off-chip program fetch in an expansion mode, with the opcode returned by an external data bus (D). A bus interchange module (BIM) allows transfer between the separate internal program and data busses (P-Bus and D-Bus) in special circumstances. The internal busses are 16-bit, while the ALU and accumulator (Acc) are 32-bit. A multiplier circuit (M) produces a single state 16.times.16 multiply function separate from the ALU, with 32-bit output to the ALU. One input to the ALU passes through a 0-to-15 bit shifter (S) with sign extension.

Abstract: A process for the fabrication of an improved LDMOS transistor, and such an improved LDMOS transistor are provided. The improved LDMOS transistor is in a semiconductor layer of a first conductivity type. The transistor has a source and drain of a second conductivity type (opposite the first conductivity type) and a channel of the first conductivity type with a conductive gate insulatively disposed over the channel. A low-voltage tank of the second conductivity type is used to contain the drain drift region and because of its lower sheet resistance provides a lower R.sub.DS (on). This tank of the second conductivity type extends from the field oxide at the exterior perimeter of the drain region, joins with the channel region and extends below the gate oxide and field oxide associated therewith.

Abstract: An electronic device includes an electronic circuit having points for introducing power supply voltage, ground return, and at least one output. A keyless device package holds the electronic circuit, and the keyless device package is subject to misorientation. Terminals, including terminals for power supply voltage, the ground return and the output, are connected to the electronic circuit and secured to the device package. The terminals are distributed on the device package so that a turning reorientation of the entire electronic device translates the terminals to each other only in a way which prevents electrical stress to the electronic circuit due to possible misorientation of the electronic device under test. Other devices, systems and methods are also disclosed.

Abstract: A logic module 400 for use in a field programmable gate array 100 can be selectively reconfigured to perform over 2,200 boolean combinational functions on output 431, to operate as a full adder with sum and carry outputs, or to perform the sequential function of a D latch or a D flipflop. Logic module 400 is comprised of 2-input multiplexers 500 and 600 which are used to form both the combinational and sequential circuits, thereby efficiently utilizing space on gate array 100.

Abstract: An integrated circuit containing high voltage PMOS an/or NMOS devices as well as low voltage PMOS and/or NMOS devices and a simple low cost method for making same that is adaptable to many types of semiconductor processes; furthermore, the breakdown voltage of the high voltage devices is easily adjusted so that the value of R.sub.on can be optimized. High voltage MOS devices 6 and 7 are formed on substrate 10 using essentially the same process steps as are used to form low voltage MOS devices 8 and 9. Low values of R.sub.on are obtained by selecting impurity concentration levels for HV drift region n-tank 21 and for HV drift region p-tank 41 so that the depletion region distance D1 bounded by equipotential lines 301a and 301j and the depletion region distance D1a bounded by equipotential lines 401a and 401h are smaller than the physical size D2 and D2a of drift regions 41 and 21, respectively.

Abstract: A technique for quantifying the effect of plasma etching during the formation of MOS transistors avoids the problems of prior techniques. A modified MOS capacitor 40 comprising a dielectric 12 separating a conductive plate 18 having a conductive sidewall 24 from a conductive substrate 10 is formed using the same or similar steps as a MOS transistor. Dielectric layer 12, such as oxide, is formed over a portion of conductive substrate 10. Conductive capacitor plate 18 is formed over a portion of the dielectric layer 12 using a plasma etch to remove unwanted material. After forming capacitor plate 18, the area of capacitor plate 18 is modified to encompass a peripheral oxide region 20. The modification consists of placing a conductive sidewall 24 of the same material as capacitor plate 18 or of other conductive materials around the periphery of capacitor plate 18.

Abstract: An electronic device for transferring data between a serial port and a memory of a CPU is provided having a plurality of data registers for transferring data between said serial port and said memory in response to a first set of control signals, a data bus connected to said registers and said memory for passing data to and from said memory in response to a portion of said first set of control signals, first control circuitry for generating said first set of control signals and for generating at least one interrupt to said CPU, at least one control register connected to said first control circuitry for providing mode control information to said first control circuitry, a plurality of address registers for storing data address, at least one address generator connected to said address registers for automatically generating addresses in response to a second set of control signals, an address bus connected to said address registers, and second control circuitry connected to said address generator, a portion of sai