Abstract: A data processing device includes a data bus and a program bus, a data memory connected to the data bus and having data memory locations, and an electronic computation unit connected to the data bus and an accumulator connected to the electronic computation unit and to the data bus. A logic circuit is connected to the program bus for receiving instructions and connected to the data bus for executing logic operations in accordance with at least some of the instructions. The logic operations affect bits in at least one of the data memory locations independently of the electronic computation unit without affecting the accumulator. A control circuit sends instructions to the logic circuit on the program bus and to the electronic computation unit. Other devices, systems and methods are also disclosed.

Abstract: An integrated circuit containing analogue operation circuitry having a plurality of nodes for input and output of signals during normal operation, a plurality of scan cells connected to at least said plurality of nodes for containing signals to be utilized in selected tests to be performed on said analogue operation circuitry and responsive to selected output signals is provided. A method for testing a module of analogue circuitry incorporated into an integrated circuit having other circuitry by decoupling a plurality of module signal terminals from respective normal operation connections to a plurality of scan cells, and inputting at least portions of test suites and sensing test result output signals through at least selected ones of said scan cells is provided.

Abstract: An audio data processing system (10) is described which comprises a control processor (12) coupled to an execution controller (22) through a bus (21). The control processor (12) serves as a master processor to control the operation of the execution controller (22) which in turn controls the operation of a multiplier accumulator (28). An ancillary data handler (20) is provided to retrieve ancillary data from an input FIFO buffer (18). Audio data is retrieved from the input FIFO buffer (18) by the control processor (12) and processed audio data is output through an output block (30).

Abstract: An integrated circuit containing analogue operation circuitry having a plurality of nodes for input and output of signals during normal operation, a plurality of scan cells connected to at least said plurality of nodes for containing signals to be utilized in selected tests to be performed on said analogue operation circuitry and responsive to selected output signals is provided. A method for testing a module of analogue circuitry incorporated into an integrated circuit having other circuitry by decoupling a plurality of module signal terminals from respective normal operation connections to a plurality of scan cells, and inputting at least portions of test suites and sensing test result output signals through at least selected ones of said scan cells is provided.

Abstract: A method for determining the energy consumption of a processor when executing a program is provided. The method initially selects the processor which will execute the program and then creates a model of energy used by said processor as a function of a plurality of instructions operable by said processor. The program whose energy consumption is to be determined is then executed using the energy model to determine the energy consumption of the program on the processor.

Abstract: A data processing device includes an electronic processor responsive to a context signal and operable in alternative processing contexts identified by the context signal. First and second registers are connected to the electronic processor to participate in one processing context while retaining information from another processing context until a return thereto. A context switching circuit is connected to the first and second registers and operates to selectively control input and output operations of the registers to and from the electronic processor depending on the processing context. Other devices, systems and methods are also disclosed.

Abstract: A high voltage PMOS or NMOS transistor 7 has improved on-resistance by truncating gate field oxide 43 so that drain region 42 may be implanted closer to channel region 49 than possible otherwise. By shortening the physical distance d2 between drain 42 and channel region 49, the drain to source on-resistance of the high voltage device is reduced and the performance of high voltage device 7 is thereby improved.

Abstract: In accordance with the present invention, an output current limit circuit for protecting a power MOS output device of an integrated circuit from an excessive drain current comprises a power MOS device 110, a means 30 to sense a predetermined trigger current, and a means 20 to reduce a gate-source voltage on MOS output device 110 to a predetermined approximately fixed value. A drain current I.sub.D flows through power MOS device 110 from output terminal 102 in response to the gate-source voltage. A short circuit condition may allow an excessive amount of drain current I.sub.D to flow through output terminal 102. The gate-source voltage is reduced in response to sensing the trigger current. Reducing the gate-source voltage raises a drain-source resistance of MOS device 110 and reduces drain current I.sub.D so that MOS device 110 is not damaged by the short circuit condition.

Abstract: A multifunction data storage register is provided having at least one first register cell having a first input multiplexer for selecting between two input signals responsive to one or more control signals and having a first output signal, a first input exclusive not OR circuit having a first input connected to said first output signal of said first input multiplexer and a second input connected to a cell output signal and having a third output signal, a first shift register latch having an input connected to said third output signal of said first input exclusive not OR circuit and having a fourth output signal, a first output exclusive not OR circuit having a first input connected to said fourth output signal of said first shift register latch and a second input connected to a feedback signal and having a fifth output signal, and a first output multiplexer for selecting between said fifth output signal and said fourth output signal responsive to said one or more control signals and having a first cell output

Abstract: A method of using a computer to assemble source code having a number of sub-instructions on each source code line, such that a processor may execute more than one sub-instruction during a single clock cycle. The computer is used to assign a binary conflict mask to each sub-instruction and to compare these conflict masks to determine whether a conflict exists among the sub-instructions. Additional features of the invention are determining the nature of the conflict and generating an appropriate indication signal to the user.

Abstract: An automatic color control and chroma killer circuit 3 and video processing system is provided that is capable of controlling an amplitude of a color signal and of performing a killer function with a simple construction without using a divider and/or vertical filter. The ACC/ACK device includes ACC and ACK circuitry which may be selectively enabled with operating signals to a selector 27. When the selector 27 enables amplitude detector 25, the amplitude detector 25 detects amplitude of the input color signal and a coefficient controller 26 compares it with a killer level. If the input color signal fails to meet the killer level then the coefficient controller 26 controls a coefficient generated by the coefficient generator 22 to perform a killer operation. The ACC operation and circuitry is thereby ACK controlled until an input color signal meets or exceeds the killer level.

Abstract: A processor (10) comprises a plurality of processing elements each having an input register (11), first memory bank (12), first sense amplifier (40), ALU (13), output register (16), second memory bank (15) and second sense amplifier (42). The first sense amplifier (40) is shared between the input register (11) and first memory bank (12). The second sense amplifier (42) is shared between the output register (16) and second memory bank (15). The sense amplifier (40,42) may be paused to prevent voltage spikes during a read/write operation, or to wait until a calculation is completed.

Abstract: A device and method for composite signal decoding is provided in which an analog to digital converter (18) digitizes an incoming composite signal. The digitized signal is transmitted to a least mean squares estimator (24). Least mean squares estimator (24) generates composite estimates which are filtered in filter (26). A phase extractor (28) extracts information on the phase between the sampling frequency and the incoming composite signal. Any phase shift existing between a left channel and right channel of the incoming composite signal are compensated in phase compensator (30). A channel extractor (34) extracts a sum and a difference of the left and right channels based on the phase information generated by phase extractor (28). An interpolator (36) adds and subtracts the information generated by channel extractor (34) to isolate the left and right channel signals.

Abstract: A method for controlling the firing times of a plurality of marine seismic sources which are towed as a seismic array behind a towing vessel is provided. The marine seismic sources are adapted to create seismic pulses after having been fired. The method measures and determines physical quantities representing the instantaneous operating depths of the individual seismic sources of the array and transmits the values of said quantities to a controling means for the seismic sources which compares the depth values thus obtained with predetermined depth values, and, if the measured depths are different from a preset depth, adjusts the firing times of the seismic sources of the seismic array in relation to the measured instantaneous depth values.Apparatus for carrying out the method is also provided.