Abstract: A system for clipping polygons representing three-dimensional objects to produce a representation of the portion of the objects in a desired viewing space is disclosed. A guardband space at least partially enclosing the viewing space is defined. The polygons are compared to the guardband space to determine which polygons intersect at least one of the guardband planes defining the guardband space. The intersecting polygons are also compared to the viewing space to determine if they intersect at least one of the viewing planes defining the viewing space. Only polygons intersecting both a viewing plane and a guardband plane are clipped.

Abstract: A graphic processing system for representing three-dimensional objects on a monitor which uses a pipeline of polygon processors coupled in series. The three-dimensional objects are converted into a group of two-dimensional polygons. These polygons are then sorted to put them in scan line order, with each polygon having its position determined by the first scan line on which it appears. Before each scan line is processed, the descriptions of the polygons beginning on that scan line are sent into a pipeline of polygon processors. Each polygon processor accepts one of the polygon descriptions and stores it for comparison to the pixels of that scan line which are subsequently sent along the polygon processor pipeline. For each new scan line, polygons which are no longer covered are eliminated and new polygons are entered into the pipe. After each scan line is processed, the pixels can be sent directly to the CRT or can be stored in a frame buffer for later accessing.

Abstract: A method and apparatus for controlling a parallel combination of correlation circuits which compare image pixels. A number of correlation circuits are provided, each having its own memory. The memories are loaded with image data with each memory being assigned a different block (region) of the image. Each memory is also loaded with an overlapping portion of an adjacent block so that a pattern can be stepped across the entire block, including a match of the first column of the pattern with the last column of the block. The loading is done by generating addresses corresponding to addresses for the source image with one or more of the most significant bits modified so that the address sequence received by the second and subsequent memories are identical to the address sequence received by the first memory. This allows the various blocks of the image in the different memories to be later simulataneously accessed in parallel using a single address sequence.

Abstract: Two pressure wheels are mounted on respective support parts and are pressed against respective edges of print medium by a common force-applying device such as a cable acting substantially equally on two mechanical devices on which the pressure wheels are mounted in order to transmit substantially identical forces thereto; each wheel may be mounted at one end of a lever which is hinged to the corresponding support part and which supports a pulley over which the cable passes.

Abstract: A timing subsystem 10 including several test period generators for supplying a variety of timing signals to a device under test. Major, minor, and free-run period generators each supply various timing signals to a multiplexer 18, which selectively connects the timing signals to timing generators 20. A central processing unit 28 supplies data to the period generators and timing generators to define their respective timing signals. Timing signals generated by the major period generator 12 define the overall testing rate. The minor period generator 14 generates multiple timing signals within the periods of the major clock signals to permit higher clock rates. Timing signals that are independent of the major clock periods are generated by the free-run period generator 16. An external synchronizer circuit 26 provides a feedback loop from the device under test 22 to the major period generator. A reference driver trigger delay circuit 27 provides means for calibrating the timing generators.

Abstract: A wall-engaging apparatus for microinductively investigating a characteristic of earth formations traversed by a borehole includes an antenna set mounted in a longitudinally elongated body adapted for a sliding engagement with the wall of the borehole. The antenna set includes a conductive backplane member mounted in the body parallel to the wall-engaging face of the body and first, second, and third half-loop antenna elements. The half-loop antenna elements are coaxial located symmetrically about the half-loop of the first antenna element, with their respective ends located at the backplane member to couple image currents in the backplane. The locations of the second and third antenna elements are further selected to place the second and third antenna elements in electromagnetic symmetry relative to the first antenna element. A differential coupler is included for coupling the second and third antenna elements.

Abstract: A system is disclosed which enables signals to be supplied at precisely desired times in an automatic test system. The apparatus includes a base delay memory which stores information representing the higher order bits of a time delay, while vernier memories store information relating to the lower order bits of the time delay. Offset memories enable storing calibration data. The base delay memory controls at least two counters in independent signal paths, while the vernier and offset memories control appropriate deskew units for further delaying the counter output signal as desired. The system enables sharing of resources, yet eliminates the need for repetitively loading correction data for deskew operations.

Abstract: A programmable logic array having a number of inputs for receiving operand data and a number of outputs for furnishing the results of Boolean operations upon the operand data is provided with a precharge signal generator responsive to a state transition in the operand data for generating a precharge signal. The buffered operand data is furnished to an AND plane, and pullup circuits associated therewith are responsive to the precharge signal for charging the AND plane and sustaining the charge on all AND plane array lines in the logical ONE state. An OR plane is connected to the outputs of the AND plane, and pullup transistors associated with the OR plane and responsive to the precharge signal for charging the OR plane and sustaining the charge on all OR plane array lines in the logical ONE state. The PLA outputs are taken from the buffered outputs of the OR plane.

Abstract: Apparatus for delaying an electrical signal includes a sequence of stages, each for delaying the signal. A coarser stage delays the signal by multiples of a predetermined fundamental delay interval and a finer stage provides for fine adjustment of the delay. The fine stage includes an integral number N of delay elements, the total providing a delay interval greater than the fundamental delay interval, whereby the fine delay intervals compensate for fabrication tolerances to enable accurate calibration of the combined system by post-fabrication measurement. In one implementation each delay stage includes a tapped transmission line to provide delay intervals, in another a ramp generator is used.

Abstract: In a collapsable elongated article such as a sailboard, the several sections are joined together at respective double chevron surfaces and maintained together by a suitable clamping device. The double chevron surface is used to prevent relative movement in two axes, and the clamping device is used to retain the sections together and thereby prevent relative movement in the third axis.

Abstract: A multi-marker, multi-destination timing signal generator including a count-setting memory for storing a plurality of pulse-count values in a numerical order and a pulse counter for counting the number of pulses from a master clock. An output selection memory stores, for each pulse count value, enabling signals for a plurality of output elements so that a marker signal generated when the pulse counter equals a pulse-counter value in memory may be selectively routed to one or more output elements. The addresses of the count-setting memory and the output selection memory are maintained by an address counter. When the value of the pulse counter equals a pulse-count value stored in the count-setting memory, the address counter counts to the next address value for locating successive values in the count-settiong memory and the output selection memory.

Abstract: A system which enables signals to be supplied at precisely desired times in an automatic test system. The apparatus includes a base delay memory which stores information related to a base time delay, while a vernier memory stores information relating to timing corrections to be made to the base time delay. The base delay memory controls a counter while the correction memory controls a vernier deskew apparatus for further delaying the output signal from the counter. To prevent carries from the vernier memory from influencing the base delay memory, the most significant bit of the vernier memory is of the same significance as the least significant bit of the base delay memory. The most significant bit of the vernier memory is also connected to drive the counter, in effect providing the counter with two least significant bits, and enabling a single base delay memory to control more than one signal timing paths.

Abstract: A wall-engaging apparatus for microinductively investigating a characteristic of an earth formation traversed by a borehole includes an antenna set mounted in a sensing body adapted for sliding engagement with the wall of the borehole. The antenna set includes first, second and third antenna elements. The second and third elements, being structurally identical but differentially coupled, are positioned in electromagnetic symmetry about the first antenna element. Either the first antenna element or the differentially coupled second and third antenna elements may be energized by suitable circuits, while the other is coupled to circuits for receiving signals indicative of a set characteristic.

Abstract: A high precision analog to digital converter comprises the combination of an imperfect or low resolution digital to analog converter having an error function known in terms of orthonormal components and an error compensating device capable of generating correction terms which do not interact with one another. The correction terms are based on orthonormal components namely, the Walsh function components, of each signal level to be compensated. At most only one weighting value per bit is required, the combination of which will compensate for errors of any bit combination. In a specific embodiment employing feedback compensation, the output of the low resolution converter and of the compensating device may be summed to produce a high performance, high precision converter with increased accuracy and resolution.

Abstract: A high precision digital to analog converter comprises the combination of an imperfect or low resolution digital to analog converter having an error function known in terms of orthonormal components and an error compensating device capable of generating correction terms which do not interact with one another. The correction terms are based on orthonormal components namely, the Walsh function components, of each signal level to be compensated. At most only one weighting value per bit is required, the combination of which will compenate for errors of any bit combination. In a specific embodiment employing feedforward compensation, the output of the low resolution converter and of the compensating device may be summed to produce a high performance, high precision converter with increased accuracy and resolution.

Abstract: A multilayer photoresist system for defining very small features on a semiconductor substrate relies on forming a planarization layer directly over the substrate. An image transfer layer is formed over the planarization layer, and a photoresist imaging layer formed over the image transfer layer. The image transfer layer comprises an organic or inorganic resin which has been cured in a non-oxidated plasma. It has been found that such a curing technique provides a particularly smooth and defect-free image transfer layer. Very thin photoresist imaging layers may thus be formed over the image transfer layer, allowing very high lithographic resolution in the imaging layer. The resulting high resolution openings may then be transferred downward to the image transfer layer and planarization layer by etching, allowing the formation of very small geometries on the substrate surface.

Abstract: The tendency of a CMOS circuit to latch up is reduced by implanting ions of germanium or tin into the source and drain regions of the circuit. The low energy gap of these ions lowers the band gap of the source and drain regions, which in turn inhibits their ability to inject carriers into the substrate and well.

Abstract: A process is disclosed for simultaneously fabricating bipolar and complementary field effect transistors. The process enables distinguishing the bipolar devices from the CMOS devices with a single base mask 108, while requiring only a single additional mask 114 to define the bipolar emitter and MOS gates. The process forms the gate oxide 100 for the MOS devices at an early stage, then protects that oxide with polysilicon 103 during subsequent fabrication steps. Self-aligned metal silicide contacts 137 are separated from undesired regions using sidewall oxidation techniques.

Abstract: In the fabrication of bipolar transistors by the single poly process, polysilicon sidewalls are formed along portions of a polysilicon layer that functions as a device contact. The sidewalls serve both as dopant sources which determine the width of underlying base and emitter regions, and as contacts to those devices. Since the thickness of the polysilicon sidewalls, and hence the width of the underlying device regions, are precisely controllable through conventional polysilicon deposition techniques, relatively relaxed design rules can be employed while making possible the formation of emitters having widths less than one-half of a micron.

Abstract: A new method for solder finishing the leads of an integrated circuit package such as a DIP having two parallel rows of leads along the sides of the package. The method contemplates establishing two vertical columns of falling molten solder and spacing the columns apart a distance substantially the width of the package. The package is passed between the vertical columns of falling molten solder immersing the two parallel rows of leads along the sides of the package in the respective columns of molten solder, washing the leads and depositing a finishing layer of solder over the surfaces of the leads. The method further contemplates directing hot nonreacting gas over the leads of the package as the package passes from the columns thereby eliminating excess solder and bridging of solder between the leads. A monorail track system and a new solder bridge for implementing the method are described. The invention may be applied for column fluxing as well as for other column liquid treatments.