Abstract: There is disclosed herein an ECL gate using switchable load impedance means to allow the gate to be placed in a low power-consumption mode while preserving the logic state existing at the outputs of the gate at the time it is switched into the low-power mode. N-channel or P-channel MOS transistors are used as the switchable load impedances. The gates of these transistors are coupled to a MODE control signal which causes the MOS transistors to switch between high-impedance and low-impedance states. Another MOS transistor having its gate coupled to the same MODE control signal is used as the current source for the bias current to the conventional ECL current mirror. When low-power mode operation is desired, all the MOS transistors are switched to their high-impedance states. This reduces the bias current flowing through the ECL gate, thereby reducing its power consumption.

Abstract: A wall-engaging apparatus for microinductively investigating a characteristic of earth formation traversed by a borehole includes an antenna set mounted in a longitudinally elongated body adapted for a sliding engagement with the wall of the borehole. The antenna set includes a first antenna element, a second antenna element, and a third antenna element, the respective locations and orientations of the second and third antenna elements being selected to place the second and third antenna elements in electromagnetic symmetry relative to the first antenna element. Differentially coupling the second and third antenna elements. Either the first antenna element or the differentially-coupled second and third antenna elements may be energized by suitable means, while the other is coupled for receiving signals indicative of the characteristic.

Abstract: A photomask for use in manufacturing integrated circuits is fabricated by coating a thin film of organic material, generally a solution of a thermally decomposable hydrocarbon, onto a glass plate and heating it in a reducing atmosphere to convert it into carbon. The carbon layer is masked and etched; for example, in an oxygen plasma, to produce the mask.

Abstract: The shear velocity of a formation traversed by a fluid-filled open or cased borehole is obtained directly. Waveforms are obtained from a dipole acoustic investigation of the formation relative to a common location in the borehole. In this investigation, the bandwidth of the waveforms is substantially bounded by an upper frequency f.sub.u at and below which energy traveling at the shear velocity is dominant. Moreover, the bandwidth of the waveforms is concentrated near the frequency f.sub.u. The shear velocity of said earth formation is determined from these waveforms. In one embodiment, the waveforms are obtained from a broadband dipole acoustic investigation. The waveforms are low-pass filtered, and an interim shear velocity v.sub.s is determined from the filtered waveforms. The filtering and determining of v.sub.s are done first for an initial f.sub.cut, and subsequently for additional decreasing values of f.sub.cut, until a preselected relationship between f.sub.cut and v.sub.s is satisfied.

Abstract: The shear velocity of a formation traversed by a fluid-filled borehole is determined in the presence of a significant flexural mode arrival. A plurality of waveforms are obtained from a dipole acoustic investigation of the formation relative to a common location in the borehole. The flexural mode phase velocity as a function of frequency is determined. If a low frequency asymptote is identifiable, it is reported as the shear velocity. If a low frequency asymptote is not identifiable, however, a plurality of additional curves of the flexural mode phase velocity as a function of frequency are theoretically determined, based on respective estimated shear velocities. These theoretically determined curves are respectively fitted to the curve determined from the waveforms, until a satisfactory least error fit is achieved. The last-estimated shear velocity is reported as the shear velocity of the formation.

Abstract: A wall engaging pad for well logging comprises a face portion of electrically conductive material within which are disposed three or more current electrodes. The survey current emitted from the current electrodes is differently focussed. A suitable current return is furnished. A plurality of individual measurements having respective graduated depths of investigation are obtained and suitably processed to yield resistivity measurements. The body of the sonde carrying the pad may be used to enhance the focussing of the survey current.

Abstract: A semiconductor wafer having a plurality of integrated circuits is provided. One surface of the wafer includes a plurality of electrical contacts on the circuits which are subsequently attached to leads. The other surface of the wafer is provided with a conductive tape. The wafer is cut, e.g., sawed, resulting in each individual circuit having a pre-attached conductive mounting media. The individual circuits can then be attached to a substrate through the conductive mounting media. Other embodiments are disclosed.

Abstract: An apparatus is described for maintaining and delivering a slack reserve length of lead wire between a spool or other source and the wire bonding tool of a lead wire bonding machine. A slack chamber or wind chamber comprised of a housing enclosure, an inlet guide on one side for guiding lead wire into the slack chamber from a spool, an outlet guide on the other side for guiding lead wire out of the slack chamber towards the wire bonding tool maintains the reserve length of lead wire in untangled condition. A source of pressurized dry air or other gas directs a gaseous flow into the slack chamber so that the lead wire is maintained suspended in the gaseous flow in an offset configuration. Wire sensors are operatively positioned in the slack chamber for sensing the offset of lead wire in the wind stream. The wire sensors are coupled to sensor and control logic for controlling the delivery and feeding of lead wire from a spool into the slack chamber.

Abstract: A deposition reactor system is described for producing a coating containing a predetermined component on a substrate from a plasma containing such component in an ionized state. The substrate is supported on a susceptor within a reactor chamber to which is introduced a gas containing the predetermined component. A radio frequency field is inductively coupled to the gas, forming a plasma in the reactor chamber in the region of the susceptor. The susceptor is maintained at ground potential in the radio frequency field.

Abstract: A low inductive impedance dual in-line package for an integrated circuit die incorporates a lead frame formed with a central opening without a die attach paddle. A ground plate forms the die attach plane spaced from and parallel with the lead frame. A dielectric layer is formed between the lead frame and ground plate. The lead frame is formed with a ground lead finger electrically coupled in parallel with the ground plate thereby providing a ground path through the ground plate with planar configuration to minimize inductive impedance to ground current and to minimize cross coupling between the electrically active lead fingers of the lead frame. In the preferred embodiment, the lead frame and ground plate are initially supported in a spaced parallel plane relationship by complementary spacing tab elements. During encapsulation, the encapsulation molding compound is introduced between the lead frame and ground plate to form the dielectric layer.

Abstract: An emitter coupled logic (ECL) to transistor-transistor logic (TTL) translator is provided with a transistor clamp operatively coupled in at least one of the alternate transistor collector paths of the ECL input gate for clamping the voltage applied through the transistor collector path by the ECL current source to a level below saturation of the ECL input gate. The source current generated by the ECL current source may therefore be increased for accelerate turn-off of the TTL output gate of the translator without saturation of the ECL input gate. The transistor clamps are also applied in an ECL to tristate TTL translator in which the TTL output gate is a TTL tristate output device or buffer with dual phase splitter transistors. A dual transistor clamp arrangement in at least one of the ECL input gate transistor collector paths also provides separate clamped base drives to the dual phase splitter transistors for eliminating "current hogging" or base drive preemption.

Abstract: A multiple layer tape bonding technique interconnects an integrated circuit chip having signal and ground bonding pads located thereon to other electrical devices. The tape bonding structure is comprised of a first layer having electrically isolated individual signal conductors coupled to respective ones of the signal bonding pads. The individual signal conductors extend away from the integrated circuit chip in an approximately parallel-spaced relationship to one another. An electrically insulating layer having a predefined thickness is deposited atop and adjacent the first layer. A ground plane layer overlies the insulating layer. The ground plane layer is comprised of a plurality of individual ground conductors coupled to respective individual ones of the ground bonding pads of the integrated circuit chip. The individual ground conductors overlie the insulating layer in a precisely spaced parallel relationship to the corresponding individual signal conductors.

Abstract: In a process of forming vias for multilevel interconnects used in integrated circuits, a layer of a first metal is formed on a semiconductor substrate. A layer of a second metal is formed on the first metal layer. The second metal layer is etched in a predetermined via pattern with a second etchant which reacts with the second metal and which is substantially unreactive with the first metal. The first metal layer is then etched with a first etchant which reacts with the first metal and which is substantialy unreactive with the second metal or with the semiconductor substrate in order to form a predetermined contacting relationship with the predetermined via pattern. This process may be used to generate second and subsequent levels of vias and interconnects which can be used to contact metal layer at any level directly to the substrate by building via posts from the substrate to any desired metal layer.

Abstract: A multiple phase-splitter TTL tristate output circuit having a feedback diode coupled between the signal output and the collector of a first phase-splitter transistor to accelerate sinking of current from the output to low potential during transition of binary signals at the output from high to low potential. An independent base drive is coupled to the base of the first phase-splitter transistor independent from any base drive coupled to the other phase-splitter transistor or transistors. Current hogging of the base drive current to the first phase-splitter transistor by the other phase-splitter transistors is thereby prevented. The first phase-splitter transistor which is coupled in the feedback circuit with the accelerating feedback diode to the base of the pulldown transistor element can therefore maintain the high current sinking mode through the pulldown transistor element with gain step-up proportional to .beta..sup.2 when the output is at the high voltage level.

Abstract: A transistor-transistor logic (TTL) to emitter coupled logic (ECL) translator includes a TTL input gate for receiving TTL voltage level logic input signals in the positive voltage range compatible with TTL circuits and an ECL output gate for delivering corresponding ECL voltage level logic output signals in the negative voltage range compatible with ECL circuits. A translating current source operatively coupled between the TTL input gate and ECL output gate translates signals down to the negative ECL voltage range for application to the input transistor of the ECL output gate. A bidirectional bridge clamp also operatively coupled between the TTL input gate and ECL output gate limits the swing of the translated signals in the negative voltage range applied at the input of the ECL output gate thereby reducing propagation delay across the translator and reducing power dissipation.

Abstract: An applique of a prepatterned film of alpha particle resistant material, such as polyimide, is applied to a semiconductor wafer. The prepatterned film covers only the critical areas e.g. those affected by alpha particle impingement. Bond pads and scribe streets are not covered by the applique.

Abstract: TTL circuits are described for generating from an input signal complementary output signals useful in integrated circuit applications. For an enable gate, an alternate enable transistor element is coupled in emitter follower configuration in the enable gate with the base of the alternate enable transistor coupled to follow the enable gate input signal E and provide through the emitter circuit an alternate enable signal A complementary to the enable signal E. The complementary enable signals are applied in an improved TTL tristate output device with reduced output capacitance. The alternate enable signal A is coupled to the base of an active discharge transistor element at the base of the pull-down transistor of the tristate input device for actively discharging and diverting Miller feedback current caused by transitions on the common bus output when the enable signal E is at low potential and the device is in the high impedance third state.

Abstract: In the apparatus and method of the invention, acoustic energy is propagated in two slightly differing, or offset, circumferential paths in such a way as to interact with the formation under investigation. The propagating energy is detected and the resulting waveforms are compared using semblance. The waveforms corresponding to the respective paths will be quite similar provided that the length of the paths are equal and that there are no fractures or other similar anomalies between the source and receiver. The waveforms for the respective paths will be quite dissimilar, however, if a fracture or similar anomaly does lie between the source and receiver for the respective paths. The semblance may be displayed in log format.

Abstract: A method for inhibiting out-diffusion of dopants from polycrystalline or single crystal silicon substrates of high speed semiconductor devices into metal silicide conductive layers disposed on the substrate comprises interposing a refractory metal nitride layer between the doped silicon substrate and the refractory metal silicide conductive layer. Dopant out-diffusion is further retarded, and contact resistance lowered, by adding a thin layer of refractory metal between the refractory metal nitride layer and the silicon substrate.

Abstract: Apparatus for investigating subsurface earth formations traversed by a borehole comprising a system of electrodes consisting of a central electrode A.sub.0 and four pairs of electrodes M.sub.1 -M'.sub.1, M.sub.2 -M'.sub.2, A.sub.1 -A'.sub.1, A.sub.2 -A'.sub.2 respectively short-circuited and aligned symmetrically on both sides of the electrode A.sub.0.This apparatus comprises arrangements which, for a frequency .function..sub.2, establish a potential gradient between electrodes A.sub.1 -A'.sub.1 and A.sub.2 -A'.sub.2. A source of alternating current of frequency .function..sub.1 is connected between the electrodes A.sub.1 -A'.sub.1 and A.sub.2 -A'.sub.2 and a source of alternating current of frequency .function..sub.2 between a surface electrode B and electrodes A.sub.2 -A'.sub.2. The potential difference between electrodes M.sub.1 -M.sub.2 and M'.sub.1 -M'.sub.2 is maintained substantially at zero by circulating a current between electrodes A.sub.1 -A'.sub.1 and electrode A.sub.0.