Abstract: Electrophoretic deposition provides an efficient process for manufacturing a field emission cathode. Particles of an electron emitting material mixed with particles of an insulating material are deposited by electrophoretic deposition on a conducting layer overlying an insulating layer to produce the cathode. By controlling the composition of the deposition bath and by mixing insulating particles with emitting particles, an electrophoretic deposition process can be used to efficiently produce field emission cathodes that provide spatially and temporally stable field emission. The deposition bath for the field emission cathode includes an alcohol, a charging salt, water, and a dispersant. The field emission cathodes can be used as an electron source in a field emission display device.

Abstract: A trimming apparatus according to the present invention has a trim punch that provides a route for continuous air flow to prevent trimmed gate scraps from clogging the apparatus. The trim punch can have a groove or a through hole for providing the continuous air flow from outside into an outlet, through which trimmed gate scraps are discharged. This continuous air flow prevents the trimmed gate scraps from remaining inside the outlet and adhering to the trim punch. Therefore, clogging of the trimmed gate scraps in the apparatus is prevented.

Abstract: An apparatus for identifying a known good die according to an embodiment of the present invention includes a carrier for containing a bare semiconductor chip, a lid for covering the carrier, and a stopper for sealing the apparatus. The carrier includes: a body, in which a chip mount cavity and multiple vacuum suction holes are formed; inner connection terminals formed on a bottom surface of the chip mount cavity to communicate electrically with the bare chip; and outer connection terminals extending from the inner connection terminals to outside the body. The apparatus has an outer configuration of a conventional semiconductor package, so that the apparatus can fit into conventional test equipment. Therefore, the carrier can have a configuration of a plastic package, such as the SOP or SOJ, without a semiconductor chip.

Abstract: Die bonding equipment for fine pitch ball grid array package includes: a semiconductor chip pickup stage for inspecting a status of a loaded semiconductor chip and a corresponding position thereof; an alignment stage on which the semiconductor chip fixed on a mount head is aligned; a chip transfer unit for transferring the semiconductor chip from the semiconductor chip pickup stage to the alignment stage; a guide rail for guiding a mount tape frame; a status inspecting unit disposed at a selected position over the guide rail, for inspecting a status and a position of the land pattern on the mount tape frame; and a bonding unit for bonding the land pattern to the semiconductor chip which is mounted on the mount head. The equipment only bonds semiconductor chips (good or defective) to lands patterns having the same status (good or defective).

Abstract: A semiconductor memory device having a write masking function and a write masking method are provided. The semiconductor memory device includes a plurality of write bit lines, a plurality of write word lines, a plurality of write drivers, a plurality of MOS transistors, a plurality of latch circuits, and a plurality of precharge controllers. Each of the write drivers receives input data, a write enable signal and a write masking signal, outputs the input data when the write enable signal is activated and the write masking signal is deactivated, and does not output the input data when the write masking signal is activated. Each of the latch circuits includes an inverter having a large driving capacity and an inverter having a small driving capacity. When a precharge signal is activated, each of the precharge controllers precharges a corresponding write bit line to the logic threshold voltage of the inverter having the large driving capacity.

Abstract: A semiconductor device having data multiplexing and data masking functions is provided. The semiconductor device includes a dynamic random access memory (DRAM) cell array for inputting or outputting M×N data signals in parallel, a logic circuit having a control function, and a memory unit connected between the DRAM cell array and the logic circuit. The memory unit transmits or receives M×N data signals to or from the DRAM cell array and transmits or receives M data signals to or from the logic circuit, in response to an address signal input from the outside. The memory unit includes at least M memory blocks. Each memory block receives N data signals from the DRAM cell array and transmits at least one data signal to the logic circuit, and receives at least one data signal from the logic circuits and transmits N data signals to the DRAM cell array. A write/read word line driver connects to the at least M memory blocks.

Abstract: A dynamic random access memory device includes a circuit for generating sense amplification activation signals applied to sense amplifier circuits. The circuit changes the slopes of the activation signals according to variation of a power supply voltage. According to the present invention, the peak current the sense amplifier circuits use when the power supply voltage increases, is reduced, so that the sense amplifier circuits create less noise in the memory device.

Abstract: A semiconductor memory device which includes a plurality of memory cell array blocks, each block including 2n partial blocks selectable in response to n address bits among a plurality of bits address. A partial block select signal generator is used for selecting ½n partial blocks of the 2n partial blocks in each of the plurality of memory cell array blocks by selecting the state of corresponding address bits among the n address bits. A method for repairing a semiconductor memory device which includes a plurality of memory cell array blocks and 2n partial blocks selected by the plurality of memory cell array blocks each responding to n address bits among a plurality of address bits, the method includes selecting only the ½n functional partial blocks of the 2n partial blocks in each of the plurality of memory cell array blocks by selecting the state of corresponding address bits among the n bits of address information.

Abstract: A discharge ionization detector (DID) includes a sensor that uses an alternating current (AC) discharge through a working gas as an ionization source. The sensor includes a discharge chamber, into which the working gas is introduced, and an ionization chamber, into which a sample gas is introduced. UV photons from the discharge chamber and metastable particles that enter the ionization chamber from the discharge chamber ionize molecules in the sample gas. The ions generated from the ionized sample gas are measured as a current indicating the quantity of ionizable molecules in the sample gas. For selective identification of molecules in the sample gas, one or more chemical filters can filter the sample gas to separate target gases from gases that interfere with detection of the target gases. Additionally, a supply for the working gas can change the working gas to change the maximum energy available for ionization of the sample gas.

Abstract: A highly effective charge pump circuit includes a pulse generator for generating a pulse signal in response to a control signal, a first voltage pumping unit for generating a first high voltage in response to the control signal and the pulse signal, a second voltage pumping unit for generating a second high voltage of the same level as the first high voltage in response to the control signal and the pulse signal, and a voltage transmitting unit that receives and outputs first high voltage when the second high voltage is applied. The charge pump obtains a high voltage using NMOS transistors.

Abstract: The present invention provides a vertical semiconductor device package comprising a semiconductor chip, a heat spreader, a printed circuit board(PCB), a plurality of metal wires, and an encapsulating material. The semiconductor chip is directly attached to the heat spreader, and/or the heat spreader is directly attached to the metal layers in the PCB, which has multiple ground metal layers. A package module has a plurality of the vertical semiconductor device packages, which are vertically mounted on a second circuit board, and a heat sink, which is attached to each heat spreader. The present invention has advantages in that it enhances the heat dissipation properties and the electrical characteristics of the packages.

Abstract: A memory device having reduced power consumption by minimizing the operation of circuits utilized in reading and writing data, and a data reading and writing method of the memory device, are provided. In the memory device, upon data reading, an input and output sense amplifier amplifies data which is read from a memory cell and transferred to an input and output line, and transfers the resultant data to a data output line. Upon data writing, a writing driver receives write data via a data input line and transfers the received write data to the input and output line. Each of the input and output sense amplifier and the writing driver operates only when previously-read or -written data is different from current data to be read or written.

Abstract: A scalable method and system for generating a 3X long code sequence for use in a CDMA communication system uses Gold sequences. A preferred pair of 1X long code sequences both running at 1.2288 Mchips/s are used to generate the 3X sequence. The 3X sequence so generated is a pseudo-random sequence with well defined auto-correlation and cross-correlation properties. Because the method is scalable it is easily scaled to generate other long code e.g. 6X, 9X, and 12X sequences.

Abstract: A merged semiconductor device having a DRAM and an SRAM, and a data transmitting method using the same are provided. In this device, the DRAM acts as a main memory, and the SRAM acts as a cache memory. The reading operation of the DRAM, and the writing operation of the SRAM are simultaneously controlled by a DRAM read control signal. Also, the writing operation of the DRAM, and the reading operation of the SRAM are simultaneously controlled by a DRAM write control signal. In this device, DRAM write commands and DRAM read commands can be continuously given. Writing of the SRAM starts after reading of the DRAM is completed, and writing of the DRAM starts after reading of the SRAM is completed.

Abstract: An apparatus and a method for automatic testing and correction of the contact between an IC device and a socket are disclosed. The apparatus includes: a table; a burn-in board having a burn-in board connector; respective tools for loading the device from an IC tray to a positioning jig on the X-Y table, for inserting the device into a socket of the burn-in board, for removing the device from a socket of the burn-in board and for moving the device to a DC test position; a contact part for contacting the burn-in board connector; and a contact tester for testing the contact between device pins and socket terminals.

Abstract: A current sense amplifier circuit using a dummy bit line is provided. The current sense amplifier circuit includes a cell current generator, a reference current generator, and a sense amplifier. The cell current generator includes a memory cell connected to a word line and a bit line and generates memory cell current applied to the memory cell and bit line charge current for charging the bit line. The reference current generator includes a dummy bit line and a reference cell and generates reference cell current applied to the reference cell and dummy bit line charge current for charging the dummy bit line. The sense amplifier includes a first input terminal, connected to the cell current generator, for receiving the memory cell current and the bit line charge current and a second input terminal, connected to the reference current generator, for receiving the reference cell current and the dummy bit line charge current.

Abstract: A die collet for a semiconductor chip having an exposed electrical structure, the die collet including a body having a vacuum line connected thereto, the die collet including a plurality of parts each having a vacuum hole communicating with the vacuum line. Apparatus for bonding a semiconductor chip to a lead frame, the apparatus including a first die collet for picking up the semiconductor chip, on aligning stage for receiving the semiconductor chip from the first pickup tool and aligning the semiconductor chip. A second die collet picks up the semiconductor chip from the aligning stage and places the semiconductor chip on a lead frame. The first and second die collets are constructed as described above.

Abstract: A memory card includes a substrate and a resin-molded layer. The substrate includes contact pads that are on a second face thereof for communication with a card reader. Semiconductor chips are on a first face of the substrate and electrically connected to the contact pads through bonding wires and circuit wiring. The resin-molded layer is on the first face and covers the chips. The fabrication process for the memory cards begins with fabrication of a multi-substrate that includes several unit substrates. At least one semiconductor chip is provided on each unit substrate and electrically connected. A continuous resin-molded layer is then formed to extend over the unit substrates. Separating the unit substrates of the multi-substrate divides the continuous resin-molded layer into individual resin-molded units and provides the memory cards.

Abstract: A multiple-channel photo-ionization detector (PID) determines the concentrations of specific gases or classes of gases. The PID includes a UV lamp, an optical window which is divided into multiple zones with each zone producing a UV light beam having a distinctive maximum photon energy. The ionization chamber of the PID includes multiple ion detectors. The PID measures ionization currents and concentrations of gases ionizable by each UV light beam. A method of determining the concentrations and/or identifications of the individual component gases uses differences and/or ratios of measured concentrations or currents.

Abstract: A redundancy circuit of a semiconductor memory device includes a mode setting circuit that generates mode signal, an input selecting circuit that generates selecting signal in response to the mode signals, and a decoding circuit that, in response to the mode selecting signals, generates decoding signals. The redundancy mode signals include a bank redundancy mode signal, an array redundancy mode signal, and a column address group redundancy mode signal. The selecting signal identifies a bank in bank redundancy mode, an array in an array redundancy mode, and a column address group in column address group redundancy mode. The decoding signals initiate a replacement of a data I/O line pair associated to a defective memory cell in the semiconductor memory device. A redundancy method includes: generating the redundancy mode signals; generating the selecting signal in response to the redundancy mode signals; and generating the decoding signals.