Abstract: A method, system, and apparatus are disclosed. In one embodiment method includes causing a cooling medium to flow through a hollow cable. The cable couples an external cooling station to a heat exchanging unit. The heat exchanging unit is located within a mobile computing device. The method then transfers heat from within the mobile computing device to the cooling medium at the heat exchanging unit. Then the cooling medium contained the transferred heat is expelled out of the mobile computing device.

Abstract: A method for managing thermal condition of a thermal zone that includes multiple thermally controllable components include determining thermal relationship between the components and reducing temperature of a first component by reducing thermal dissipation of a second component.

Abstract: A processor, system, and method are disclosed. In an embodiment, the processor includes a first site and a second site. There is a link to transmit a voltage stabilization signal from the second site to the first site. In the first site voltage correction logic can dynamically modify a voltage supplied to the first site and second site. In the second site there is logic to assert the voltage stabilization signal. After asserting the voltage stabilization signal, the second site is granted at least a window of time in which the supplied voltage to the second site does not change.

Abstract: A method and apparatus for updating the system configuration settings of a computer system. Embodiments include a remote system configuration system that enables a user to update the system configuration of a target machine from a server machine over a network or similar communications system. Another embodiment includes a system configuration method using a bus master device to write system configuration data into a target computer system.

Abstract: A method, device, system, and computer readable medium are disclosed. In one embodiment the method includes managing one or more threads attempting to steal task work from one or more other threads. The method will block a thread from stealing a mailed task that is also residing in another thread's task pool. The blocking occurs when the mailed task was mailed to an idle third thread. Additionally, some tasks are deferred instead of immediately spawned.

Abstract: A device, method, and system are disclosed. In one embodiment a computing device resides in a mesh network. The device includes a first storage device that operates when the computing device is awake. The first storage device stores a last known list of peer computing devices in the mesh network. The device also includes a a second storage device that operates regardless of whether any central processing unit in the computing device is awake or asleep. The second storage device includes a local block that stores a list of resources provided by the first computing device and a list of computing devices in the mesh network verified by the first computing device. The second storage device also includes a remote block that stores an unverified remote list of computing devices in the mesh network.

Abstract: File data for an operating system may be stored in a compressed format in a re-programmable semiconductor memory. The memory may be provided with a header and data for one or more file systems all stored in a compressed format. A device driver also stored in the memory may be utilized to decompress the data and to convert it to a format suitable for a particular file system or operating system.

Abstract: A method, device, and system are disclosed. In one embodiment the method includes causing a processor to enter into a first power state. Then an interrupt is received that signals the processor to leave the first power state. The method continues by causing the processor to remain in the first power state if the interrupt was received less than a minimum dwell time after the processor entered the first power state.

Abstract: A method, apparatus, system, and computer readable medium are disclosed. In one embodiment the method includes detecting a virtual machine (VM) attempting to communicate with a device coupled to a computer system using a first software plug-in interface that is incompatible with the device. The method continues by temporarily removing the VM from controlling system. Then the first software plug-in interface in the VM is replaced with a second software plug-in interface, which is compatible with the device, without the knowledge of the VM. Then control is returned to the VM and the VM is allowed to resume the communication attempt with the device using the second software plug-in interface.

Abstract: A method, device, and system are disclosed. In one embodiment the method includes grouping multiple memory requests into multiple of memory rank queues. Each rank queue contains the memory requests that target addresses within the corresponding memory rank. The method also schedules a minimum burst number of memory requests within one of the memory rank queues to be serviced when the burst number has been reached in the one of the plurality of memory rank queues. Finally, if a memory request exceeds an aging threshold, then that memory request will be serviced.

Abstract: A device, method, and computer readable medium are disclosed. In one embodiment the device includes a first network packet storage queue that is capable of storing incoming network packets from a network. The device also includes a second network packet storage queue that is capable of storing incoming network packets from a network. The device also includes flush logic to synchronize a flush of the network packets stored in the first and second network packet storage queues. The flush is triggered by a flush event affecting at least one of the storage queues.

Abstract: A method, device, and system are disclosed. In one embodiment method includes determining a left edge and right edge of a valid data eye for a memory. The method continues by periodically checking the left and right edges for movement during operation of the memory. If movement is detected, the method retrains the valid data eye with an updated left edge and right edge.

Abstract: A method, device, and system are disclosed. In one embodiment the method includes supplying a processor with a first voltage. The method also includes allowing the processor to function within an enhanced processor halt state at the first voltage. The first voltage is a voltage below the lowest compatible voltage for the enhanced processor halt state. The method allows the processor to execute instructions upon waking from the enhanced processor halt state at the first voltage by throttling a maximum throughput rate of instructions being executed in the processor.

Abstract: A system, device, and method are disclosed. In one embodiment the system includes an optical link and a peripheral device optically coupled to the optical link. The system also includes a host controller, such as a graphics, network, or I/O controller. The system also includes a unified optical connector port, which is optically coupled to the optical link and electrically coupled to the first host controller. The port has a wavelength allocation unit that can allocate an optical wavelength for an optical signal that is utilized to communicate with the peripheral device. The port also includes an electrical-to-optical transmission unit capable of converting an electrical signal, received from the host controller, to the optical signal that was allocated at the first optical wavelength. The electrical-to-optical transmission unit is also capable of transmitting one or more data packets within the first optical signal to the peripheral device across the optical link.

Abstract: A distributed direct memory access (DMA) method, apparatus, and system is provided within a system on chip (SOC). DMA controller units are distributed to various functional modules desiring direct memory access. The functional modules interface to a systems bus over which the direct memory access occurs. A global buffer memory, to which the direct memory access is desired, is coupled to the system bus. Bus arbitrators are utilized to arbitrate which functional modules have access to the system bus to perform the direct memory access. Once a functional module is selected by the bus arbitrator to have access to the system bus, it can establish a DMA routine with the global buffer memory.

Abstract: A technique to reduce the latency of a remote DNS lookup operation is disclosed. More specifically, a machine-readable medium, method, device, and system are described that scan a document when it is retrieved from the Internet. The scan takes place for one or more patterns, where each pattern denotes an Internet host name. The technique then asynchronously causes an Internet Domain Name System (DNS) server to translate each Internet host name pattern discovered from the document scan to an associated Internet Protocol (IP) address. The technique then asynchronously stores each translated IP address in a local DNS cache.

Abstract: A method and system are disclosed. In one embodiment the method includes computing, during runtime, an active hash value of a hypervisor on a computer platform using an authenticated integrity agent. The method also includes comparing the active hash value to a registered hash reference value. The method also includes verifying the integrity of the hypervisor when the active hash value and the registered hash reference value match.

Abstract: A system, method, and device are disclosed. In one embodiment, the device comprises logic to determine whether a received transaction layer packet (TLP) has a compressed header and, if the received TLP has a compressed header, logic to decompress the header.

Abstract: An apparatus and method are disclosed. In one embodiment, the apparatus trains a memory link using a signal alignment unit. The signal alignment unit aligns a read data strobe signal that is transmitted on the link with the center of a read data eye transmitted on the link. Next, the signal alignment unit aligns a receive enable signal that is transmitted on the link with the absolute time that data returns the data lines of the link a column address strobe signal is sent to the memory coupled to the link. Next, the signal alignment unit aligns a write data strobe signal transmitted on the link with the link's clock signal. Finally, the signal alignment unit aligns the center of the write data eye transmitted on the link with the write data strobe transmitted on the link.

Abstract: A method, device, and system are disclosed. In one embodiment, the method includes programming a first On Die Termination (ODT) value into a first plurality of dynamic random access memory (DRAM) devices. The first plurality of DRAM devices are located on a dual inline memory module (DIMM). Additionally, the method also includes programming a second ODT value into a second plurality of additional DRAM devices. The second plurality of additional DRAM devices are also located on the DIMM. The method also specifies that the first and second ODT values are not the same value.