Abstract: A method, device, system, and computer readable medium are disclosed. In one embodiment the method includes dynamically associating a newly active port in a computer system with a first host controller. The first association happens when a total number of currently active ports in the computer system is less than a maximum capacity number of ports for the first host controller. The method also includes dynamically associating the newly active port in the computer system with a second host controller. The second association happens when the total number of currently active ports in the computer system is greater than or equal to the maximum capacity number of ports for the first host controller. In this method, each port, the first host controller, and second host controller all utilize the same protocol.

Abstract: A circuit, method, and system are disclosed. In one embodiment the circuit comprises a ring oscillator circuit having a plurality of delay elements, the ring oscillator circuit to generate a clock signal frequency, a checker circuit to compare a count of clock signal oscillations observed per complete loop of the ring oscillator circuit to a reference count, and to set a flag signal if the clock signal oscillation count is above a high threshold amount or below a low threshold amount.

Abstract: A method, device, and system are disclosed. In one embodiment, the method comprises transitioning one or more lanes of a multi-lane serial link from a fully operational power state to a low power state and keeping one or more other lanes of the multi-lane serial link in the fully operational power state to allow one or more data transfers across the remaining operational lanes in the link.

Abstract: A system includes an interconnect within an integrated circuit, and a first fuse-disabled design block within the integrated circuit that has an internal static random access memory (SRAM). The first fuse-disabled design block is coupled to the interconnect. The system also includes a memory controller that is coupled to the interconnect. The memory controller is capable of selecting the internal SRAM and allocating the internal SRAM for storage accessible by one or more devices external to the first fuse-disabled integrated peripheral.

Abstract: A method and system are disclosed. In one embodiment the method includes a first device sending a stream of packets in a sequence across a network to a second device. In the sequence of packets there are a number of data packets and one or more synchronization packets. The synchronization packets are interspersed throughout the data packets. The method also includes the second device being capable of dropping any of the received data packets in the sequence arriving more than a first delta of time threshold value after the arrival of the most recent synchronization packet.

Abstract: A method and apparatus for high performance volatile disk drive (VDD) memory access using an integrated direct memory access (DMA) engine. In one embodiment, the method includes the detection of a data access request to VDD memory implemented within volatile system memory. Once a data access request is detected, a VDD driver may issue a DMA data request to perform the data access request from the VDD. Accordingly, in one embodiment, the job of transferring data to/from a VDD memory implemented within an allocated portion of volatile system memory is offloaded to a DMA engine, such as, for example, an integrated DMA engine within a memory controller hub (MCH). Other embodiments are described and claimed.

Abstract: In some embodiments, a chip includes a link interface, monitoring circuitry to provide an activity indicator that is indicative of activity of the chip, and scheduling circuitry to schedule commands. The chip also includes mode selection circuitry to select a first mode or a second mode for the scheduling circuitry depending on the activity indicator, wherein in the first mode the scheduling circuitry schedules certain commands as separate single commands and in the second mode the scheduling circuitry schedules at least one consolidated command to represent more than one of the separate single commands. Other embodiments are described.

Abstract: Machine-readable media, methods, and apparatus are described to issue message signaled interrupts. In some disclosed embodiments, a device generates message signaled interrupts in a manner that enables a device driver written with level-sensitive semantics to properly service the device despite the edge-triggered characteristics message signaled interrupts.

Abstract: A method, device, and system are disclosed. In one embodiment, the method comprises discovering a failure on a PCI Express interconnect, determining whether a failure override bit has been set to override the standard PCI Express Polling. Compliance state for the failure on the PCI Express interconnect, and if the failure override bit has been set, entering PCI Express Polling. Configuration state if any one lane of the interconnect successfully completes the transmitting and receiving training sequence requirements in PCI Express Polling.Active state.

Abstract: A method and device are disclosed. In one embodiment the method includes driving a first clock domain reference signal on a first clock tree and driving a second clock domain reference signal on a second clock tree. The first tree routes the first signal from a PLL to a first clock domain drop off circuit and the second tree routes the second signal from the PLL to a second clock domain drop off circuit. A jitter produced from the second tree is less than a jitter produced from the first tree. The method continues by detecting any phase misalignment between the first signal and the second signal. The method also causes the first signal to be delayed so that it aligns with the second signal.

Abstract: Hot plug modules comprising processors, memory, and/or I/O hubs may be added to and removed from a running computing device without rebooting the running computing device. The hot plug modules and computing device comprise hot plug interfaces that support hot plug addition and hot plug removal of the hot plug modules.

Abstract: In some embodiments, a chip includes a request queue to include write requests, and scheduling circuitry to schedule commands including commands in response to the write requests. The chip also includes mode selection circuitry to monitor the request queue and in response thereto to select a first or a second mode for the scheduling circuitry, wherein in the first mode the scheduling circuitry schedules certain commands as separate single commands and in the second mode the scheduling circuitry schedules consolidated commands to represent more than one separate single command. Other embodiments are described.

Abstract: A wearable data processing system includes a high power radio module and a low power radio module. The high power radio module may retrieve data from radio frequency identifier (RFID) tags. The low power radio module may transmit data to a base station data pertaining to the detected RFID tags. The low power radio module may also receive a power management signal from a gate radio. The gate radio may have an adjustable range. A power management engine in the wearable data processing system may determine whether the low power radio module is receiving the power management signal from the gate radio. The power management engine may also activate and deactivate the high power radio module, depending on whether the low power radio module is receiving the power management signal from the gate radio. Other embodiments are described and claimed.

Abstract: A method, apparatus, and system are disclosed. In one embodiment the method comprises determining whether a feature on a device is permitted to be enabled, determining whether a total number of enabled features on the device is less than or equal to a maximum number of allowable features on the device, and allowing the enabling of the device feature if the device feature is permitted to be enabled and the total number of enabled features on the device is less than or equal to the maximum number of allowable features on the device.

Abstract: A method, apparatus, and system are disclosed. In one embodiment the method detects a temperature event in a processor and then modifies the bus frequency of an I/O bus coupled to an I/O controller hub in response to the temperature event. In another embodiment, the apparatus includes a temperature detection unit that detects a temperature event in a processor and, additionally, a bus frequency modification unit that will modify the bus frequency of an I/O bus in response to the temperature event.

Abstract: A method and apparatus to provide communications over a packet channel, including applying a forward error correction (FEC) code to a first group of data packets to create a coded group of packets by supplementing a set of parity packets to the first group of data packets; and transmitting the first group of data packets, and transmitting the set of corresponding parity packets after the first group of data packets have been transmitted. In response to receiving a positive acknowledgement corresponding to the first group of packets, ceasing to send parity packets corresponding to the first group of packets and sending a second group of data packets dependent on the first group of data packets. In response to not receiving the acknowledgment, not sending the second group of data packets and continuing to transmit the parity packets corresponding to the first group of data packets.

Abstract: A NoDMA cache including a super page field. The super page field indicates when a set of pages contain protected information. The NoDMA cache is used by a computer system to deny I/O device access to protected information in system memory.

Abstract: A method, circuit, and system are disclosed. In one embodiment, the method comprises sending a step pulse across a serial advanced technology attachment (SATA) transmission line, determining the length of time the transmission line takes to charge from common mode voltage to supply voltage, and determining whether a device is connected to the SATA transmission line based on the length of the transmission line charge time.

Abstract: A method, circuit, and system are disclosed. In one embodiment, the method comprises receiving a differential clock signal from two clock signal lines into a first differential pair of transistors of a first size, receiving the differential clock signal from the two clock signal lines into a second differential pair of transistors of a size smaller than the first size, converting the differential clock signal into a single-ended clock signal, outputting the single-ended clock signal through an inverter, and synchronizing any differential clock phase error by controlling the transconductance between the first differential pair of transistors and the second differential pair of transistors.

Abstract: A method, device, and system are disclosed. In one embodiment, the method comprises acquiring vehicle fuel consumption information from a plurality of geographic locations, compiling the information to a map, and creating a low fuel consumption path between two locations on the map using the information.