Abstract: An active memory 14 is provided which includes a data memory 20 including rows and columns of storage locations for holding data and computational results. A broadcast memory 22 includes rows and columns of storage locations for holding control instructions. Computing circuitry 26 is provided which is operable to perform a first computational operation using first and second words of data retrieved from the data memory 20 and perform a second computational operation using a result from the first operation and a result from a previous operation. Control circuitry 24 is operable in response to control instructions received from broadcast memory 22 to control the transfer of the first and second words of data from the data memory 20 to said computing circuitry 26 and the performance of the first and second operations.

Abstract: The described embodiments of the present invention provide an apparatus and method for rapidly programming field programmable devices. A dummy antifuse is provided on the field programmable device for testing prior to actual programming. The current drawn by the device is measured by the programming apparatus until an adequate soaking current is measured while programming the test antifuse. The programming apparatus then records the time required this current level and selects that time as the programming period T.sub.p. This programming time T.sub.p is then used to program the entire device. T.sub.p is now the minimum time required given the process variations of this particular device to adequately program the antifuses which must be blown.

Abstract: An integrated circuit capacitor has a semiconductor die and a plurality of field effect transistors fabricated on the die and having gates, sources and drains. The gates are connected to each other as one side of the capacitor. The sources and drains are connected together as another side of the capacitor. A color palette has a die with circuitry including a dot clock buffer with transistors connected to supply rails and the integrated circuit capacitor having a plurality of the parallel-connected field effect transistors connected across the supply rails. The dot clock buffer has an output distributed directly to the rest of the circuitry. Other capacitors, buffers, systems and methods are also disclosed.

Abstract: A flash waveform analyzer (10) includes a transmission line (12) for propagating a signal from an input (14). The transmission line (12) contains a plurality of samplers (16) located at different points along the transmission line (12). Each sampler (16) is activated by a strobe pulse from a strobe source (18) in order to measure a characteristic of the signal at the different points along the transmission line (12). The propagation velocity of the signal is made slower than the propagation velocity of the strobe pulse by using a different dielectric constant in the transmission line (12) than that of the strobe delay line (17). The characteristic measured by each sampler (16) is sent to a multiplexer (20) that selectively outputs the measured characteristic from each sampler (16) to an analog-to-digital converter (22) for processing and subsequent analysis.

Abstract: A tri-state driver circuit is disclosed which provides rail-to-rail output swings and does not consume a significant amount of d.c. power.

Abstract: A current duplicator (10) is provided for receiving a calibration current and providing an output current to a load (10). Current duplicator (10) includes a transconductor (14) having a differentially coupled input with a parasitic capacitance for storing a differential voltage during a supply period. This parasitic capacitance also converts a difference current into the voltage during a feedback period. The difference current is equal to the difference between the output current and the calibration current. Transconductor (14) converts the voltage into the output current. The current duplicator also includes a first switch network for coupling the output current to the load (12) during the supply period. The output current remains within a predetermined amount from the calibration current during the supply period. A second switch network feeds back the difference current to the input during the feedback period at least until the output current becomes substantially equal to the calibration current.

Abstract: Plasma generator (10) includes chamber (14) for containing the plasma source and a plurality of coils (12) located inside of chamber (14). Located external to chamber (14) are a plurality of permanent multipolar magnets (34) operable to establish a magnetic field in the plasma source along the surface of chamber (14) and a set of electromagnets (36) located outside of chamber (14), which define a preferred propagation direction for a whistler wave in chamber (14). Coils (12) resonantly inductive couple RF power to the whistler wave so as to transfer a sufficient amount of energy to the plasma source to induce a plasma state in the plasma source. Coils (12) also generate time varying electromagnetic fields which also sustain the plasma state in the plasma source.

Abstract: Programmable circuitry (10) is provided including a plurality of logic modules (12) each having at least one input conductor (16). A nearest neighbor conductor (36) is fusibly coupled to output circuitry (25) of a selected logic module (12), the nearest neighbor conductor (36) intersecting the input conductor (16) of a nearest neighbor logic module (12). A fuse (40) disposed at the intersection of the nearest neighbor conductor (36) and the input conductor (16) of the nearest neighbor logic module (12) is provided for selectively establishing electrical coupling therebetween.

Abstract: A method of fabricating a resistor which comprises the steps of providing a semiconductor substrate, preferably silicon, forming a layer of oxide over the substrate, providing on the layer of oxide a region of material having a substantially higher resistance in the undoped state than in the doped state, preferably polysilicon, patterning a region over the material to expose predetermined regions of the material, doping the exposed regions of the material to a predetermined doping level substantially greater than the doping level of the original material, masking the doped regions and a portion of the previously unexposed regions of the material on spaced apart portions of the doped regions and etching away the exposed region of material external to the doped regions and external to the portion of the previously unexposed regions of the material on spaced apart portions of the doped regions.

Abstract: A differential emitter coupled logic circuit having an output and a compliment of the output, the circuit comprising: a first emitter coupled transistor pair (Q17 and Q18); a second emitter coupled transistor pair (Q19 and Q20); a third emitter coupled transistor pair (Q25 and Q26); a fourth emitter coupled transistor pair (Q33 and Q34); a filch emitter coupled transistor pair (Q37 and Q38); and a sixth emitter coupled transistor pair (Q35 and Q36).

Abstract: NH.sub.4 OH:H.sub.2 O.sub.2 :H.sub.2 O solution is used for selective wet etching of different films such as TEOS oxide, borophosphosilicate glass (BPGS), nitride, doped polysilicon, and thermal oxide.

Abstract: A processing system (10) includes a mass flow controller (22) operating in response to a plurality of control signals, and a data processor system (40). Data processor system (40) collects and stores data characterizing the plurality of control signals from the mass flow controller (22). Features are extracted from the data which characterizes failure modes of the mass flow controller (22), such as miscalibration and malfunction. Data processor system (40) combines there features represented by membership functions using fuzzy rules to diagnosis anomalous operation of the mass flow controller (22). If the mass flow controller 22 is miscalibrated, the data processor system 40 automatically recalibrates it by the rate-of-nie calibration procedure. In case of malfunction, a warning is raised to the operator. Processing system (10) employs self-learning techniques to initialize and refine the knowledge base.

Abstract: A process chamber purge module (56) is provided, including a stack module (60) and a process chamber liner (62). The stack module comprises a plurality of quartz plates (100, 110, and 116) having flow apertures to permit radial and axial flow of a purge gas to the backside of a semiconductor wafer (18). The process chamber liner (62) isolates the process chamber walls from the process chamber process environment by flowing between the liner and the walls a portion of the purge gas. Process chamber liner (62) comprises a quartz cylindrical collar that operates to decouple the process chamber (16) process environment (20) from the process chamber collar walls (42). The stack module (60) decouples the process chamber optical/vacuum quartz window (64) from the semiconductor wafer (18) during a heated semiconductor wafer fabrication process. By flowing purge gas to the backside of the semiconductor wafer (18), the present invention prevents reactive process gas interaction with the semiconductor wafer backside.

Abstract: A system (60) and method for monitoring, evaluating and controlling the uniformity of a semiconductor wafer fabrication process is provided for use in manufacturing integrated circuits on semiconductor wafers (40). By using in situ ellipsometry (20) in conjunction with statistical modeling methods, the spatial etch rate pattern across a semiconductor wafer (40) may be inferred as a function of the process conditions. A predicted mean etch rate may be calculated for other locations (46 and 48) on the semiconductor wafer surface (42) by using the mean etch rate measured at the selected ellipsometer site (44) and individual spatial etch rate models developed for each site (44 and 48) based on statistically designed experiments. The predicted mean etch rate at the other sites (46 and 48) is also a function of the fabrication process conditions.

Abstract: An electrical power source or power cell (10) includes a semiconductor material (12) having an N region (14), a P region (16) and a P-N junction (18). A radioactive source (24) associates with P-N junction (18) and emits energy or radioactive particles (26) into semiconductor material (12). In semiconductor material (12), electron-hole pairs are formed in N region (14) and P region (16) to cause electrical current to pass through P-N junction (18) and produce, therefrom, electrical power.

Abstract: The present invention is a dynamic type semiconductor memory device comprising a plurality of memory cells (not shown), plural pairs of bit lines, a first sense amplifier (20), arranged for each of the plural pairs of bit lines, for amplifying a bit line signal. A pair of data input/output lines extracts data from a pair of bit lines. A second sense amplifier (22), is arranged for each of said plural pairs of bit lines and consists of first and second driver MOS transistors (52 in FIG. 3) gates of which are connected to the pair of bit lines. The second sense amplifier is activated when said first sense amplifier is activated, for amplifying signals of the pair of data input/output lines. First and second column selecting transistors (30 in FIG. 2) are inserted between the pair of data input/output lines and the second sense amplifier and gates of which are connected to a column selecting line. A first write transistor (54 in FIG.

Abstract: A memory system 10 is provided including a processor 12 and an active memory device 14 coupled to a processor 12. Active memory 14 includes a first memory 20 for storing a plurality of possible addresses and a second memory 22 for storing an actual address received from processor 12. Circuitry 26 is provided for identifying at least one active address from ones of the possible addresses stored in first memory 20 as a function of the actual address stored in second memory 22.

Abstract: A high speed signal driving scheme is disclosed which reduces timing delays associated with a signal line precharged to a selected voltage by limiting the voltage transition on the signal line from its precharged voltage.

Abstract: A described embodiment of the present invention includes an anti-fuse comprising: a first conductive layer having a horizontal major surface and having a substantially vertical sidewall; a thick insulating layer formed on the horizontal major surface of the first conductive layer; a dielectric layer formed on the vertical sidewall; and a second conductive layer formed on the dielectric layer. In an additional embodiment, the first and/or second conductive layers comprise polycrystalline silicon and a conductive material selected from the group of titanium, tungsten, molybdenum, platinum, titanium silicide, tungsten silicide, molybdenum silicide, platinum silicide, titanium nitride and combinations thereof.