Abstract: The described embodiments of the present invention provide a memory cell and method for fabricating that memory cell and memory array including the cell. The memory cell is a trench capacitor type having a transistor (1-1-2) formed on the surface of a major face of a substrate (16) and having a capacitor (2-1-2) formed in the substrate around the periphery of a trench. The capacitor and transistor are connected by a buried, heavily doped region (26) having the opposite conductivity type from the substrate. A doped storage area (24) having the same doping type as the buried doped region surrounds the trench. A field plate (30) is formed in the trench separated from the storage region by a dielectric layer (32). The field plate extends onto the isolation areas between memory cells thus providing isolation between cells using a minimum of surface area.

Abstract: The described embodiments of the present invention provide a method in which the circuit configuration of redundancy circuitry in a random access memory can be simplified and the setting operation of the address of the defective memory cell is also simplified. In one described embodiment, the redundant circuit includes a fuse decoder (11), which functions as the address-generating circuit for the address of the defective memory cell, and a latch circuit (21). A write operation to the defective memory cell on the write port containing the fuse decoder (11) causes the address of the defective cell to be stored in the latch circuit. Each input/output port, except the input port using the fuse decoder, includes a comparator (22) for comparing the address for an operation on the respective port to the address stored in the latch circuit.

Abstract: The described embodiments of the disclosed invention provide a semiconductor devices, test apparatus for the semiconductor devices and a method for testing the semiconductor devices. The semiconductor devices may have many different types of pin counts and configurations. Each semiconductor device includes standardized test circuitry. The necessary pins to operate the test circuitry are included in a standardized position on the semiconductor devices relative to the positioning of the semiconductor devices in the test apparatus. Thus a single test apparatus may be utilized to test semiconductor devices having a wide range of pin configurations.

Abstract: A variable frequency oscillator (19) and method of producing an oscillating signal are provided in which a current mirror (12) receives a control current and generates a mirrored current. A capacitor (20) is coupled to the current mirror (12) and charges and discharges through the current mirror (12) based on the direction of the mirrored current. A trigger (22) is coupled to the capacitor (20) and outputs a first voltage level when the capacitor (20) charges to a first voltage threshold and outputs a second voltage level when the capacitor (20) discharges to a second voltage threshold. A switch (14) is coupled to the current mirror (12) and the trigger (22) for changing the direction of the mirrored current based on the output voltage of the trigger (22).

Abstract: A MOS to ECL level conversion circuit is disclosed which comprises transistors forming a differential pair connected to a current source. One of the transistors is configured as a diode and is self-referencing in that it supplies its own reference voltage level.

Abstract: This invention provides a FIFO memory device having a simple circuit structure without using a cache memory, and line buffers used in the FIFO memory device having a simplified circuit structure.The FIFO memory device comprises a read line buffer (5) having a two-step structure in place of a cache memory which stores and outputs the first data. The read line buffer (5) outputs the data from the memory array (4). Namely, the read line buffer (5) comprises first-step master latch circuits (33) and (34) and a second-step slave latch circuit (37), and the single master latch circuit (33) functions equivalent to the cache memory. In addition, the number of line buffers is reduced by multiplying the selection of memory array (4) bit lines (BL) using transfer gates (11-14).

Abstract: The present invention teaches a new method for fabrication of DRAM cells having an upper capacitor plate over the polysilicon storage gate. To provide a very high specific capacitance and very good integrity between the first poly storage gate and the (second or third poly) upper capacitor plate, the dielectric is formed as an oxide/nitride composite which is then reoxidized. This provides the advantages of high dielectric integrity, high specific capacitance, uniformity and reproducibility.

Abstract: A dRAM cell and array of cells, together with a method of fabrication, are disclosed wherein the cell includes one field effect transistor and one storage capacitor with both the transistor and the capacitor formed in a trench in a substrate. The transistor source, channel and drain and one capacitor plate are formed essentially vertically in the bulk substrate sidewalls of the trench, and the gate and other capacitor plate are formed in two regions of material inserted into the trench and isolated from the bulk by an insulating layer. Signal charge is stored on the capacitor material inserted into the trench by an electrical connection of the bulk substrate source to the capacitor material through the insulating layer. In preferred embodiments word lines on the substrate surface connect to the upper of the inserted regions which forms the gate, and bit lines on the substrate surface form the drains.

Abstract: A dRAM cell and array of cells, together with a method of fabrication, are disclosed wherein the cell includes one field effect transistor and one storage capacitor with the capacitor formed in a trench in a substrate and the transistor channel formed by epitaxial growth on the substrate. The transistor source and drain are insulated from the substrate, and the transistor may be adjacent the trench or on the upper portion of the trench sidewalls. Signal charge is stored on the capacitor plate insulated from the substrate.

Abstract: An elevated transistor is provided having minimized junctions (33) and a polysilicon pad (27) over the transistor insulating regions (12) and partially over the moat (14). A conductive layer (32) overlays the polysilicon pad (27) and partially overlays the moat (14) in the interim areas (29).

Abstract: Preferred embodiments include silicon complementary MOSFETs with titanium silicided junctions (38, 58) and direct contacts of aluminum metallization (61, 62) to the p junctions (58) which avoids the high contact resistance of the silicide (60) to p silicon (58). Preferred embodiments also include silicided polysilicon lines without corresponding silicided MOSFET junctions.

Abstract: An on-chip transient event detector (FIG., 1) is fabricated onto an integrated circuit chip to provide rapid response to a detected event, such as a transient radiation dose or other condition that can cause transient current pulses. The transient event detector includes a detector circuit 10 that includes a narrow p-channel FET (12), and a wide n-channel FET (14). These detector transistors are coupled together and biased so that the narrow-channel transistor is normally on and the wide-channel transistor is normally off. A transient event, such as a photocurrent induced by radiation, causes a current pulse in the normally off wide-channel transistor that is sufficiently greater than the current in the narrow-channel transistor to cause a change in logic output, providing an event signal. The event signal can be used to disable memory WRITE operations during the transient event. The detector circuit can be integrated with an on-chip time-delay circuit (30) to provide a time-delayed system reset signal.

Abstract: The described embodiments of the present invention provide a bipolar transistor using an integrated field effect load device with one end of the load device integrally formed with the base of the transistor. The gate of the load device is connected to the emitter of the transistor. This structure is particularly advantageous in bipolar-complementary metal oxide semiconductor (BiCMOS) integrated circuitry. The unconnected end of the load device may be connected to the emitter using standard metal interconnection techniques or local interconnection techniques. In an additional embodiment of the invention, the end of the load device not connected to the base may be left unisolated to the substrate and thus connected to ground. It often occurs that the emitter of the bipolar transistor will be connected to ground and thus an automatic connection of the load device between the base and the emitter can be realized.

Abstract: The described embodiments of the present invention show a high voltage bipolar transistor integrated into a bipolar complementary metal oxide semiconductor integrated circuit. The high voltage transistor is fabricated using the available processing steps for fabricating other components in more standard BiCMOS processes. The collector of the transistor is formed using a buried N type region in a P substrate. A P well, rather than the conventional N well is formed above the buried N layer. The collector contact to the buried N layer is fabricated so as to surround the P well to provide a separate base region. A highly doped P type base region is formed with a P+ contact to this region. An N+ emitter is formed by out diffusion from a heavily doped polycrystalline silicon layer formed in contact with the base region.

Abstract: The present invention teaches a new method for fabrication of DRAM cells having an upper capacitor plate over the polysilicon storage gate. To provide a very high specific capacitance and very good integrity between the first polysilicon storage gate and the (second or third polysilicon) upper capacitor plate, the dielectric is formed as an oxide/nitride composite which is then reoxidized. This provides the advantages of high dielectric integrity, high specific capacitance, uniformity and reproducibility.

Abstract: A method for forming a quantum effect switching device is disclosed which comprises the step of forming a heterostructure substrate 10. A silicon nitride layer 22 is formed on an outer surface of the substrate 10. An aluminum mask body 30 is formed using a lift-off procedure. Aluminum mask body 30 is then used to form a silicon nitride mask body 32 from the silicon nitride layer 22 using a CF.sub.4 /O.sub.2 reactive ion etch process. A boron trichloride etch process is then used to form a dual column structure 34 while removing the aluminum mask body 30. A buffered HF wet etch process removes the silicon nitride mask body 32. Separate metal contacts can then be made to electrically separate points on the outer surface of the dual column structure 34.

Abstract: The described embodiments of the present invention provide a method and structure for actively controlling the voltage applied to the channel of field effect transistors. In the described embodiments, a transistor connected to the channel region is fabricated. The channel transistor has opposite conductivity type to the transistor using the main channel region. The source of the channel transistor is connected to the channel and the drain of the channel transistor is connected to a reference voltage. The same gate is used to control the channel transistor and the main transistor. When a voltage which causes the main transistor to be on is applied, the channel transistor is off, thus allowing the channel to float and allowing higher drive current. On the other hand, when a voltage to turn off the main transistor is applied, the channel transistor is turned on, thus clamping the channel region to the reference voltage. This allows for consistent threshold voltage control of the main transistor.

Abstract: A low-temperature (650.degree. C. to 800.degree. C.) in-situ dry cleaning process (FIG. 2) for removing native oxide (and other contaminants) from a semiconductor surface can be used with either multi-wafer or single-wafer semiconductor device manufacturing reactors. A wafer is contacted with a dry cleaning mixture of germane GeH.sub.4 and hydrogen gas (51), such that the germane:hydrogen flow ratio is less than about 0.15:12000 sccm. The dry cleaning mixture can include a halogen-containing gas (such as HCl or HBr) (52, 54) to enhance cleaning of metallic contaminants, and/or anhydrous HF gas (53, 54) to further lower the process temperature. The dry cleaning process can be achieved by introducing some or all of the hydrogen and/or an inert gas as a remote plasma. The dry cleaning process is adaptable as a precleaning step for multiprocessing methodologies that, during transitions between process steps, reduce thermal cycling (FIGS. 3c-3e) by reducing wafer temperature only to an idle temperature (350.

Abstract: Contact etching is simplified by including a conformal etch stop layer underneath the interlevel or multilevel oxide (MLO). Etching through the unequal thickness of the MLO with sufficient overetching to reliably clear the thickest parts of the MLO layer will therefore not damage the silicon contact areas underneath the thinner parts of the MLO. Process control is also improved.Preferably this conformal etch stop layer is a conductor, and is grounded to configure a field plate over the entire surface of the chip.

Abstract: Bitlines (34) are formed by creating a diffused region (26) around the sidewalls and bottom of a trench (20). The trench (20) is filled with a conductive region (30), typically a refractory metal, refractory metal silicide.