Abstract: A void (60) is created in a semiconductor substrate (52) by forming a cavity which is subsequently filled with an organic polymer (66). The organic polymer is masked and etched to form a spacer. A dielectric (70) fills the portions of the cavity where the organic polymer was etched away. The organic polymer is subsequently etched leaving a void.

Abstract: A BICMOS semiconductor device (20) and method for its fabrication is disclosed. Bipolar, PMOS, and NMOS transistors (22, 26, and 28) are isolated from one another by a P type channel stop (54) implantation step prior to formation of a field oxide (56). An N type channel stop (64) implantation step occurs after the field oxide (56) formation. In addition, the N type channel stop (64) implantation step utilizes the same mask as is used to implant N dopant which forms a deep collector region (62) for the bipolar transistor (22).

Abstract: A capped silicide process which prevents reactions between the siliciding metal and oxygen contaminants and prevents silicon outdiffusion. In one form the process entails formation of a cap layer over the metal layer prior to performing the silicide reaction and subsequent removal of the cap layer with an isotropic etchant that does not degrade the underlying silicide.

Abstract: The present invention is described in conjunction with the fabrication of a dRAM cell which an important application of the present invention. The described cell provides a one-transistor/one-capacitor dRAM cell structure and array in which the cell transistor is formed on the sidewalls of a substrate trench containing the cell capacitor; the word and bit lines cross over this trench. This stacking of the transistor on top of the capacitor yields a cell with minimal area on the substrate and solves a problem of dense packing of cells.One capacitor plate and the transistor channel and source region are formed in the bulk sidewall of the trench and the transistor gate and the other plate of the capacitor are both formed in polysilicon in the trench but separated from each other by an oxide layer inside the trench.

Abstract: An electron image projector (10) is exposed to a heat source (22) to induce the emission of electrons (20) which flow from a pattern (14) of a mask (12) to a photoresist layer (18) of a substrate (16). An electron field (26) is applied across the substrate (16) and the mask (12) to accelerate the electrons (20) from the pattern (14) to the photoresist layer (18) to form a shape (24) on the photoresist layer (18) which reproduces the shape of the pattern (14). A projection system (28) can be disposed between the substrate (16) and the mask (12) to selectively direct the plurality of electrons (20) from the pattern (14) to the photoresist layer (18).

Abstract: A baseboard for orthogonal mounting of integrated circuit chips is described. Plural channels (14) are anisotropically etched in a silicon baseboard (10). A corresponding plurality of integrated circuit chips (12) are inserted into the channels (14). A number of baseboard contact pads (18) are formed adjacent each channel (14), and are solder bonded to corresponding chip conductor pads (16). Interconnect conductors (20, 28) provide connection of each baseboard pad (18) either to other chips (12) or to connector pads (22) located adjacent an edge (26) of the baseboard chip mount (10). A coating (30) of silicon carbide over the surface of the baseboard chip mount (10) improves the thermal efficiency of the assembly.

Abstract: The present invention provides a method for inhibiting the oxidation of a titanium layer during the direct reaction of the titanium with exposed silicon areas of an integrated circuit. In one embodiment of the present invention, a titanium nitride layer is formed on the surface of the titanium layer in the reactor where the titanium layer is deposited. The titanium nitride layer provides an effective barrier against oxidation. Thus, the formation of titanium dioxide is inhibited. In addition, in those areas where titanium nitride local interconnect is to be formed between diffused areas, the extra thickness provided by the top titanium nitride layer adds in the integrity of the conductive layers. By conducting the silicidation in a nitride atmosphere, diffusion of the nitride from the titanium nitride layer into the titanium layer and substitution of those lost nitrogen atoms by the atmosphere occurs thus providing a blocking layer for the formation of titanium silicide shorts.

Abstract: The described embodiment of the present invention provides a memory cell which is fabricated using a self-isolating structure and provides misalignment tolerance in the design of the cell thereby eliminating the need for additional area to be reserved for isolation structures and misalignment tolerances.

Abstract: P channel and N channel CMOS FETs (22, 24) and a process for their simultaneous fabrication with a minimal number of masking steps are disclosed. After formation of gates (30, 32) for both P channel FETs (24) and N channel FETs (22), a first N type dopant implanting step forms lightly doped drain extensions in both the P channel FETs (24) and the N channel FETs (22). A mask then protects the N channel FET area (22) while a P type dopant is implanted in source and drain regions (36) of the P channel FET (24) at a greater concentration than the prior implanted N type dopant. Another N type dopant implant occurs to both the P channel FET (24) and N channel FET (22). The N type dopant dosage used in this second N type dopant implantation step is greater than the dosage used in the first N type dopant implantation step.

Abstract: A circuit for assisting the charging of a line conductor having a distributed resistance and capacitance, such as a word line in a semiconductor memory device, is disclosed. In the conventional memory device, a driver circuit is disposed at one end of a word line, with a circuit for holding unselected word lines at the discharged voltage being disposed at the end of the word line opposite from the drive circuit. The invention is directed towards a pull-up circuit being disposed at the end of the word line opposite the driver circuit, the pull-up circuit having a transistor which is precharged to a high voltage prior to the active cycle. The precharged transistor is discharged as the selected word line is charged by the driver circuit, causing a driving node in the circuit to be connected to a high supply voltage.

Abstract: A method for patterning an integrated circuit workpiece (10) includes forming a first layer (16) of organic material on the workpiece surface to a depth sufficient to allow a substantially planar outer surface (36) thereof. A second, polysilane-based resist layer (22) is spin-deposited on the first layer (16). A third resolution layer (24) is deposited on the second layer (22). The resolution layer (24) is selectively exposed and developed using standard techniques. The pattern in the resolution layer (24) is transferred to the polysilane layer (22) by either using exposure to deep ultraviolet or by a fluorine-base RIE etch. This is followed by an oxygen-based RIE etch to transfer the pattern to the surface (18) of the workpiece (10).

Abstract: A process for forming backside contacts includes first forming an etch stop layer (12) beneath the surface of a silicon substrate. An active circuit is then formed in the silicon surface and associated metal interconnecting layers formed on the upper surface of the substrate. A planarizing layer is then formed on the upper surface of the substrate which is operable to be connected to a mechanical support. Thereafter, the backside of the substrate is etched away up to the etch stop layer (12). The thickness of the remaining substrate between the metal layers on the upper surface and the etch stop layer is sufficiently thin that the alignment marks on the upper surface can be seen through the substrate. These alignment marks are utilized to form vias from the backside to the active elements and then deposit and pattern interconnecting layers on the backside.

Abstract: A dRAM cell and array of cells, together with a method of fabrication, are disclosed wherein the cell includes one field effect transistor and one capacitor with both the transistor and the capacitor formed in a trench in a substrate. One capacitor plate and the transistor source are common and are formed in the lower portion of the trench sidewall. The transistor drain is formed in the upper portion of the trench sidewall to connect to a bit line on the substrate surface, and the channel is the vertical portion of the trench sidewall between the source and drain. The transistor gate fills the upper portion of the trench, and a heavily doped other plate of the capacitor fills the lower portion of the trench and makes contact with the substrate through the bottom of the trench.

Abstract: A process for planarizing the surface of a semiconductor wafer, after the wafer has been processed to form nonplanar topography layers on the blank, polished wafer, by mechanically removing material from this surface by abrasion until a desired planarity is attained. The mechanical planarization prevents step coverage problems encountered in further processing, avoids multiple step prior art planarizing methods, and can be effectively controlled by several simple methods.

Abstract: The following detailed description describes a dynamic random access memory (dRAM) cell. The described cell provides a one-transistor/one-capacitor dRAM cell structure and array in which the cell pass transistor is formed on the sidewalls of a trench containing the cell capacitor; the word and bit lines cross over this trench. The trench extends through an epitaxial layer into a substrate. The epitaxial layer and substrate are separated by a layer which serves as a diffusion barrier. This stacking of the transistor on top of the capcitor yields a cell with minimal area on the substrate and solves a problem of dense packing of cells. The diffusion barrier allows for the optimal doping of the epitaxial for operation of the transistor and optimal doping of the substrate for operation of the capacitor.

Abstract: The described embodiments of the present invention provide structures, and a method for fabricating those structures, which include a memory cell formed within a single trench. A trench is formed in the surface of a semiconductor substrate. The bottom portion of the trench is filled with polycrystalline silicon to form one plate of a storage capacitor. The substrate serves as the other plate of the capacitor. The remaining portion of the trench is then filled with an insulating material such as silicon dioxide. A pattern is then etched into the silicon dioxide which opens a portion of the sidewall and the top portion of the trench down to the polycrystalline capacitor plate. A contact is then formed between the polycrystalline capacitor plate and the substrate. Dopant atoms diffuse through the contact to form a source region on a sidewall of the trench. A gate insulator is formed by oxidation and a drain is formed at the surface of the trench adjacent to the mouth of the trench.

Abstract: A dynamic random access memory cell (14) is disclosed which is characterized by a high capacity storage element and small lateral wafer area. The cell (14) is constructed with a word line (40) overlying a split bit line (48, 50), with an underlying transistor 30, and yet thereunder a high capacitance capacitor (34). The word line (40) includes a member (42) isolated from the bit line (36) and formed therethrough to provide the transistor gate conductor. The transistor gate insulator (44) covers the gate conductor (42), and is encircled by a transistor semiconductor region (46) forming a vertical transistor conduction channel. The split bit line elements (48, 50) are in electrical contact with an underlying transistor drain region (126). The transistor conduction channel (46) is also in contact with an underlying transistor source region forming one plate (52) of the capacitor (34). The capacitor plate (52) is a core which is enclosed annularly by dielectric isolation (54).

Abstract: A dRAM cell and array of cells, together with a method of fabrication, are disclosed wherein the cell includes one field effect transistor and one storage capacitor with both the transistor and the capacitor formed in a trench in a substrate. The transistor source, channel and drain and one capacitor plate are formed essentially vertically in the bulk substrate sidewalls of the trench, and the gate and other capacitor plate are formed in two regions of material inserted into the trench and isolated from the bulk by an insulating layer. Signal charge is stored on the capacitor material inserted into the trench by an electrical connection of the bulk substrate source to the capacitor material through the insulating layer. In preferred embodiments word lines on the substrate surface connect to the upper of the inserted regions which forms the gate, and bit lines on the substrate surface form the drains.

Abstract: A color signal is encoded into luminance and chrominance signals. Relationships between the luminance and chrominance signals, and the color components are computed. A color component signal is generated by matrixing these relationships. In addition, a signal processor may be used to combine other video images with the color component signal.

Abstract: A dynamic one-transistor read/write memory cell employs a trench capacitor to increase the magnitude of the stored charge. The trench is etched into the silicon surface at a diffused N+ capacitor region similar to the N+ bit line, then thick oxide is grown over the bit line and over the capacitor region, but not in the trench; a partial etch followed by regrowth of oxide is used prior to the final etch for most of the depth of the trench, to thereby reduce the effect of undercut. The upper plate of the capacitor is a polysilicon layer extending into the trench and also forming field plate isolation over the face of the silicon bar. A refractory metal word line forms the gate of the access transistor at a hole in the polysilicon field plate.