Abstract: An analog sampling processor includes an analog sampling filter, a sample amplitude comparison circuit, a switch and switch control circuitry. The analog sampling filter filters a filter input signal to produce a filtered signal. The sample amplitude comparison circuit compares amplitude of the input signal and the filtered signal to produce a comparator signal. The switch samples a processor input signal to produce a sampled signal. The switch control circuitry receives the comparator signal and input from a sampling control signal. The switch control circuitry combines the comparator signal from the sampling control signal to generate a control signal that controls the sampling characteristics of the switch.

Abstract: An isolation structure on an integrated circuit is formed using a shallow trench isolation process. On a substrate, a trench is formed. A thermal anneal is performed to oxidize exposed areas of the substrate to provide for round corners at a perimeter of the trench. The thermal anneal in performed in an ambient where a chlorine source is added to O.sub.2 in order to minimize facets while creating the round corners. Oxidation time is lengthened by introducing an inert gas during the thermal anneal.

Abstract: In accordance with the preferred embodiment of the present invention, a first-in-first out queue includes a buffer for storing data. A write pointer indicates a next position for data to be written into the buffer from an external interface. An input pointer indicates a next position for data to be read out to processing circuitry. An output pointer indicates a next position for data which has been processed by the processing circuitry to be returned to the buffer. A read pointer indicates a next position for data to be read out of the buffer to the external interface.

Abstract: A CF.sub.4 /H.sub.2 O.sub.2 plasma is used to remove residues remaining after an ashing step. On a substrate, a layer of photoresist is formed over an underlying layer. The layer of photoresist is developed to form a photoresist pattern. The underlying layer is etched using the photoresist pattern. The substrate, including exposed areas of the underlying layer, are subjected to a plasma comprising H.sub.2 O.sub.2 vapor and a gaseous fluorocarbon to remove residual polymers.

Abstract: To perform a secure operation, an original encrypted value is obtained from a memory. The original encrypted value is decrypted to obtain an original value and an original validity code. The original validity code is compared with a stored validity code. If the original validity code is equivalent to the stored validity code, the secure operation is performed on the original value to produce a new value. Then a permanent alteration is made to the stored validity code to produce a new stored validity code. The new value and the new stored validity code are encrypted to produce a new encrypted value. The new encrypted value is stored in the memory.

Abstract: A hardware implementation of a hashing algorithm is presented. In a first pipeline stage, a first memory stores input data for the hashing algorithm. Data is selected out of the first memory, for example, using a counter which is reset and incremented by differing values depending upon the round of the algorithm. A second memory stores constants used for the hashing algorithm. Constants are selected out of the second memory, for example, using a counter. An adder adds data from the first memory and a constant from the second memory with a state value selected, for example, using a multiplexer. The result is stored as an intermediate algorithm value in a first pipeline register. In a second pipeline stage a second adder adds one of a plurality of hashing function values to the intermediate algorithm value in the first pipeline register. The result is shifted. A third adder adds the shifted result to one of the plurality of state values and places the result into a second pipeline register.

Abstract: A heat sink is formed on a bonded semiconductor on insulator (SOI) wafer. A trench is formed which extends from a top of the bonded SOI wafer through an isolation region of the bonded SOI wafer to a base of the bonded SOI wafer. The base of the bonded SOI wafer is located below the isolation region of the bonded SOI wafer. A conductive pillar is formed in the trench. The conductive pillar extends from the top of the bonded SOI wafer through the isolation region of the bonded SOI wafer and is physically in contact with but electrically insulated from the base of the bonded SOI wafer. In the preferred embodiment, the conductive pillar is formed of doped polysilicon. The doped polysilicon is of a conductivity type which is different than the conductivity type of the base. Out-diffusion from the doped polysilicon forms a region within the base which electrically insulates the conductive pillar from the base.

Abstract: An isolation structure on an integrated circuit is formed using a shallow trench isolation process. A layer of buffer oxide is formed on a substrate. A layer of nitride is formed on the layer of buffer oxide. The layer of nitride and the layer of buffer oxide are patterned to form a trench area. The substrate including the trench area is subjected to a plasma comprising H.sub.2 O vapor, and a gaseous fluorocarbon or a fluorinated hydrocarbon gas to clean impurities on the trench area. The substrate is etched to form a trench within the trench area.

Abstract: The temperature of a wafer is controlled during a chemical mechanical polishing process. Fluid containment is provided on a wafer backing plate in contact with the wafer during the chemical mechanical polishing process. Transportation of fluid is provided to and from the fluid containment during the chemical mechanical polishing process. Temperature of the fluid is controlled in order to control temperature on the wafer during the chemical mechanical polishing process.

Abstract: A low pass filter includes an input, an output, a storage means, a switching means and a control means. The input receives an input signal. An output signal is generated on the output. The storage means is a sample storage element, for example, a capacitance. A first end of the storage means is connected to the output. The switching means is connected between the first end of the storage means and the input. The switching means, when closed, electrically connects the input to the first end of the storage means. When open, the switching means electrically isolates the input from the first end of the storage means. The control means controls the switching means. The control means generates a switching control signal. The switching control signal has a sampling frequency. The capacitance provided by the capacitance means and a pulse width of the switching control signal are selected so that a maximum cutoff frequency of the low pass filter is less than the sampling frequency divided by two.

Abstract: A circuit on a detachable device, such as a plug-in card, determines when the detachable device has been disconnected from a host device. The circuit includes a node, a power source, a switch and a control circuit. The node is connected to ground when the detachable device is connected to the host device. The node is disconnected from ground when the detachable device is disconnected from the host device. The switch is for connecting and disconnecting the node to the power source. The control circuit is for, repeatedly at a predetermined interval of time while the detachable device remains connected to the host device, causing the switch to connect the node to the power source for a first length of time. The control circuit, at the end of the first length of time, checks a voltage level of the node in order to detect whether the detachable device has been disconnected from the host device.

Abstract: A gate region of a transistor is prepared for receiving a deposit of metal. A chemical mechanical polishing process is performed to reduce thickness of an insulation layer above the gate region. At the end of the chemical mechanical polishing process, a portion of the insulating layer remains above the gate region. An etch process is performed to remove the portion of the insulating layer remaining above the gate region. The etch process also removes a portion of polysilicon within the gate region and removes a top portion of spacers on either side of the gate region. A polysilicon selective etch-back is performed to remove an additional portion of the polysilicon within the gate region.

Abstract: A method is used to detect a location of contaminant entry in a processing fluid production and distribution system. A wafer is placed in a clean container. The clean container is connected to a test point within the processing fluid production and distribution system. Processing fluid from the test point of the processing fluid production and distribution system is allowed to flow through the clean container. The wafer is dried. The wafer is then tested for the existence of contaminants.

Abstract: A method for transferring data is performed by a first input/output device in order to perform a data transaction with a host device. The first input/output device receives a first data transaction request from the host device. The first input/output device stops the first data transaction. The first input/output device then requests a data second transaction with a second input/output device and asserts a request signal. The first input output device continuously asserts the request signal even when receiving a stop signal from the second input/output device. The first input/output device retries the second data transaction with the second input/output while continuously asserting the request signal. Upon completing the second data transaction with the second input/output device, the first input/output device releases the request signal. The first input/output device then completes the data transfer with the host device.

Abstract: Within a dual gate oxide process, gate oxide is formed within regions on a substrate. Gate material, such as polysilicon, is placed over a first region. The gate material extends over field oxide surrounding the first region. Gate oxide within a second region is stripped. The gate material over the first region prevents gate oxide within the first region from being stripped. A new layer of gate oxide is formed within the second region. A first transistor gate is formed within the second region. The gate material which is over the first region is etched to form a second transistor gate.

Abstract: In the course of processing integrated circuits production wafers are placed within a plurality of production boats on a platform. A first baffle boat is placed at a front end of the plurality of production boats. The first baffle boat contains a first plurality of wafers made of quartz. A second baffle boat is placed at a rear end of the plurality of production boats. The second baffle boat contains a second plurality of wafers made of quartz. The plurality of production boats, the first baffle boat and the second baffle boat are placed within a processing chamber.

Abstract: An integrated circuit accesses encrypted data stored in an external memory, the integrated circuit includes a main memory for storing decrypted data. A processor within the integrated circuit utilizes the decrypted data in the main memory. A soft secure memory management unit (SMMU), within the integrated circuit, monitors data accesses by the processor. The soft SMMU signals the processor when the processor attempts to access first data which is not within the decrypted data in the main memory but is within the encrypted data stored in the external memory. When the soft SMMU signals the processor, the processor oversees transfer of the first data from the external memory and oversees decryption of the first data.

Abstract: A first synchronization signal is used by a master base station and a remote base station in a digital cordless communication system. The master base station generates a second synchronization signal. The second synchronization signal is used to transfer information over a transmission medium between the master base station and the remote base station. The master base station generates the first synchronization signal from the second synchronization signal. Information is transferred over the transmission medium between the master base station and the remote base station using the second synchronization signal. The remote base station generates the first synchronization signal from the second synchronization signal. The first synchronization signal is utilized by the master base station and the remote base station for digital cordless communication.

Abstract: A programmable resistor is composed of two layers. A first layer of the programmable resistor has a substantially lower resistance than a second layer of the programmable resistor. The programmable resistor is programmed by placing a signal across the programmable resistor. A resulting current generated by the signal travels in parallel through the first layer of the programmable resistor and the second layer of the programmable resistor. The voltage of the signal is of a sufficient level so that a first portion of the resulting current which travels through the first layer causes a break in the first layer of the programmable resistor. However, the voltage of the signal is not of a sufficient level to allow a second portion of the resulting current which travels through the second layer to cause a break in the second layer of the programmable resistor.

Abstract: A testing apparatus and method are for testing a plurality of logic blocks within an integrated circuit. The integrated circuit includes a test data input bus, a test data output bus coupled to the output of each logic block, and test enable means which includes selection means coupled between the plurality of logic blocks and the test data input bus. The test enable means selects a first logic block from the plurality of logic blocks, and the selection means selectively inputs to each logic block either normal operating input or the test data. The test results are received from the first logic block through the test data output bus.