Abstract: An I/O holdoff mechanism is used to compensate for I/O device inputs being fed through a latency introducing bus. A system includes one or more I/O devices connected through a serial bus to a controller device. Each I/O device includes at least one request pin which is connected to a peripheral device. A serializer in the I/O device responds to a voltage transition occurring on any request pin of the I/O device by forwarding, in a packet over the serial bus, an indicator. The indicator indicates a current voltage on the request pin of the I/O device on which the voltage transition occurred. The controller device includes a deserializer and a bus controller. The deserializer receives the first packet and outputs a signal which indicates a current value for the voltage on the indicated request pin. The deserializer includes a busy output which indicates when the deserializer is busy and when the deserializer is idle.

Abstract: In a text mode of a display controller, for each character of the text, a plurality of multiple-byte words are stored in a memory buffer. Each multiple-byte word contains an ASCII character code for the character, font attribute information for the character and at least one font line for the character. For each character font line to be displayed on the monitor, a multiple byte word is read. The attribute information and a first character font line are extracted from the multiple byte word. The display controller then constructs a character scan line for the character based on the attribute information and the first character font line. The character scan line may then be displaying on the monitor.

Abstract: An integrated circuit is tested when input/output pads of the integrated circuit are unconnected to any external device. In order to do this, for each of a subset of the unconnected input/output pads, a boundary scan register is provided. A test vector is scanned serially into the boundary scan registers. The test vector may then be applied to internal logic of the integrated circuit. While the test is in progress, the value contained within each boundary scan register is applied to an associated input/output pad so that, as a result, the test vector is applied to the subset of the unconnected input/output pads.

Abstract: A scan flip-flop includes a data input, a scan input, a mode selection input, a mode control input and a clock input. When the mode selection input is set to a first selection value, and the mode control input is set to a first control value, the scan flip-flop operates as a D flip-flop. When the mode selection input is set to a second selection value, the scan flip-flop shifts in a scan input value on the scan input when one of the mode control input and the clock input is toggled. Also, as long as the mode selection input is set to the first selection value, and the mode control input is set to a second control value, the scan flip-flop holds a current value within the scan flip-flop.

Abstract: A computing system encodes and emulates requests signals, such as DMA requests or interrupt requests. A first peripheral device is connected to a first request pin of a first input/output (I/O) device. When the first peripheral device asserts a first request signal on the first request pin, a serializer within the first I/O device generates a first packet. The serializer forwards the first packet to a serial out port of the first I/O device. The first packet identifies the type of request and the direction of the edge transition. The serial out port forwards the first packet to a serial in port of a controller device. Upon the serial in port receiving the first packet, an unserializer within the controller device asserts an emulated first request signal, the emulated first request signal being coupled to a first request controller within the controller device.

Abstract: A secure mode within a dual mode processor is implemented. In a general/external mode, the dual mode processor executes instructions provided from an external source. The instructions are supplied to the processor via input/output to the processor. Upon receiving a special software or hardware interrupt, the dual mode processor enters a secure/internal mode. The interrupt specifies a secure function stored in a read-only memory within the dual mode processor. Upon receiving such an interrupt, input/output to the dual mode processor is disabled. The identified secure function is executed by the processor. During execution of the secure function, any attempt to insert instructions not originating from the read-only memory are ignored. However, the processor may access data specifically identified by secure function being executed.

Abstract: The planarity of the dielectric layer over a processing layer is increased by adjustments made to a mask generated for patterning the processing layer. Active circuitry lines are generated for the mask. Also, a fill pattern is generated for the mask. The fill pattern is placed in areas of the mask not filled by the active circuitry lines. The active circuitry lines are combined with the fill pattern to produce a final pattern for the mask. In one embodiment, the fill pattern is generated by first over-sizing the active circuitry lines to form a first pattern. The first pattern is inverted to produce a negative of the first pattern. The negative of the first pattern serves as a marker layer. In addition, a dummy fill pattern is generated. An intersection of the marker layer and the dummy fill pattern is performed to produce an unsized fill pattern.

Abstract: A clock signal is extracted from a received signal. An edge detector detects edges of the received signal, where the received signal transitions between a logic 0 and a logic 1. A center between each pair of consecutive edges is determined. An extracted clock signal is generated. The phase of the extracted clock signal is varied based on the center between each pair of consecutive edges. For example, the center between each pair of consecutive edges is determined by counting a number of cycles of an over sampling signal which occurs between each pair of consecutive edges to obtain a bit width. The bit width is divided in half and the result added to an edge phase value to obtain a value for the center. Also, the phase of the extracted clock signal may be varied based on the center between each pair of consecutive edges as follows. An amount a plurality of centers varies from a center of the extracted clock signal is averaged to produce a phase error.

Abstract: Performance degradation resulting from hot carrier stress is determined using a special test circuit. The test circuit is formed using a string of inverters on an integrated circuit. The string of inverters is connected in series. Every other inverter in the string of inverters uses cascaded transistors so that performance of the inverters with cascaded are not degraded by introduced hot carrier stress. For example, odd numbered inverters are each constructed using cascaded PMOSFETs and cascaded NMOSFETs and even numbered inverters are each constructed using a single PMOSFET and a single NMOSFET. On an input of the string of inverters, a first signal is placed which transitions from logic 0 to logic 1. Propagation delay of the first signal through the string of inverters is measured. Also, a second signal which transitions from logic 1 to logic 0 is placed on the input of the string of inverters. Propagation delay of the second signal through the string of inverters is measured.

Abstract: A slip buffer includes a first-in-first-out memory, an input address generating means, an output address generating means, and a slip buffer control logic. The input address generating means generates addresses into which data is read into the first-in-first-out memory. The output address generating means generates addresses from which data is read from the first-in-first-out memory. The slip buffer control logic includes a first latch, a second latch and a slip address generation means. A first boundary address of a first frame boundary is stored in the first latch. The first latch includes a first validity bit which indicates whether the first boundary address is valid, A second boundary address of a second frame boundary is stored in the second latch. The second latch includes a second validity bit which indicates whether the second boundary address is valid.

Abstract: A method determines approximate propagation delay through logic devices within a library. Each logic cell within the library is characterized at baseline conditions to obtain parameters for each logic cell which define propagation delay through each logic cell at the baseline conditions. A subset of the logic cells are characterized at conditions varying from the baseline conditions to obtain scaling parameters. The scaling parameters modify values of the parameters for all logic cells within the library in order to approximate changes in propagation delay through each logic cell resulting from changes in the baseline conditions. In the preferred embodiment, the conditions varying from the baseline conditions includes a change in at least one of operating temperature, power supply voltage and process conditions.

Abstract: A method approximates propagation delay through a logic device. Operation of the logic device is divided into a first region and a second region. A boundary between the first region and the second is based on duration of input ramp to the logic device and amount of capacitive load driven by the logic device. For example, the boundary between the first region and the second occurs where for each value of the capacitive load, an output ramp for the logic device is one half complete when the input ramp is complete. When the logic device operates in the first region, a first formula is used to obtain a first value representing delay through the logic device. The first formula varies the first value based on the duration of the input ramp to the logic device and the capacitive load driven by the logic device. When the logic device operates in the second region, a second formula is used to obtain the first value.

Abstract: A cache memory controller and method for dumping the contents of a cache directory and a cache data random access memory (RAM) are described. In order to dump the contents of the cache directory, access to the cache data RAM is disabled by disabling the cache controller. Then, address tags within the cache directory are read sequentially from a reserved register. In order to dump the contents of the cache data RAM, new addresses are allocated to data in the cache data RAM. This is done, for example, by blocking writes to the cache data RAM while enabling read access from the cache data RAM and both read and write access to the cache directory. A reserved block of cacheable memory within, for example, the main system memory, is accessed. When the reserved block of cacheable memory is accessed, address tags for addresses of the reserved block of cacheable memory are written into the cache directory; however, data from the reserved block of cacheable memory is not written into the cache data RAM.

Abstract: Chip capacitors are attached to an integrated circuit package. Strips of synthetic tape are placed between pairs of chip capacitor pads on the integrated circuit package. The strips of synthetic tape each have a height extending above height of the pairs of chip capacitor pads. In the preferred embodiment, the strips of synthetic tape are strips of polyimide tape. The height of the strips of synthetic tape is selected so that the chip capacitors will be installed at a sufficient distance from the integrated circuit package so that solder balls will not be of sufficient diameter to wedge between the integrated circuit package and the chip capacitors. The chip capacitors are installed over the pairs of chip capacitor pads. The chip capacitors rest on the strips of synthetic tape. For example, the chip capacitors are permanently attached to the pairs of chip capacitors using a solder process. A reflow solder process is then performed.

Abstract: An ESD protection device for protecting semiconductor devices from electrostatic discharge includes a metal pad of the semiconductor device, a first charge sink, and a first MOS transistor. The first MOS transistor is placed under the metal pad. The first MOS transistor is coupled as a switch between the first charge sink and the metal pad. In addition, the metal pad operates as a gate of the first MOS transistor. Upon static electricity of a high magnitude of voltage being placed on the metal pad, the first MOS transistor turns on and the static electricity is discharged to the first charge sink.

Abstract: A transistor is formed which has improved hot carrier immunity. On a substrate, between two source/drain regions, a gate region is formed over a dielectric region. An implant is used to dope the source/drain regions. After doping the source/drain regions, a tilted angle nitrogen implant is performed to implant nitrogen into areas of the dielectric region overlaying the drain/source regions of the transistor. The tilted angle nitrogen implant may be performed before or after forming spacer regions on sides of the gate region.

Abstract: Semiconductor wafers are processed in a semiconductor diffusion furnace. During processing, the semiconductor wafers are placed in a quartz tube. Also during processing, a laser beam is transmitted below a top surface of the quartz tube. While the quartz tube is not sagging, the laser beam is detected with a detector. When the top surface of the quartz tube sags so that the laser beam is obstructed by the top surface, the laser beam is no longer detected by the detector. At this point the detector will alert an operator of the system that the top surface of the quartz tube is sagging so that the laser beam is obstructed by the top surface. The operator of the semiconductor diffusion furnace then may replace the quartz tube before damage is done to the semiconductor wafers.

Abstract: A floor-plan of component blocks of logical circuits, including the symbolic routing of major connection networks, is produced as part of the process for laying out an integrated circuit on a chip. The floor-plan is produced before performing optimized placement and routing of logical circuits within component blocks of the VLSI circuit. First, the logical circuits are apportioned into component blocks. Then, an initial lay out of the component blocks of the VLSI circuit is performed. The major connection networks are routed between the component blocks so that the major connection networks are connected to connection areas within the component blocks. The initial lay out of component blocks is adjusted as necessary in order to take into account the addition of the major connection networks. Once any needed adjustments are made, routing guidance information is generated as part of the floor plan. The routing guidance information indicates locations and sizes of the major connection networks.

Abstract: A built-in self-test circuitry includes a design under test and a self-test processor. Included within the design under test is a plurality of scan row registers. The self-test processor includes a command processing section and a signal generating section. The command processing section receives information which indicates the configuration of the scan row registers. The signal generating section generates control signals which control the built-in self-testing of the circuit. The control signals are based on the information received by the command processing section. In the preferred embodiment, the command processing section includes a shift section, a load section, and a signature section. The shift section receives information which indicates a number of bits in each scan row register. The load section receives information which indicates a number of loads into the scan row registers.

Abstract: A method produces a capacitor. On a substrate, a first polysilicon layer is formed over an insulating region. A metal-silicide layer is formed on top of the first polysilicon layer. A dielectric layer is formed on top of the metal-silicide layer. A second polysilicon layer is formed on top of the dielectric layer. The second polysilicon layer and the dielectric layer are etched to form a top electrode and dielectric region. The metal-silicide layer and the first polysilicon layer are etched to form a bottom electrode.