Abstract: A low EMI bias current generator for cable modem applications has a distributed output stage with a steering input that controls the amount of bias current flowing through each transistor of a differential pair. A pair of resistors acts as a potentiometer controlling the amount of voltage seen across the input of the differential pair. The resistor pair controls the speed of transfer of bias current from one transistor to another such that the current transfer will take the form of a hyperbolic tangent that will allow a very gentle start-up.

Abstract: A current-to-current impedance converter re-circulates the driver transistor collector current back into the output current path to generate an error current that has two portions including a DC offset portion and a second order in 1/&bgr; portion. Since the error current has no first order in 1/&bgr; portion, the current-to-current ronverter exhbits very low distortion.

Abstract: A method for generating a plurality of enhanced accuracy current slopes includes providing a plurality of current slopes and summing signals indicative of each of the plurality of current slopes to generate a current slope sum. The method also includes generating an enhanced accuracy current slope sum based on the current slope sum and generating the plurality of enhanced accuracy current slopes based on the enhanced accuracy current slope sum such that each respective ratio between each enhanced accuracy current slope and the enhanced accuracy current slope sum is approximately equal to each respective ratio between each signal indicative of the corresponding current slope and the current slope sum.

Abstract: A magneto-resistive head preamplifier structure has a difference amplifier with cross-coupled transistors configured to cancel the adverse effects on preamplified output signals due to parasitic capacitance associated with the difference amplifier transistors. The cross-coupled transistors extend the useable bandwidth of the preamplifier by substantially reducing internally generated thermal noise.

Abstract: Method and apparatus for electrically interconnecting a sensor (104) in a beverage dispensing apparatus (102) to a sensor control system contained within a separate unit concurrent with attachment of said beverage dispensing apparatus to said separate unit are disclosed, comprising locking members (114) disposed on the beverage dispensing apparatus, a base plate (200) on the separate unit having receptacles (210) adapted to matably engage and align the beverage dispensing apparatus, a plurality of base plate conductor members (212), disposed on the lower surface of the base plate and electrically coupled to the sensor control system, a plurality of dispenser apparatus conductor members (118), electrically coupled (202) to the sensor and disposed on an upper surface (112) of the beverage dispensing apparatus such that as the beverage dispensing apparatus is matably engaged with the base plate the conductor members are brought into alignment and communicative contact.

Abstract: A capacitor structure (100) including first and second capacitor plates (102, 106) insulatingly spaced from each other by a capacitor dielectric (102). A first set of conductive posts (301) electrically couple to the first capacitor plate (102) and extend away from the capacitor dielectric (104). A first conductive structure (302) comprising a material with lower resistivity than the first capacitor plate (102) is electrically coupled to the first set of conductive posts (301). In a preferred embodiment, a second set of conductive posts (501) are electrically coupled to the second capacitor plate (106) and extend away from the capacitor dielectric (102). A second conductive structure (503) is electrically coupled to the second set of conductive posts (501).

Abstract: A differential voltage sense circuit has a fuse placed in one upper leg of a resistance bridge while the remaining upper leg (sense leg) employs a resistor constructed of doped poly or poly silicide or constructed of the doped silicon that forms the N-well or P-well in CMOS process. The lower legs each have a switch selected from a pair of matched switches. A comparator, latch and combinational logic sense the state of the fuse in the resistance bridge and latch the state information before the switches can operate to stop the flow of current in the resistance bridge. The differential voltage sense circuit can operate at low voltage levels compatible with advanced CMOS processes.

Abstract: A method for validating flash memory includes selecting for execution and executing, from a plurality of setup procedures available for the memory, a memory validation setup procedure setting respective values for a plurality of parameters that are also parameters set by execution of the other of the plurality of setup procedures. The method also includes determining that validation of a particular sector of the flash memory is desired and validating the particular sector of the flash memory, including examining the values of the plurality of parameters.

Abstract: A method for improving the accuracy, from ±2.5% to less than ±1%, and time, from 8 seconds to less than 4 seconds, for trimming the dual frequency of an integrated circuit oscillator while reducing the effects of transistor mismatch and power supply variations. This method picks trim values for the two frequencies using a combination of binary and linear searching techniques, and then performs tests to assure that the trimmed oscillator frequencies are well within specification. To save circuitry, the coarse adjust binary value (typically 4 bits) is shared between the two frequencies with only the fine adjust binary values (typically 3 bits) requiring separate values. This method compensates for the fact that the desired ratio between the two frequencies is not constant, but decreases as the coarse trim setting increases, and provides an optimal trim of the two desired oscillator frequencies by setting on-chip fuses.

Abstract: Disclosed is a method of automatically sensing and controlling beverage quality for soft drinks from a fountain dispenser, for example, comprising the steps of supplying a first fluid, such as water or carbonated water, wherein the flow of the first fluid is controlled by a first valve, supplying a second fluid, mixing the first fluid and the second fluid, passing a sample of the mixture of the first fluid and the second fluid onto a sensing surface of a fixed optic sensor, measuring one or more properties of the sample, such as, for example, refractive index, temperature, and pressure, controlling the first valve based on the one or more properties, and dispensing the mixture. The first valve may be proportionally enlarged and reduced or it may selectively opened and closed pursuant to a desired duty cycle.

Abstract: A thick copper interconnection structure and method for an LDMOS transistor for power semiconductor devices. A large LDMOS transistor is formed of a plurality of source and drain diffusion regions to be coupled together to form the source and drain. Gate regions are formed between the alternating source and drain diffusions. Each diffusion region has a first metal layer stripe formed over it and in electrical contact with it. A second metal layer conductor is formed over a plurality of the first metal layer stripes, and selectively contacts the first metal layer stripes to form a source and a drain bus. A thick third metal layer is then formed over each second metal layer bus, either physically contacting it or selectively electrically contacting it. The thick third level metal is fabricated of a highly conductive copper layer.

Abstract: A circuit for improving the performance of a charging capacitor inverter used in VCO and similar circuits. The disclosed approach is used to provide both trip point and charging current delay control to reduce the amount of “jitter” associated with the circuit. Trip point delay control is accomplished by adding an in-line transistor, output in a typical charged capacitor inverter, between the charging capacitor and the circuit. The threshold of this transistor is controlled by a dc bias level (control voltage) which allows this transistor to turn “ON” or “OFF” when the node voltage of the capacitor reaches the controllable preset level. Further control of the circuit's delay is obtained by means of circuitry which allows the amount of capacitor charging current to be selected.

Abstract: A fast acting polarity detector uses a “very fast” polarity detector in tandem with a “precise” polarity detector to increase the maximum speed achievable from an A/D converter that employs a 1-bit folding front end. The fast polarity detector is a coarse polarity detector that immediately controls the 1-bit folder. The precise polarity detector operates more slowly, but more accurately. When the output of the precise polarity detector becomes available, it overrides the output of the fast polarity detector. This process does not limit the speed of the A/D conversion even though the precise polarity detector is slower to operate since the signal levels are small.

Abstract: A low noise, low distortion, power efficient DSL/cable line driver has a double Wheatstone impedance bridge network that functions to prevent contamination of DSL signals that are received by and transmitted from the line driver. The line driver employs an external current sensing impedance that can be either purely resistive or complex and that can be selected to accommodate a particular transmission medium. The line driver further employs an internal programmable resistor that can be programmably adjusted to accommodate changes in transmission medium impedance to optimize sidetone rejection.

Abstract: A fast FIFO memory system stores identical data in both static RAM memory and FIFO memory. Data is transferred from the FIFO when insufficient RAM read time is available. When the FIFO is full, additional data is stored in the RAM which runs at a much slower speed than the FIFO. Data is then transferred from the RAM until the FIFO is no longer full, at which time the memory system again functions at the faster FIFO speed.

Abstract: An adaptive equalizer capable of tracking rapid channel variations while maintaining high stability and low jitter, and a receiver constructed therefrom. A novel feature of the invention is that is that the equalizer is sectioned, that is constructed from a plurality of feed-forward sections and decision-feedback sections, where these sections comprise a cascade of an adaptive linear filter and an adaptive multiplier. This structure is effective at combating rapid channel variations, which are a result of delay variations of the reflections of the signal, e.g., airplane flutter, without sacrificing the stability and the accuracy of the equalizer even in cases where the equalizer has a large number of taps. The different equalizer sections may have different step size parameters. A controller monitors the channel variations and adjusts the step size parameters of each section accordingly.

Abstract: An integrated circuit (IC) comprising an integrated level shifting latch for I/O. The level shift in the IC I/O section may be clocked. In addition, a latch may be moved from the core section to the I/O section of the device, and thus the incoming clock may remain in the external voltage domain to clock the latch along with the level shift. The level shift and latch may be clocked on opposite phases of the clock. Preferably, the level shift and latch may operate differentially on the data signal. Both setup and clock-to-Q times are significantly reduced with respect to prior art devices, allowing higher speed industry specifications may be met.

Abstract: A reprogrammable FIFO status flags system for determining the status of a FIFO memory having a storage capacity (depth) D generates a pair of FIFO status flags, PAF (Programmable Almost Full) and PAE (Programmable Almost Empty) that can be reprogrammed multiple times, even after FIFO writes and reads have occurred. Two offset values (‘N’ and ‘M’) are programmed into the FIFO. PAE is high only when the number of words stored in the FIFO equals N or fewer. PAF is high only when the number of words stored in the FIFO equals D minus M or more.

Abstract: A system and method for detecting battery removal or absent battery condition in a charger without use of external stimulus such as a thermistor, EEPROM, or additional pin. The system and method use information solely available from the charger positive and negative terminals to correctly annunciate the current state of the charger to a host or end-user.

Abstract: A frequency synthesizer architecture naturally combines transmitter modulation capability with a wideband all-digital PLL modulation scheme to maximize a digitally-intensive implementation by operating in a synchronous phase-domain. Synchronous logic is provided across a digitally controlled VCO and is synchronous to the VCO output clock by implementing a timing adjustment in association with a reference calculation to allow a frequency control word to contain both channel information and transmit modulation information.