Abstract: A power supply pulse width modulation (PWM) control system uses peak current program mode (CPM) control for large duty ratios with a smooth transition to voltage mode control at small duty ratios down to zero duty ratio. The PWM control system implements the latch function in an analog, circuit in contrast with commonly employed digital solutions, further resulting in low delay times since it does not have logic and set-up delays that are associated with latches.

Abstract: An efficient and practical system and method to determine when a switching DC-DC regulator is under a light load condition. The light load condition is determined by monitoring the switch node voltage to detect a zero-crossing voltage that is load dependent and occurs when the average output current minus half the switching current at the switch node is less than or equal to zero.

Abstract: A conducting path with a path meander provides a precision voltage-dividing circuit. At each location wherein a voltage level is to be established, the conducting path has an expanded region called a junction region. The centers of all junction regions are equidistant from the centers of neighboring junction regions. Junction regions are positioned at predetermined intervals along the straight portions of the conducting path and at each corner of the path meander. Each junction region has a metal patch extending therefrom. The metal patches are coupled to conducting plugs that, in turn, can be coupled to switching elements of a digital-to-analog converter unit. The junction regions can be altered to increase the precision of the voltage-dividing circuit. Because the junction regions are equidistant from the neighboring junction regions, a cell that includes the switching elements can have a square geometry.

Abstract: A high power supply ripple rejection internally compensated low drop-out voltage regulator using an output PMOS pass device. The voltage regulator uses an intermediate amplifier stage configured from a common source, current mirror loaded PMOS device to replace the more conventional source follower impedance buffer associated with conventional Miller compensation techniques. Compensation is achieved through use of a small internal capacitor that provides a very low frequency dominant pole at the output of the input stage while effectively pushing out the two other poles at the outputs of the second and third gain stages to a frequency well outside of the unity gain frequency to ensure closed loop stability. High, wide bandwidth PSRR is achieved through an integrated circuit implementation of three voltage gain stages compensated by a nested active Miller compensation technique that does not impedance shunt the output series PMOS pass device.

Abstract: An amplifier slew rate boosting scheme for use with an amplifier having a closed-loop gain equal to or very near unity has one plate of a compensation capacitor conventionally coupled to an internal high impedance gain node, but has the other plate of the compensation capacitor unconventionally driven with a buffered version of the input signal. The voltage appearing across the compensation capacitor in response to changes in the input signal is significantly less than that achieved using conventional compensation architectures where the other plate of the compensation capacitor is coupled to an AC ground. Since very little current is required to charge the compensation capacitor, the tail current generated by the input stage can be used instead to charge parasitic capacitances within the amplifier to increase the slew rate.

Abstract: A voltage reference overshoot protection circuit senses unwanted ringing voltage levels in a driven device such as a backplane and controls the gate voltage to a voltage level control transistor such that a ringing output signal produced by an associated output driver is reduced in response to a control signal dependent on the ringing voltage level.

Abstract: A digital signal system (100) for determining an approximate logarithm of a value of x having a base b. The approximate logarithm includes an integer portion (i) and a decimal portion (f). The system comprises an input (12) for receiving a signal, and circuitry (18) for measuring an attribute of the signal. The attribute relates at least in part the value of x. The system further comprises circuitry (104) for identifying a bounded region within which x falls. The bounded region is one of a plurality of bounded regions, where each of the plurality of bounded regions corresponds to a different value of an integer n and is bounded on a lower side by bn and on a higher side by bn+1. Additionally, the identified bounded region identifies the integer portion of the approximate logarithm.

Abstract: A synchronous dynamic random access memory (SDRAM) (500) is disclosed. The SDRAM (500) operates in synchronism with differential clock signals (CLK and /CLK). A timing and control circuit (510) compares the complementary differential clock signals (CLK and /CLK) to generate an internal clock signal (CLKI). By comparing the differential clock signals (CLK and /CLK) to generate the internal clock signal (CLKI), the preferred embodiment can compensate for degradations in the differential clock signals (CLK and /CLK). In addition, by utilizing the internal timing signal (CLKI) the preferred embodiment does not have to employ more complex circuits that must operate in synchronism with the edges of both differential clock signals (CLK and /CLK).

Abstract: An energy efficient gate drive technique for binary push-pull MOSFET switching systems having a common switch node with inductive and capacitive elements connected to this common switch node. These energy storage elements on the common switch node can be parasitic in nature or discrete components. This technique recycles otherwise lost PMOS gate drive energy through the switch node, as a storage element, to the NMOS output FET.

Abstract: An LFRS (40, 50) calculates a PN sequence using Fibonacci form, such that when an offset is calculated from a known state, the bits of the new state comprise a block of sequence bits. Accordingly, to calculate a block having a length less than the length of the LFSR (40), all bits of the desired block can be calculated in a single offset calculation. If the block has a length greater than the length of the LFSR, one or more additional masks can be used to calculate the additional bits of the block sequence. Zero insertion is also supported.

Abstract: A circuit is designed with a decode circuit (313-315) having a first output terminal (319). The decode circuit is coupled to receive an address signal (81, 82, 85) having a first voltage range for producing a first output signal having one of a first and second logic levels. An output circuit (307, 309) is coupled to receive the first output signal and a power supply signal. The output circuit produces a second output signal having a second voltage range. A first latch transistor (301) is coupled to receive the second output signal. The first latch transistor is arranged to couple the first output terminal to a voltage terminal (209) in response to one of a first and second logic state of the second output signal. A second latch transistor (317) is coupled to receive the second output signal. The second latch transistor is arranged to couple the first output terminal to a reference terminal (318) in response to another of the first and second logic state of the second output signal.

Abstract: A low noise, low current, high bandwidth differential amplifier circuit (30), including a first amplifier (44) driving a first transistor X1 and having a first current source I2 coupled to an input of the first amplifier (44). A first feedback resistor R3 is coupled between the first current source I2 and the first transistor X1, and a second resistor R4 is coupled to the first resistor R3. A second amplifier (46) drives a second transistor X2, and has a second current source I3 coupled to an input of the second amplifier 46. A third feedback resistor R5 is coupled between the second current source I3 and the second transistor X2. A fourth resistor R6 is coupled to the third resistor R5. The first R3 and third R5 feedback resistors are driven by the first I2 and second I3 current sources rather than by the first (44) and second (46) amplifiers, respectively, allowing the first and second amplifiers (44, 46) to be single stage amplifiers.

Abstract: A class AB amplifier (400) is disclosed, having a first input node (402), a second input node (404), and an output node (406). A push-pull input stage (412) includes cross-coupled pairs of transistors, which form a charge current path and a discharge current path. When the voltage at the first input node (402) is greater than the voltage at the second input node (406), the amount of current drawn in the charge current path increases, and the amount of current drawn in the discharge current path decreases. When the voltage at the first input node (402) is less than the voltage at the second input node (404), the amount of current in the charge current path decreases while the amount of current in the discharge path increases. A first and fourth current mirror (422 and 428) are coupled to the charge current path, and a second and third current mirror (424 and 426) are coupled to the discharge current path.

Abstract: An ultra low voltage CMOS, class AB power amplifier has internal compensation using only parasitic gate capacitance.

Abstract: An integrated circuit having dynamic logic (20) is disclosed that includes a dynamic node (NODE 1). A feedback stage protects the dynamic node (NODE 1) and includes a controllable current path (26) connected between a voltage supply and the dynamic node (NODE 1), where the controllable current path (26) has a control terminal. The feedback stage also includes a feedback path from the dynamic node (NODE 1) to the control terminal, where the feedback path includes a delay stage (27) providing a delay greater than intrinsic circuit delay.

Abstract: A variable transconductance current mirror circuit includes a first field effect transistor having a gate, a source, and a drain, and a second field effect transistor having a gate, a source, and a drain. The gate of the second transistor is coupled to the gate of the first transistor, and a current source is coupled to the gates of the first and second transistors. The circuit also includes a voltage supply coupled to the sources of the first and second transistors. The circuit further includes a first diode having an anode and a cathode. The anode of the first diode is coupled to the gates of the first and second transistors, and the cathode of the first diode is coupled to the source of the first and second transistors. The first diode comprises a zener diode having a reverse breakdown voltage operable to prevent gate oxide breakdown of the first and second transistors.

Abstract: A compact data line arrangement (600) includes “twisted” data line pairs (604a-604c) disposed in a first direction. Each twisted data line pair (604a-604c) includes an upper segment pair (608a-608f) that is connected to a lower segment pair (610a-610f) by a twist structure (612a-612c). The upper and lower segment pairs (608a-608f and 610a-610f) can be formed with a first pitch using phase-shifted lithography. The twist structures (612a-612c) are formed from a second conductive layer, and have a greater pitch than the first pitch. The twist structures (612a-612c) are generally arranged in a second direction that is perpendicular to the first direction. Selected twist structures (612b) are offset in the first direction with respect to adjacent twist structures (612a and 612c). The offset twist structures (612a-612c) allow supplemental conductive lines (618) to be formed from the first conductive layer that extend in the first direction, between adjacent offset twist structures (612a and 612b).

Abstract: A system and method for wireless communication between two devices allows the transfer of location information through a cellular or “BLUETOOTH” link that can be used to provide a continuous indication of estimated distance and direction relative to the two devices in communication with one another.

Abstract: A high power supply ripple rejection (PSRR) internally compensated low drop-out voltage regulator using an output PMOS pass device. The voltage regulator uses a non-inversion variable gain amplifier stage to adjust its gain in response to a load current passing through the output PMOS device such that as the load current decreases, the gain increases, wherein a second pole associated with the voltage regulator is pushed above a unity gain frequency associated with the voltage regulator. The non-inversion variable gain amplifier is further operational to adjust its gain in response to a load current passing through the power PMOS device such that as the load current increases, the gain decreases, wherein the voltage regulator unity gain bandwidth associated with the loop formed by the compensation capacitor is kept substantially constant.

Abstract: A circuit (100) that drives word lines and tests a word line (102) in a semiconductor device is disclosed. A charge circuit (108) couples a supply voltage (VPP) to a charge node (106) according to a potential at a boot node (110). The charge node (106) supplies a charge voltage for the word line (102). In a standard cycle, the boot node (110) is charged to a high voltage, and maintained at the high potential, to keep the word line (102) charged. In a test cycle, the boot node (110) is charged to a high voltage, and then discharged to a low voltage, thereby isolating the charge node (106) and the word line (102). In the event the word line (102) suffers from current leakage, a drop in potential will be detected at the charge rode (106).