Abstract: An adaptive equalizer capable of tracking rapid channel variations while maintaining high stability and low jitter, and a receiver constructed therefrom. A novel feature of the invention is that is that the equalizer is sectioned, that is constructed from a plurality of feed-forward sections and decision-feedback sections, where these sections comprise a cascade of an adaptive linear filter and an adaptive multiplier. This structure is effective at combating rapid channel variations, which are a result of delay variations of the reflections of the signal, e.g., airplane flutter, without sacrificing the stability and the accuracy of the equalizer even in cases where the equalizer has a large number of taps. The different equalizer sections may have different step size parameters. A controller monitors the channel variations and adjusts the step size parameters of each section accordingly.

Abstract: The invention is a method for making a lead frame (30) having fine pitched lead frame leads (32). A first side of the lead frame material is etched to for the lead frame and define the lead frame leads and die pad, but the etch process does not etch completely through the lead frame material. The partially etched first side is then covered with a tape (31) or layer of photoresist (71). The second side of the lead fame material is then etched to complete the lead frame. The lead frame may then be plated.

Abstract: A digital self calibration scheme for pipelined AD converters. The scheme can correct for capacitor mismatch, capacitor non-linearity, amplifier gain and amplifier non-linearity.

Abstract: Disposable spacers of an organic material or a low-temperature inorganic material provide advantages in the formation of STI trenches and contact holes and additional freedom in line spacing.

Abstract: A pipeline analog-to-digital conversion system (10) includes a plurality of cascaded subconverter stages (12) and a digital correction unit (16). Each subconverter stage (12) includes an n-bit analog-to-digital converter (26), an n-bit digital-to-analog converter (28), and an arithmetic unit (32). The n-bit analog-to-digital converter (26) generates a second intermediate digital signal (18) as a function of a first input analog signal (24) and a corresponding first intermediate digital signal (18) received from a previous stage (12).

Abstract: A digital self calibration scheme for pipelined AD converters. The scheme can correct for capacitor mismatch, capacitor non-linearity, amplifier gain and amplifier non-linearity.

Abstract: An integrated circuit includes a substrate (12) having a conductive region (18), and includes a dielectric layer (19) disposed over the substrate. An upwardly tapering frustoconical opening (22) is created through the dielectric layer to the conductive region. A barrier layer (31) is then applied, after which a thin metal layer (32) is applied, the upper end of the opening being pinched off or closed by the metal layer. Heat and pressure are then simultaneously applied, so that the metal layer flows to completely fill the available space within the opening. Selected portions of the metal layer external to the opening are then etched away. A further dielectric layer (41) is applied over the barrier layer and metal layer, and then planarization is carried out on the further dielectric layer.

Abstract: In order to form an isolation structure in a substrate, a blocking layer (13, 14) is fabricated over the substrate (12), after which portions of the blocking layer and the substrate are removed at an isolation region (22). A dielectric layer (26) is then deposited over the blocking layer and the isolation region. Thereafter, a chemical-mechanical polishing process is carried out on the dielectric layer, so as to remove a substantial portion of the dielectric layer disposed above an upper surface of the blocking layer. A non-patterned etch is then carried out on the dielectric layer, in order to remove a remaining portion of the dielectric layer disposed above the upper surface of the blocking layer.

Abstract: An integrated circuit (12) made with a CMOS P-epi process includes a bandgap circuit (16). A pair of PNP bipolar junction transistors (73, 72) have respective currents flowing through them with a ratio of 8 to 1. A differential stage has a further pair of PNP bipolar junction transistors (66, 67) which are identical, and which have their emitters coupled to each other and to a power source (11). Each transistor of the further pair has a base coupled to the emitter of a respective transistor of the first pair. The output of the differential stage controls a current source (82), which causes a current to flow through multiple resistors (86, 87, 88) and through a diode (30). One of the resistors (87) has its ends coupled to the respective bases of the transistors of the first pair.

Abstract: An SCR provides for increased holding voltage by decoupling the pnp and npn parasitic bipolar transistors of the SCR. In one embodiment, a N+ region is placed between the n+ region and the p+ region normally associated with conventional SCR devices, to formulate a new resistance. The new resistance is manifested to allow more current to flow through the new resistance rather than through the SCR parasitic pnp bipolar transistor. Since the parasitic pnp bipolar transistor no longer turns on as strongly as it would otherwise without the low resistance path through the new resistor, the holding voltage of the SCR is raised.

Abstract: A conversion (20, 120, 220) system for converting an analog signal (18, 118, 218) to a digital signal (54, 154, 254) in a communications system (10), the conversion system (20, 120, 220) including an oversampled analog-to-digital converter modulator (24, 124, 224) for receiving an oversampling-clock signal (29, 129, 229) and a transmitted analog signal (18, 118, 218), the oversampled analog-to-digital converter modulator (24, 124, 224) operable to sample the analog signal (18, 118, 218) and to convert the analog signal (18, 118, 218) to a first digital signal (32, 132, 232), a time adjustor (41, 141, 241) coupled to the oversampled analog-to-digital converter modulator (24, 124, 224) for receiving the first digital signal (32, 132, 232) and a first adjustment signal (48, 148, 248), and for producing an output digital signal (54, 154, 254), and a digital signal processor unit (56, 156, 256) coupled to the time adjustor (41, 141, 241) for receiving the output digital signal (54, 154, 254) and performing timing

Abstract: A power management method and system which includes providing a system having a plurality of clock operated circuits, each clock operated circuit being operable in response to the receipt of clock signals. A first subplurality of the clock operated circuits receives an uninterrupted stream of clock signals and thereby is uninterruptably operable and a second plurality of the clock operated circuits receives a normally off interruptable stream of clock signals and is normally inoperable. The system is sampled for the presence of data signals being input thereto. The clock signals are sent to the second plurality of circuits in response to the sampling the presence of data signals being input to the system to cause the second plurality of circuits to be operable. The data signals are transmitted to the second plurality of circuits after a time delay equal to or greater than the expired time from the sampling to the sending.

Abstract: An electronic storage buffer (22) is efficiently used by dividing the buffer into a first (26) and second (28) storage area with a dynamically adjustable boundary (24) governing the respective sizes of each storage area. If the first storage area becomes full with data, the first storage area can be expanded and the second storage area can be reduced to utilize the empty space in the second storage area. Conversely, the second storage area can be expanded and the first storage area can be reduced to satisfy the data storage demands of the second storage area.

Abstract: A high-speed parallel-to-serial CMOS data transmitter uses a D Flip-flop matrix architecture to combine a shift scheme with a selection scheme to serialize parallel bit data. Data is partially serialized through multi data paths at a much lower frequency and a time-division multiplex scheme selects one bit from each data path allowing for pipelined data processing. The CMOS architecture uses selective load clock mode switching allowing different word bit widths to be processed simply by adjusting the frequency of a loading clock.

Abstract: An improved hydraulic brake system accommodates multiple, e.g. primary and secondary actuation forces while maintaining independence of operation between primary and secondary brake subsystems. A secondary subsystem line pressure booster draws its charging fluid from the primary system line using a split piston, free backflow, volume displacement approach. The improved brake system has a temperature sensitive condition sensing hydromechanical fuze to sense hydraulic line flow for velocity, volume, direction and pressure. The brake system also employs an input flow control valve to direct fluid flow in the secondary subsystem.

Abstract: A manually operated in-line secondary master cylinder can be configured for use with any hydraulic system which accommodates multiple manual input forces, and which requires the secondary input device to operate independently of the primary input device. The secondary master cylinder can be placed directly in a primary system operating pressure line, where it has no effect on system operation until it is actuated. Unlike a conventional master cylinder, the device draws a very small amount of charging fluid directly from the primary system line due to its use of a split piston, free backflow and volume displacement approach.

Abstract: A maintenance free, easy to install portable dock system has a molded shell constructed of a UV resistant, linear low density polyethylene. The dock shell includes a plurality of internal columnar supports strategically located to provide structural integrity as well as a desired adhesive surface area for the polyethylene. An "L" or "T" pier type or floating type dock can be formulated simply by coupling a desired number of dock shells together in a desired configuration via a full width self-aligning latching structure which does not require the hand and eye coordination generally required for known dock structures. The dock shell has support beams which run longitudinally over the entire length of the dock shell. Metal stringers are inserted into the outer most support beams to further enhance the structural integrity and increase the rigidity of the dock shell. Buoyancy for the dock shell is ensured with a polyurethane foam which is injected into the dock shell.

Abstract: A duct hose coupling device for attaching a hose to a ductwork structure. The device selectively attaches and detaches the hose without use of fastening hardware. Attachment of a hose via the duct hose coupling device allows air to be efficiently forced into or withdrawn from the ductwork structure. The device retains its high efficiency over prolonged periods of usage by isolating critical moving components from exposure to contaminants and unwanted debris.

Abstract: A detachable golf equipment and supply cleaning apparatus includes a substantially flat, flexible, moisture retaining wiping element. The wiping element is comprised of a flexible fabric with sufficient nap to loosen and remove any debris or unwanted matter on the face of a golf club. A pressure sensitive adhesive is secured to one side of the wiping element. The pressure sensitive adhesive is protected via a release backing sheet with a release coating on its inner surface that engages the adhesive layer. When the release backing sheet is removed, the wiping element can be selectively applied, removed and reapplied multiple times to a golfer's skin, clothing, equipment or other selected curved, flat or irregular surface as desired without adverse effects to either the wiping element or any of the aforesaid skin, clothing, equipment or other selected surfaces.