Abstract: A SCSI bus phase status register is included in a parallel SCSI host adapter integrated circuit. Initially, the SCSI bus phase status register has a predefined value. When the parallel SCSI host adapter integrated circuit must wait for assertion of a request signal by a target device, e.g., an active request signal is expected by the host adapter integrated circuit, an on-chip sequencer executes a SCSI bus phase status register read instruction. When the SCSI bus phase status register is read and has the predefined value, an active pause signal is sent to the on-chip sequencer that causes the sequencer to suspend execution of the read instruction. When an active request signal is received from the target device, the SCSI bus phase status register is loaded automatically with a current SCSI bus phase a predefined period of time after the assertion of the request signal provided that an active parity error signal is not generated by the host adapter integrated circuit within the predefined period of time.

Abstract: A memory architecture in accordance with an embodiment of the present invention improves the speed of method invocation. Specifically, method frames of method calls are stored in two different memory circuits. The first memory circuit stores the execution environment of each method call, and the second memory circuit stores parameters, variables or operands of the method calls. In one embodiment the execution environment includes a return program counter, a return frame, a return constant pool, a current method vector, and a current monitor address. In some embodiments, the memory circuits are stacks; therefore, the stack management unit to cache can be used to cache either or both memory circuits. The stack management unit can include a stack cache to accelerate data transfers between a stack-based computing system and the stacks. In one embodiment, the stack management unit includes a stack cache, a dribble manager unit, and a stack control.

Abstract: An active digital voltage regulator circuit is a two terminal device that is connected in shunt to first and second power supply input lines. The active digital voltage regulator circuit stores energy during times when the local power supply voltage is greater than a predefined voltage, e.g., during times when the parasitic inductances supplement the local power supply voltage. The active digital voltage regulator circuit uses the stored energy to supplement the local power supply voltage during times when the local power supply voltage starts to collapse, e.g., during periods when inductive losses are preventing the power supply from maintaining the local power supply voltage. Consequently, digital active voltage regulator circuit smooths the local power supply voltage by greatly ameliorating the ripple voltages associated with parasitic inductances and resistances. A control circuit within the regulator circuit is a combination of two self-biasing and off-set nulling power supply monitor circuits.

Abstract: An ergonomic dual-section computer-pointing device, that includes a cursor control section fixedly and movably attached to an ergonomic hand support section, reduces stress and helps to prevent cumulative trauma disorder. The ergonomic dual-section computer-pointing device keeps the hand in a neutral position, which imitates the natural roll of the hand, the wrist and the forearm. The ergonomic dual-section computer-pointing device facilitates two fields of motion. In a first field of motion, the fingers, the hand, and the wrist are used to manipulate the cursor control section while the ergonomic hand support section remains substantially stationary. In a second field of motion, the arm and shoulder are used to move the cursor control section and ergonomic hand support section in unison. The cursor control section is fixedly and movably attached to the ergonomic hand support section by a coupler.

Abstract: A source module, a destination module, or both modules, that are used in a data transfer, signal over an internal communication bus to a bus master when the addressed storage location in the data transfer comprises a single point address type memory, the addressed module drives an active signal on an address increment disable line in the control bus. In response to the active signal on the address increment disable line, the bus master inhibits changing the address for the duration of the data transfer. The module also drives an active signal on an expansion address off boundary line in the control bus when an internal expansion address of the module is not aligned with a natural boundary of a data bus of the internal communication bus to allow the bus master to adjust the width of the data transfer.

Abstract: A parallel SCSI host adapter integrated circuit includes a Bus Free management circuit having a plurality of input lines coupled to SCSI bus control terminals of said parallel SCSI host adapter integrated circuit; a Bus Free phase interrupt disable line; a clear line; a Bus Free phase status line; and a Bus Free phase interrupt line. The Bus Free management circuit automatically generates an active signal on said Bus Free phase status line following receipt of (i) one of a selection complete signal and a reselection complete signal on said plurality of input lines; and (ii) a Bus Free phase signal on said plurality of input lines. The parallel SCSI host adapter integrated circuit also includes a sequencer coupled to said clear line, to said Bus Free phase status line, and to said Bus Free phase interrupt disable line. The sequencer generates an active signal on said Bus Free phase interrupt disable line when a Bus Free phase is expected.

Abstract: An exhaust gas particulate controller is included between an exhaust of a barrel chemical vapor deposition reactor and the gas scrubber system. The exhaust gas particulate controller is positioned as close to the exhaust of the reactor as is practical. The exhaust gas particulate controller is a passive system that prevents generation of particulates associated with gas density changes that occur during processing within the reactor.

Abstract: In a parallel SCSI host adapter integrated circuit, a hardware circuit includes a SCSI bus request terminal, a SCSI bus attention terminal, and an automatic SCSI bus attention management circuit. The automatic SCSI bus attention circuit includes an automatic SCSI bus attention assertion hardware circuit coupled to the SCSI bus attention terminal and an automatic SCSI bus attention de-assertion hardware circuit coupled to the SCSI bus attention terminal and to the SCSI bus request terminal. Upon pending initiation of a selection phase, the automatic SCSI bus attention assertion circuit asserts an active signal on the SCSI bus attention terminal. Following assertion of the active signal on the SCSI bus attention terminal, the automatic SCSI bus attention de-assertion hardware circuit counts the number of active SCSI bus request signals received from the SCSI bus request terminal.

Abstract: In an integrated circuit, a scan cell has a data input terminal, a data output terminal, a scan enable terminal a scan output terminal, and a clock input terminal. A multiplexer in the scan cell has a first input terminal connected to the data input terminal, a second input terminal connected to a scan input terminal, a control terminal connected to the scan enable terminal, and a multiplexer output terminal. A D-type flip-flop element in the scan cell has a data input terminal connect to the multiplexer output terminal; a clock terminal connected to the scan cell clock input terminal; and a data output terminal connected to the scan cell data output terminal. An AND gate in the scan cell has a first terminal connected to the scan enable terminal, a second terminal coupled to the data output terminal of the D-type flip-flop, and an output terminal connected to the scan output terminal.

Abstract: A parallel host adapter that interfaces two I/O buses includes at least two independent data channels, a receive data channel and a send data channel. The receive data channel supports at least two data contexts. The parallel host adapter also includes an administrative information channel that couples one of the I/O buses to a memory where administrative information for the parallel host adapter is stored. The send data channel includes a send buffer memory, and a data transfer engine. The data transfer engine is coupled to a first port of the send buffer memory and to a first I/O bus coupled to the parallel host adapter. The send buffer memory is a single data context buffer memory. The receive data channel includes a receive buffer memory, and another data transfer engine. The another data transfer engine is coupled to the first I/O bus and to a first port of the receive buffer memory.

Abstract: An active digital voltage regulator circuit is a two terminal device that is connected in shunt to first and second power supply input lines. The active digital voltage regulator circuit stores energy during times when the local power supply voltage is greater than a predefined voltage, e.g., during times when the parasitic inductances supplement the local power supply voltage. The active digital voltage regulator circuit uses the stored energy to supplement the local power supply voltage during times when the local power supply voltage starts to collapse, e.g., during periods when inductive losses are preventing the power supply from maintaining the local power supply voltage. Consequently, digital active voltage regulator circuit smooths the local power supply voltage by greatly ameliorating the ripple voltages associated with parasitic inductances and resistances. A control circuit within the regulator circuit is a combination of two self-biasing and off-set nulling power supply monitor circuits.

Abstract: A novel rapid thermal process (RTP) reactor processes a multiplicity of wafers or a single large wafer, e.g., 200 mm (8 inches), 250 mm (10 inches), 300 mm (12 inches) diameter wafers, using either a single or dual heat source. The wafers or wafer are mounted on a rotatable susceptor supported by a susceptor support. A susceptor position control rotates the wafers during processing and raises and lowers the susceptor to various positions for loading and processing of wafers. A heat controller controls either a single heat source or a dual heat source that heats the wafers to a substantially uniform temperature during processing. A gas flow controller regulates flow of gases into the reaction chamber. Instead of the second heat source, a passive heat distribution is used, in one embodiment, to achieve a substantially uniform temperature throughout the wafers. Further, a novel susceptor is used that includes a silicon carbide cloth enclosed in quartz.

Abstract: The present invention uses a stack management unit including a stack cache to accelerate data retrieval from a stack and data storage into the stack. In one embodiment, the stack management unit includes a stack cache, a dribble manager unit, and a stack control unit. The dribble manager unit maintains a cached stack portion, typically a top portion of the stack in the stack cache. The stack cache includes a stack cache memory circuit, one or more read ports, and one or more write ports. The stack management unit also includes an address pipeline to transfer multiple data words by the spill control unit and the fill control unit to improve the throughput of spill and fill operations. When new data words are written to the top memory location of the stack, the optop pointer is incremented. If data words are read off the stack the optop pointer is decremented. During normal operations the dribble manager unit detects spill conditions and fill conditions.

Abstract: A method for suspending and resuming execution of firmware routines facilitates high speed concurrent processing within a multi-tasking integrated circuit that interfaces a first input/output (I/O) bus with a second input/output bus. The method uses a single instruction in a first executing routine to save a return address, and to transfer execution to a second routine. Similarly, a single return instruction in the second routine is used to restore the return address and to transfer execution from the second routine to the first routine. The use of single instructions in the two routines reduces the silicon area required to store the firmware, and enhances execution performance.

Abstract: An integrated circuit includes a sequencer module that executes firmware command lines and a plurality of hardware I/O bus interface modules. The plurality of hardware modules operates independently, and performs operations specified in a hardware I/O control block. Each of the plurality of hardware modules and receive data from and/or transmit data to an I/O bus. The sequencer module configures each hardware module by initializing a register set in each module, and monitors the operation of each module by polling the hardware register set. Each hardware module has a unique module identifier. Each register set has the same logical address space. A physical address of a particular register is the combination of the module identifier and the logical address of the register. Registers in two or more register sets that are used for the same operation, or function have the same logical address. This permits a single firmware routine to be used to service these modules for that function or operation.

Abstract: A shut-off circuit included in a dynamic flip-flop isolates output terminals of the dynamic flip-flop from circuitry within the flip-flop that could introduce noise on either output terminal during a portion of the evaluation phase. Since the output terminals are isolated from the input terminals during this portion of the evaluation phase, spurious input signals have no affect on the output signal levels. Similarly, charge within the dynamic flip-flop that is not completely dissipated in the transition from a precharge phase to the evaluation phase has no affect on the output signal levels during this portion of the evaluation phase.

Abstract: A collet assembly coupled to a rotary-linear drive unit allows easily placement of a susceptor shaft within a collet of the collet assembly when the collet assembly is in a first position. After the susceptor shaft is placed into the collet, the collet assembly is retracted to a second position by a spring force acting on a collet draw bar that is coupled to the collet. As the collet assembly is retracted by the spring force, the collet is closed about the susceptor shaft by the interaction between the collet and a collet spindle in which the collet is moveably mounted. As the collet closes, the collet assembly exerts a pressure about a circumferential surface of a susceptor shaft that in turn holds the susceptor shaft firmly in place within the collet, i.e., holds the susceptor shaft stationary within the collet. Consequently, when the susceptor shaft is rotated by the rotary-linear drive unit, there is no wobble associated with the rotary movement of the susceptor shaft.

Abstract: An improved method and apparatus for providing a service framework for a distributed object network system are provided. In some embodiments, an apparatus that includes a server, a service for a limited resource residing on the server, and a pool of workers for the service that execute service requests from a client in a distributed object network system is provided. In some embodiments, a method that includes providing client-side service request encapsulation, balancing workloads among clones of service locators, clones of services, and workers in a worker pool of a service, and improving fault tolerance in a distributed object network system is provided.

Abstract: An active digital voltage regulator circuit is a two terminal device that is connected in shunt to first and second power supply input lines. The active digital voltage regulator circuit stores energy during times when the local power supply voltage is greater than a predefined voltage, e.g., during times when the parasitic inductances supplement the local power supply voltage. A control circuit within the regulator circuit is a combination of two self-biasing and off-set nulling power supply monitor circuits. Each power supply monitor circuit further includes a differencing, non-overlapped, dual-output amplifier connected to the first and second power supply input lines. The differencing, non-overlapped, dual-output amplifier includes a predriver stage and an output stage, both of which are connected to the first and second power supply input lines.

Abstract: A hand support device for use with a computer pointing device relieves repetitive motion stress and includes a top surface, a bottom surface, and a perimeter surface connecting the top surface and the bottom surface. The top surface includes: a palm support region, that is an inclined planar surface; a little finger support portion extending from the palm support region; a thumb support region extending from the palm support region; a front index positioned on a side of the palm support region, and between the little finger and thumb support regions; and a side index adjacent to and extending from the palm support and thumb support regions. The bottom surface facilitates sliding of the hand support device on a work surface. The hand support device reduces stress and risk of injuries resulted from repetitive motions by encouraging the user of a computer pointing device to employ two fields of motion to control the pointing device.