Abstract: A self-aligning mating structure of a substrate support element is connected to an alignment guide. The combination of the self-aligning mating structure and the alignment guide assures that the element properly seats in a complementary mating structure shaped opening in a susceptor as the susceptor is moved into the processing position. An end of the substrate support element opposite to and removed from the self-aligning mating structure is weighted. Thus, the substrate support element remains properly seated in the susceptor throughout the process cycle. The end of the substrate support element opposite to and removed from the self-aligning mating structure also includes a support structure. As the susceptor is lowered from the processing position to the load/unload position, the support structure contacts the bottom of the reaction chamber or other surface in the reaction chamber.

Abstract: The present invention uses a stack management unit including a stack cache to accelerate data retrieval from a stack and data storage into the stack. In one embodiment, the stack management unit includes a stack cache, a dribble manager unit, and a stack control unit. The dribble manager unit maintains a cached stack portion, typically a top portion of the stack in the stack cache. The stack cache includes a stack cache memory circuit, one or more read ports, and one or more write ports. The stack management unit also includes an overflow/underflow unit. The overflow/underflow unit detects and resolves overflow conditions and underflow conditions. If an overflow occurs the overflow/underflow unit resolves the overflow by suspending operation of the stack cache and spilling a plurality of data words from the stack cache to the stack and equating the bottom pointer to the optop pointer. Typically, the overflow/underflow unit spills all valid data words from the stack cache during an overflow.

Abstract: A novel rapid thermal process (RTP) barrel reactor processes a larger batch of semiconductor substrates than was previously possible. The RTP barrel reactor is characterized by a short process cycle time in comparison to the same process cycle time in a conventional CVD barrel reactor. A rapid heat-up of the substrates is one of the keys to the shorter process cycle times of the RTP barrel reactor. The RTP barrel reactor utilizes a radiant heat source in combination with a heat controller that includes an open-loop controller for heat-up and a closed-loop controller for deposition as well as a new energy stabilizer to achieve heating a larger energy stabilizer and volume to a uniform processing temperature in times characteristic of RTP reactors.

Abstract: An active digital voltage regulator circuit stores energy during times when the local power supply voltage is greater than a predefined voltage, e.g., during times when the parasitic inductances supplement the local power supply voltage. The active digital voltage regulator circuit uses the stored energy to supplement the local power supply voltage during times when the local power supply voltage starts to collapse, e.g., during periods when inductive losses are preventing the power supply from maintaining the local power supply voltage. A control circuit within the regulator circuit is a combination of two self-biasing and off-set nulling power supply monitor circuits. Each power supply monitor circuit further includes a differencing, non-overlapped, dual-output amplifier connected to the first and second power supply input lines.

Abstract: The present invention provides a stack management unit including a stack cache to accelerate data transfers between the stack-based computing system and the stack. In one embodiment, the stack management unit includes a stack cache, a dribble manager unit, and a stack control unit. The dribble manager unit includes a fill control unit and a spill control unit. Since the vast majority of memory accesses to the stack occur at or near the top of the stack, the dribble manager unit maintains the top portion of the stack in the stack cache. Specifically, when the stack-based computing system is pushing data onto the stack and a spill condition occurs, the spill control unit transfers data from the bottom of the stack cache to the stack so that the top portion of the stack remains in the stack cache.

Abstract: An active digital voltage regulator circuit is a two terminal device that is connected in shunt to first and second power supply input lines. The active digital voltage regulator circuit stores energy during times when the local power supply voltage is greater than a predefined voltage, e.g., during times when the parasitic inductances supplement the local power supply voltage. The active digital voltage regulator circuit uses the stored energy to supplement the local power supply voltage during times when the local power supply voltage starts to collapse, e.g., during periods when inductive losses are preventing the power supply from maintaining the local power supply voltage. Consequently, digital active voltage regulator circuit smooths the local power supply voltage by greatly ameliorating the ripple voltages associated with parasitic inductances and resistances. A control circuit within the regulator circuit is a combination of two self-biasing and off-set nulling power supply monitor circuits.

Abstract: A hardware virtual machine instruction processor directly executes virtual machine instructions that are processor architecture independent. The hardware processor has high performance; is low cost; and exhibits low power consumption. The hardware processor is well suited for portable applications. These applications include, for example, an Internet chip for network appliances, a cellular telephone processor, other telecommunications integrated circuits, or other low-power, low-cost applications such as embedded processors, and portable devices.

Abstract: A microprocessor includes an on-chip low phase noise CMOS LC capacitance oscillator. The LC oscillator is relatively insensitive to power supply fluctuations. In addition, the LC oscillator is operable over a range of frequencies sufficient to support both normal full power operation, and reduced power operation of the microprocessor. The LC oscillator minimizes clock jitter problems and so permits extension of the microprocessor operating frequency to even higher levels than heretofore were possible. An output signal from a phase-frequency detector is a frequency control signal on a frequency control input line of a level converter and filter circuit of the LC oscillator. The output signal from level converter and filter circuit is a filtered frequency control signal on a control voltage input line to a continuously modifiable gigahertz frequency voltage controlled oscillator (VCO) circuit.

Abstract: An array boundary checking apparatus is configured to verify that a referenced element of an information array is within a maximum array size boundary value and a minimum array size boundary value. The array boundary checking apparatus of the invention includes an associative memory element that stores and retrieves a plurality of array bound values. Each one of the plurality of array bound values is associated with one of the plurality of array access instructions. An input section simultaneously compares the array access instruction identifier with at least a portion of each of the stored array reference entries, wherein the array access instruction identifier identifies an array access instruction. An output section is configured to provide as an array bounds output values one of the plurality of array bound values stored in one of the plurality of memory locations of the associated memory element.

Abstract: A method for queuing hardware control blocks for a system including a host microprocessor and a plurality of devices that each includes an onboard sequencer is based on a single host endless new hardware control block queue in a host memory that is managed such that the host endless new hardware control block queue never goes empty. Each device, that is coupled to the host microprocessor by an I/O bus, also has a device endless new hardware control block queue in a common hardware control block array. These device endless new hardware control block queues are managed such that the queues never are empty. A single device on the bus fetches hardware control blocks from the host endless hardware control block queue and loads the hardware control blocks in the common hardware control block array. The other devices on the I/O bus do not participate in the transfer of hardware control blocks to the common hardware control block array.

Abstract: An IC includes a plurality of functional blocks each having a discrete block-level architecture. The functional blocks are connected to one another via metal interconnect lines defined by an interconnect architecture. One or more of the functional blocks includes a spare (i.e., unused) repeater amplifier. Where a repeater amplifier inserted in a particular long line of the interconnect structure would decrease the signal propagation delay through the long line, the interconnect architecture is modified so that the long line is routed through the spare repeater amplifier. Such modification decreases the signal propagation delay of the long line without requiring a modification of the block-level architecture.

Abstract: A stack management unit includes a stack cache to accelerate data retrieval from a stack and data storage into the stack. The stack management unit also includes an address pipeline to transfer multiple data words by a spill control unit and a fill control unit in the stack management unit. The address pipeline contains an incrementor/decrementor circuit, a first address register and a second address register. An address multiplexer drives either the output signal of the incrementor/decrementor or a cache bottom pointer to the first address register. The output terminals of the first address register are coupled to the input terminals of the second address register. A stack cache multiplexer drives either the address in the first address register or the address in the second address register to the stack cache. A memory multiplexer drives either the address in the address multiplexer or in the first address register to a slow memory unit.

Abstract: A method for queuing TCBs for a system including a microprocessor and at least one host adapter device is based on an endless new TCB queue, that is managed such that the endless new TCB queue never goes empty. A device driver executing on the microprocessor manages an endless new TCB queue for each host adapter device in the system. The TCBs in the endless queue include a next TCB address field and a host adapter (HA) TCB array site field. The next TCB address field is used to couple TCB sites in a host memory into a linked list. The destination of a TCB in a host adapter (HA) TCB array is specified in the HA TCB array site field. The endless new TCB queue has head and tail pointer delimiters. The head pointer is accessible only by the host adapter device, and the tail pointer is accessible only by the device driver. The device driver appends a new TCB to the endless new TCB queue using the tail pointer to identify the next TCB storage site.

Abstract: The address used to specify the storage location of data streaming from a first device to a second device is used in the control of a data function, such as an XOR function circuit in an integrated PCI buffer controller and data function circuit. An alias PCI address is loaded in a SCSI command block for the data destination when the data function circuitry is to be enabled. A host adapter system driver or application is notified of an alias address during initialization, and uses the alias address in the construction of SCSI command blocks to specify that the data shall be operated upon by the data function. When no data operation is desired, the normal (non-alias) address is specified in the SCSI command block. Thus, for every address for the device, there is a corresponding alias address which not only addresses the same location, but also turns on the data function. In effect, two devices are defined in the address space corresponding to the two modes of operation.

Abstract: An active digital voltage regulator circuit is a two terminal device that is connected in shunt to first and second power supply input lines. The active digital voltage regulator circuit stores energy during times when the local power supply voltage is greater than a predefined voltage, e.g., during times when the parasitic inductances supplement the local power supply voltage. The active digital voltage regulator circuit uses the stored energy to supplement the local power supply voltage during times when the local power supply voltage starts to collapse, e.g., during periods when inductive losses are preventing the power supply from maintaining the local power supply voltage. Consequently, digital active voltage regulator circuit smooths the local power supply voltage by greatly ameliorating the ripple voltages associated with parasitic inductances and resistances. A control circuit within the regulator circuit is a combination of two self-biasing and off-set nulling power supply monitor circuits.

Abstract: An integrated buffer controller and data function circuit includes a data function circuit that is controlled by addresses supplied to the circuit. The integrated buffer controller and data function circuit has a bus interface that is used to connect the circuit to a bus on which one or more host adapters are connected so that both the host adapters and a host computer can transfer data to and from the circuit, and supply addresses to control operation of this data function circuit. A data channel in the integrated buffer controller and data function circuit connects the bus interface to a buffer memory controller. The buffer memory controller has a buffer memory port that includes a data port, a memory address port, and a memory control port. A buffer memory is connected to the buffer memory port. A data function circuit in the buffer memory controller is coupled to a data function enable output line.

Abstract: A method and apparatus for accelerating the execution of an object oriented computer program having a plurality of objects. In one embodiment, each of the objects includes an object header and object data which are stored in a memory. Moreover, each of the objects is associated with a corresponding set of methods (or functions). A typical object oriented program only maintains one copy of a method which is accessed by more than one object. However, in the present invention, each method is copied and stored in a memory, such that each object has a dedicated set of methods stored in memory. For example, if a first object and a second object require access to the same method, then a first copy of this method is provided for the first object, and a second copy of this method is provided for the second object. Providing each object with a dedicated set of methods minimizes the levels of indirection required to access the methods, and thereby accelerates the execution of instructions which access the objects.

Abstract: A method for queuing hardware control blocks, such as SCBs, for a system including a system processor coupled to a plurality of host adapter devices and a buffer memory controller device by an I/O bus is based on use of an endless new hardware command block queue, and an endless done hardware command block queue. The hardware command blocks for a plurality of devices, where each device includes a device processor, are managed by forming an endless queue for a device in a memory external to the device. A first pointer to the endless queue is maintained in a memory that is not within the memory space of the device processor. A second pointer to the endless queue is maintained in a memory addressable by the device processor. The first and second pointers address the head and tail hardware command block array sites of the endless queue.

Abstract: A flip-flop circuit for use with logic gates includes a dynamic input stage and a static output stage. The flip-flop receives a single phase which defines a precharge phase and an evaluation phase. The dynamic input stage has a NMOS logic block coupled to receive one or more data signals. The dynamic input stage output signal is precharged to a logic high level during the precharge phase. During the evaluation phase, the NMOS logic block of the dynamic input stage causes the dynamic input stage to generate an output signal that either remains at a logic high level or else transitions from high-to-low by performing a logic operation of the data signals. The static output stage receives the output signal from the dynamic input stage and the clock signal. During the precharge phase, the static output stage maintains the flip-flop output signal logic at the logic level of the previous evaluation phase independently of the signal received from the dynamic input stage.

Abstract: A dual instruction set processor decodes and executes code received from a network and code supplied from a local memory. Thus, the dual instruction set processor is capable of executing instructions in two different instructions sets from two different sources. The dual instruction set processor includes a computer platform independent instruction decoder, another decoder, and an execution unit that executes decoded instructions from both of the decoders. A computer system with the foregoing described dual instruction set processor, a local memory, and a communication interface device, such as a modem, for connection to a network, such as the Internet or an Intranet, can be optimized to execute, for example, JAVA code, in example of one set of computer platform independent instructions, from the network, and to execute non-JAVA code stored locally, or on the network but in a trusted environment or an authorized environment.