Abstract: In response to a component management function call by a remote client application, the component management application programming interface (API) generates a message that identifies the called function and the version of the component management API. The component management API calls a local message transfer RPC command to send the message to a RPC command module. The RPC command module processes the local message transfer RPC command, and packages the message for transfer as a RPC over the heterogenous network. The RPC command module sends the packaged RPC to a network stack which in turn transmits the packaged RPC over the heterogenous network to a network stack in the server computer. The server network stack provides the packaged RPC to a server RPC command module that unpacks the RPC in a conventional manner to obtain the original message. The message is passed to a server component management API.

Abstract: An I/O command block, that is stored in a memory, includes information for connecting the I/O command block to other I/O command blocks in a chain structure. The I/O command block chain structure allows simultaneity of execution, provides a mechanism to inhibit and enable execution of an individual I/O command block, and a mechanism for establishing precedence in the sequence of execution of the I/O command blocks. This level of capability is provided by only information in the I/O command blocks within the chain. To make a chain, a chain control field, a next block pointer, and an offshoot block pointer are configured in each I/O command block in the chain.

Abstract: A single phase edge-triggered staticized dynamic flip-flop circuit for use with dynamic logic gates includes a dynamic input stage and a static output stage. The dynamic input stage is coupled to receive a data signal and a clock signal. During the precharge phase, the dynamic input stage provides an output signal that is the complement of the data signal. The dynamic input stage output signal is precharged to a logic high level during the precharge phase. During the evaluation phase, the dynamic input stage generates an output signal that either remains at a logic high level or else transitions from high-to-low, complementing the logic level of the data signal. The static output stage receives the output signal from the dynamic input stage and the clock signal. During the precharge phase, the static output stage maintains the flip-flop output signal logic at the logic level of the previous evaluation phase independently of the signal received from the dynamic input stage.

Abstract: A circuit is disclosed which allows an IN-Test to be performed on an integrated circuit (IC) without having to stop the external clock sources by disabling the IC's internal phase-locked loops. Information indicative of the IC's clock mode and of the desired stop mode is contained within the IC's clock control register. In one embodiment, the internal clocks may be stopped in either of three stop modes while operating in one of three clock modes. When it is desired to stop the IC's internal clocks, the clock control register provides a stop instruction signal STOP.sub.-- INSTR to a clock control circuit which, depending upon the particular stop mode and clock mode encoded in signal STOP.sub.-- INSTR by the clock control register, asserts a enabling signal to a disable clock circuit.

Abstract: An I/O command block, that is stored in a memory, includes information for connecting the I/O command block to other I/O command blocks in a chain structure. The I/O command block chain structure allows simultaneity of execution, provides a mechanism to inhibit and enable execution of an individual I/O command block, and a mechanism for establishing precedence in the sequence of execution of the I/O command blocks. A plurality of I/O command blocks are configured into a chain of I/O command blocks in a memory where each I/O command block includes one of the plurality of I/O commands necessary to perform a RAID 5 I/O operation. A set of the I/O command blocks in the chain are configured so that the set of I/O command blocks are enabled to execute concurrently, i.e., the set of I/O command blocks are a concurrent string of I/O command blocks. The chain of I/O command blocks is executed in a sequence that is specified and controlled only by information in the I/O command blocks to perform the RAID 5 operation.

Abstract: A host adapter system includes a secondary computer bus, a plurality of I/O buses, and a plurality of host adapter circuits. Each host adapter circuit is connected to the secondary computer bus and to one I/O bus in the plurality of I/O buses. An integrated buffer controller and data function circuit is connected to the secondary computer bus and an external buffer memory. The external buffer memory appears to the plurality of host adapter circuits as a host computer buffer memory. The integrated buffer controller and data function circuit includes a data function circuit that is controlled by addresses supplied to the circuit. The integrated buffer controller and data function circuit has a bus interface that is used to connect the circuit to the secondary computer bus. A data channel in the integrated buffer controller and data function circuit connects the bus interface to a buffer memory controller. The buffer memory controller has a buffer memory port that is connected to the external buffer memory.

Abstract: A non-blocking multiple-phase clocking system for use with dynamic logic provides clock phases with overlapping evaluation phases to a circuit including a several cascaded dynamic logic gates. The circuit also includes a first flip-flop that is coupled to provide input signal(s) to the first dynamic logic gate of the cascade and a second flip-flop that is coupled to receive output signal(s) from the last dynamic logic gate of the cascade. Through the use of the overlapping evaluation phases and proper assignment of the clock signals to the dynamic logic gates, the output signal(s) generated by the dynamic logic gates receiving a particular clock phase are used as input signals to the dynamic logic gates receiving the next clock phase. Because of the overlapping of the clock phases, no latch is used. The clock phases are assigned to a particular dynamic logic gate so that the this dynamic logic gate enters the evaluation phase before the input signal(s) to the particular dynamic logic gate arrives (i.e.

Abstract: A cluster tool layer thickness measurement apparatus is part of a reactor cluster that includes a plurality of substrate processing reactors arranged around a sealed chamber in which a robot is located. The cluster tool layer thickness measurement apparatus is also mounted on the sealed chamber. After a layer is deposited on a substrate in one of the reactors, the robot removes the substrate from the reaction chamber of the reactor and places the substrate directly in the cluster tool layer thickness measurement apparatus on a substrate support. A carriage assembly moves the substrate support and consequently the substrate under an optical thickness measurement assembly. Optical thickness measurement assembly generates a signal representative of the thickness of the layer at one point that is transmitted to a monitor computer. After the measurement is completed, the carriage assembly moves the substrate so that the thickness of a layer on the substrate is measured at each of a plurality of locations.

Abstract: A hand support device for use with a computer pointing device relieves repetitive motion stress and includes a top surface, a bottom surface, and a perimeter surface connecting the top surface and the bottom surface. The top surface includes: a palm support region, that is an inclined planar surface; a little finger support portion extending from the palm support region; a thumb support region extending from the palm support region; a front index positioned on a side of the palm support region, and between the little finger and thumb support regions; and a side index adjacent to and extending from the palm support and thumb support regions. The bottom surface facilitates sliding of the hand support device on a work surface. The hand support device reduces stress and risk of injuries resulted from repetitive motions by encouraging the user of a computer pointing device to employ two fields of motion to control the pointing device.

Abstract: Circuits and methods of testing an integrated circuit die are disclosed. Active logic setting circuits are incorporated into input cells of a die. During testing, the active logic setting circuits weakly drive the input cells to a definite logic level. Therefore, the necessity of connecting probes to all of the input pads to prevent floating signals in the die is eliminated. Furthermore, during normal operations the active logic setting circuits have little or no effect on the performance of the die.

Abstract: A hand support device for use with a computer pointing device relieves repetitive motion stress and includes a top surface, a bottom surface, and a perimeter surface connecting the top surface and the bottom surface. The top surface includes: a palm support region, that is an inclined planar surface; a little finger support portion extending from the palm support region; a thumb support region extending from the palm support region; a front index positioned on a side of the palm support region, and between the little finger and thumb support regions; and a side index adjacent to and extending from the palm support and thumb support regions. The bottom surface facilitates sliding of the hand support device on a work surface. The hand support device reduces stress and risk of injuries resulted from repetitive motions by encouraging the user of a computer pointing device to employ two fields of motion to control the pointing device.

Abstract: A method for verifying that an area of memory is zero utilizing only hardware facilitates use of an integrated buffer controller and data function circuit in RAID applications. In this method, a logic zero value is loaded in a storage element. A unit of data is retrieved from the area of memory being tested for a logic zero value. The logic zero value and retrieved unit of data are applied as input signals to a logic hardware circuit that has a unique output signal for two logic zero input signals. If the output signal from the logic hardware circuit is not equal to the unique output signal, a status flag is set. So long as the output signal from the logic hardware circuit is the unique value, the retrieving, applying and setting operations are repeated until all data in the area of memory has been processed.

Abstract: Circuits and methods for a zero setup time storage element are disclosed. A storage element having a data input terminal, a clock input terminal and a data output terminal is able to capture a logic value of a data signal on the data input terminal with a substantially zero setup time at an active edge of a clock signal. Furthermore, some embodiments of the storage element are able to drive the captured logic value until the next active edge. One embodiment of the storage element includes a control circuit coupled to an output driver circuit. Depending on the state of the data input signal during an active edge, the control circuit can drives a first control signal to the output driver circuit or a second control signal to the output driver circuit. The output driver drives a data output signal on the data output terminal of the storage element based on the values of the control signals.

Abstract: A hand support device for use with a computer pointing device relieves repetitive motion stress and includes a top surface, a bottom surface, and a perimeter surface connecting the top surface and the bottom surface. The top surface includes: a palm support region, that is an inclined planar surface; a little finger support portion extending from the palm support region; a thumb support region extending from the palm support region; a front index positioned on a side of the palm support region, and between the little finger and thumb support regions; and a side index adjacent to and extending from the palm support and thumb support regions. The bottom surface facilitates sliding of the hand support device on a work surface. The hand support device reduces stress and risk of injuries resulted from repetitive motions by encouraging the user of a computer pointing device to employ two fields of motion to control the pointing device.

Abstract: An I/O command block, that is stored in a memory, includes information for connecting the I/O command block to other I/O command blocks in a chain structure. The I/O command block chain structure allows simultaneity of execution, provides a mechanism to inhibit and enable execution of an individual I/O command block, and a mechanism for establishing precedence in the sequence of execution of the I/O command blocks. This level of capability is provided by only information in the I/O command blocks within the chain. A method for specifying concurrent execution of a string of I/O command blocks stored in a memory using only information in the string of I/O command blocks allows concurrent execution of a plurality of I/O commands. The method first configures one I/O command block in the string as a head of string concurrent I/O command block. Another I/O command block in the string is configured as an end of string concurrent I/O command block. The remaining I/O command blocks, i.e.

Abstract: A method and structure for routing electrically conductive interconnect paths through a printed circuit board. The printed circuit board includes a plurality of insulating layers and conductive layers, including at least one electrically conductive voltage supply layer for receiving a first supply voltage. A plurality of voltage supply pad patterns are located at the upper surface of the printed circuit board. Each voltage supply pad pattern includes two or more electrically conductive pads which are coupled by one or more electrically conductive traces. Electrically conductive via plugs extend through the printed circuit board to connect the voltage supply layer to the voltage supply pad patterns. Each via plug is connected to one corresponding voltage supply pad pattern, thereby allowing each via plug to provide the first supply voltage to a plurality of pads at the upper surface of the printed circuit board.

Abstract: A method includes operating a general purpose computer system to minimize signal-propagation delay time of a long line of a simulated circuit. A design engineer empirically derives two rule bases, the first of which determines whether to divide the long line into two or more segments by inserting repeater amplifiers into a long line to minimize the propagation delay through the line. The second rule base relates optimum amplifier size for driving long lines to line length. These rule bases are stored in a main memory of the computer system. The computer system is configured to apply the first rule base to the long line to determine whether to divide the long line into two or more segments by inserting repeater amplifiers, and to apply the second rule base to optimize the size of each of the repeater amplifiers. The resulting long line, segmented by size-optimized repeater amplifiers, provides minimal signal-propagation delay.

Abstract: A structure and method for controlling the junction temperature of a semiconductor chip in an electronic system. A temperature sensing device and the chip whose junction temperature is to be monitored are located adjacent to one another on the same interconnect structure. A thermally conductive lid can also be attached to the interconnect structure, thereby enclosing the temperature sensing device and the chip within in a closed cavity. Dedicated pins extend from the temperature sensing device through the interconnect structure, for connection to a temperature control circuit. By locating the temperature sensing device on the same interconnect structure as the chip, and within a common enclosure, the temperature sensed by the temperature sensing device is an accurate representation of the actual junction temperature of the chip. By obtaining an improved reading of the actual junction temperature, the operation of the temperature control circuit can be optimized.

Abstract: A RTP reactor susceptor is a multi-layer structure. A first layer of the RTP susceptor is a thin layer of preferably silicon carbide, graphite, or silicon carbide coated graphite with a thickness less than about 6 mm, with an emissivity such that the first layer radiates heat, and with thermal heat transfer characteristics such that the first layer facilitates maintaining a substrate or substrates supported by the susceptor at a uniform temperature, and facilitates maintaining uniform process gas characteristics over the substrates. A second layer of the susceptor is transparent to the heat source of the RTP reactor and provides a rigid, stable platform for the first layer.

Abstract: A loudness balancing process includes three operations. In a first operation, the user specifies a plurality of digitally sampled audio time domain waveforms and an adjusted maximum loudness for each waveform is generated and stored. This operation includes a retrieve and filter process that identifies a portion of each waveform with a maximum loudness, and an adjust and store process that generates an adjusted maximum loudness that is a maximum loudness for the waveform which is free of audible distortion due to clipping. In a second operation, each stored adjusted maximum loudness is retrieved and filtered. The filtering selects a minimum adjusted maximum loudness that is selected as a global maximum loudness. In a third operation, each waveform in the plurality of waveforms is loudness-balanced based on the global maximum loudness. This three step process assures a consistent maximum loudness across the plurality of waveforms and assures that no audible noise is introduced by loudness balancing process.