Patents Represented by Attorney Fujitsu Patent Center
-
Patent number: 8332691Abstract: A main step is retrieved from an operations process subject to verification. Mapping information is referenced to further retrieve a preventive measure against an error expected upon execution of the main step. Based on the order in which the preventive measure is executed within the operations process, it is determined whether the preventive measure has been incorporated into the operations process at a correct position and a result of the determination is output.Type: GrantFiled: March 30, 2009Date of Patent: December 11, 2012Assignee: Fujitsu LimitedInventor: Masataka Sonoda
-
Patent number: 8332480Abstract: A plurality of storage nodes are connected via a network to build a storage system. Each of the storage nodes includes a storage device. A condition holding unit holds a state condition indicating an inactive state and an active state of the storage device. A state control unit controls a state of the storage device between the inactive state and the active state based on the state condition held by the condition holding unit.Type: GrantFiled: August 28, 2006Date of Patent: December 11, 2012Assignee: Fujitsu LimitedInventor: Mitsuhiko Ohta
-
Patent number: 8331239Abstract: Upon communication nodes receiving data that is a transfer target, based on a link value corresponding to a communication quality of each communication node that has transferred the data and radio wave strength among the communication nodes, a network system calculates a total link value that indicates a quality of a communication path that is used to transfer the data. The network system determines whether the calculated total link value is greater than or equal to a threshold value and based on a determination result, transfers the data to a destination communication node.Type: GrantFiled: October 18, 2007Date of Patent: December 11, 2012Assignee: Fujitsu LimitedInventor: Kenji Yamada
-
Patent number: 8332503Abstract: In order to provide a message abnormality automatic detection device, method and program for accurately detecting messages indicating abnormalities requiring response from a large amount of messages, the message abnormality automatic detection device 1 comprises a message collection unit 2 for collecting messages, a learning unit 3 for extracting patterns from the collected messages, a normal pattern memory unit 4 for storing normal patterns, a collation unit 5 for collating the collected messages with normal patterns and detecting message abnormalities, a warning unit 6 for outputting abnormalities to display 9 and the like, and a definition unit 7 for storing the definition data related to normal patterns.Type: GrantFiled: August 17, 2005Date of Patent: December 11, 2012Assignee: Fujitsu LimitedInventor: Ryuichi Takagi
-
Patent number: 8325548Abstract: A semiconductor device includes a first memory including a first memory cell and a first redundant memory cell; a first test circuit configured to test the first memory and output first defect information indicating a defective portion included in the first memory cell; a first storage part; and a first control circuit configured to, based on unmodified information stored in the first storage part, and the first defect information, determine modified information to be stored in the first storage part, wherein the first memory identifies the defective portion based on the modified information of the first storage part and replaces the first memory cell including the defective portion with the first redundant memory cell.Type: GrantFiled: June 21, 2010Date of Patent: December 4, 2012Assignee: Fujitsu Semiconductor LimitedInventor: Tatsuru Matsuo
-
Patent number: 8326850Abstract: A data converting apparatus includes a storage unit that stores encoded meta-definition information, a data converting function, a conversion rule table, and a conversion rule; an input unit that receives input of data to be converted; a detecting unit that uses the encoded meta-definition information to detect metadata codes for a conversion source and a conversion destination for which the conversion rule code matches; a determining unit that determines whether the detected metadata codes match; a specifying unit that, by referring to a conversion rule and based on the determination result at the determining unit, specifies the data converting function, according to the combination of the metadata codes for the conversion source and for the conversion destination; and a converting unit that uses the specified data converting function to convert the data of the conversion source to have a property prescribed by metadata for the conversion destination.Type: GrantFiled: July 16, 2010Date of Patent: December 4, 2012Assignee: Fujitsu LimitedInventors: Kazuo Mineno, Takashi Yoshino
-
Patent number: 8327041Abstract: A storage device is connected to a tape library having a plurality of tapes holding data and a host device. The storage device includes a receiving section, a first determining section and a reading section. The receiving section receives a request for data held in one of the tapes from the host device. The first determining section determines whether the data requested by the host device is stored in a storage section on the basis of the request received by the receiving section. The reading section reads the data in a predetermined amount to a memory from the tape in a case where the first determining section determines that the data is not stored in the storage section. The transferring section transfers the data in the memory to the host device and writes it on the storage section.Type: GrantFiled: January 20, 2010Date of Patent: December 4, 2012Assignee: Fujitsu LimitedInventor: Tomohiko Muroyama
-
Patent number: 8327081Abstract: A processor module having a cache device and a system controller having a copy TAG2 of a tag of the cache device configure a system to which a protocol representing the states of a data block of the cache device by six states, that is, an invalid state I, a shared state S, an exclusive state E, a modified state M, a shared modified state O, and a writable modified state W can be applied. In order to implement the concept, information about a new state in a cache device of a requester is included in a reply packet from the cache device for transmitting the data block. After the completion of the snooping process of the TAG2 until the reception of the reply packet from the cache device for transmitting the data block and the determination of the next state, an object data block is locked in the TAG2.Type: GrantFiled: August 27, 2008Date of Patent: December 4, 2012Assignee: Fujitsu LimitedInventor: Gou Sugizaki
-
Patent number: 8326916Abstract: A relay apparatus for relaying a communication between a client and a server includes a determining unit that determines, when the server is to be switched to a standby server, whether connection in an application layer established between the server and the client can be maintained, without depending on an application; and an executing unit that executes a process depending on a result of determination by the determining unit. The process includes a maintaining process for maintaining the connection when the determining unit determines that the connection can be maintained; and a disconnecting process for disconnecting the connection when the determining unit determines that the connection cannot be maintained.Type: GrantFiled: June 22, 2005Date of Patent: December 4, 2012Assignee: Fujitsu LimitedInventors: Takeshi Yamazaki, Toshio Ishitobi
-
Patent number: 8327079Abstract: A cache memory control device includes: a determination unit for determining whether or not a command provided from, for example, each core is to access cache memory during the execution of the command; and a path switch unit for putting a command determined as accessing the cache memory in pipeline processing, and outputting a command determined as not accessing the cache memory directly to an external unit without putting the command in the pipeline processing.Type: GrantFiled: December 11, 2009Date of Patent: December 4, 2012Assignee: Fujitsu LimitedInventors: Koken Shimizuno, Naoya Ishimura
-
Patent number: 8324873Abstract: A power supply apparatus is provided which includes: a first switch provided between an inductor and a terminal to which a reference voltage is applied; a second switch provided between the inductor and an output terminal; a first comparator circuit that compares an input voltage with a first comparison voltage; a signal generating circuit that outputs a frequency signal according to an output from the first comparator circuit; and a first control circuit that controls the first and second switches based on an output from the signal generating circuit to control an electrical current flowing into the inductor.Type: GrantFiled: December 13, 2009Date of Patent: December 4, 2012Assignee: Fujitsu Semiconductor LimitedInventors: Shinichi Nakagawa, Masahiro Natsume, Katsuyuki Yasukouchi
-
Patent number: 8324678Abstract: The method of manufacturing a semiconductor device, including a first region where a transistor including a gate electrode of a stacked structure is formed, a second region where a transistor including a gate electrode of a single-layer structure is formed, and a third region positioned in a boundary part between the first region and the second region, includes: depositing a first conductive film, patterning the first conductive film in the first region and the third region so that the outer edge is positioned in the third region, depositing the second conductive film, patterning the second conductive film to form a control gate in the first region while leaving the second conductive film, covering the second region and having the inner edge positioned inner of the outer edge of the first conductive film, and patterning the second conductive film in the second region to form the gate electrode.Type: GrantFiled: October 25, 2010Date of Patent: December 4, 2012Assignee: Fujitsu Semiconductor LimitedInventors: Hiroyuki Ogawa, Hideyuki Kojima, Taiji Ema
-
Patent number: 8325125Abstract: A display apparatus includes a cholesteric liquid crystal display panel, a control circuit and a driving circuit. The control circuit classifies pixels into different gradation level groups. The driving circuit applies a first driving waveform to the cholesteric liquid crystal display panel to bring pixels belonging to the first and the fourth group into a state corresponding to the highest gradation level, pixels belonging to the second group into a state corresponding to the lowest gradation level, and pixels belonging to the third group into states corresponding to gradation levels to be displayed, and applies a second driving waveform to the cholesteric liquid crystal display panel to bring pixels belonging to the fourth group into states corresponding to gradation levels to be displayed.Type: GrantFiled: March 1, 2010Date of Patent: December 4, 2012Assignee: Fujitsu LimitedInventors: Tomohisa Shingai, Masaki Nose, Hirokata Uehara
-
Patent number: 8326160Abstract: A dispersion compensation device includes: an optical branching unit to branch an optical signal to be received; a first dispersion compensator to perform dispersion compensation on one part of the optical signal branched by the optical branching unit with a variable compensation amount; a second dispersion compensator to perform dispersion compensation on another part of the optical signal branched by the optical branching unit; a monitoring unit to monitor the communication quality of an output optical signal of the second dispersion compensator; and a controlling unit to determine the direction of variation in chromatic dispersion of the optical signal based on the direction of variation in communication quality monitored by the monitoring unit and control the compensation amount of the first dispersion compensator based on the result of the determination.Type: GrantFiled: November 22, 2010Date of Patent: December 4, 2012Assignee: Fujitsu LimitedInventors: Makoto Murakami, Toshihiro Ohtani
-
Patent number: 8326459Abstract: A robot control apparatus includes walking operation control unit which controls the robot to carry out a predetermined walking operation; an obstacle detection unit which detects an obstacle existing in a place where a leg of the robot lands; a determination unit which determines whether or not a place on a sole of the robot's leg on which a reaction force from the obstacle works is in a stable area; and a reflex control unit which causes an ankle of the robot's leg in contact with the obstacle, when the reaction force working on the sole of the robot's leg is not in the stable area, to carry out a pitching or rolling operation, expanding the stable area, extends the leg, and controls the leg in such a way that a ZMP converges on a point of equilibrium of a support leg.Type: GrantFiled: September 15, 2009Date of Patent: December 4, 2012Assignee: Fujitsu LimitedInventor: Riadh Zaier
-
Patent number: 8327197Abstract: According to an aspect of an embodiment, an apparatus has a first storage, a read write unit for reading and writing data from/into the first storage, a first error detector for detecting an error of data read out from the first storage, an address storage for storing an address of the first storage, a determining unit for determining whether an address of the first storage in which data to be written is matched with the error detected address, a second storage for storing data to be written into the first storage when the address of the first storage in which the data to be written is matched with the error detected address, a second error detector for detecting an error of data read out from the second storage and a selector for outputting one of the data stored in the first storage or the second storage.Type: GrantFiled: January 8, 2009Date of Patent: December 4, 2012Assignee: Fujitsu LimitedInventor: Katsuya Ishiyama
-
Patent number: 8324714Abstract: A semiconductor device includes a semiconductor substrate having a main surface in which a semiconductor element region where a plurality of functional elements are formed is formed; a multilevel wiring layer disposed on the main surface of the semiconductor substrate; a first organic insulating material layer disposed on the multilevel wiring layer; a groove that penetrates the multilevel wiring layer on a scribe region that surrounds the semiconductor element region; and an organic insulating material that is spaced from the first organic insulating material layer and disposed in the groove.Type: GrantFiled: November 30, 2010Date of Patent: December 4, 2012Assignee: Fujitsu Semiconductor LimitedInventors: Jun Tsukakoshi, Yoshitaka Aiba
-
Patent number: 8325597Abstract: A bridge apparatus creates, transmits and circulates pass checking frames having virtual network identifiers in a ring network, and collects a passing/non-passing state of each virtual network identifier. The bridge apparatus creates, transmits and circulates a usage state checking frame in the ring network, and collects a used/unused state of the virtual network identifier of each bridge apparatus. The bridge apparatus creates, transmits and circulates a connection changing frame to change the virtual network identifier having the used state and the non-passing state into the virtual network identifier having the unused state and the passing state. Each bridge apparatus changes the virtual network identifier having the used state and the non-passing state into the virtual network identifier having the unused state and the passing state.Type: GrantFiled: December 16, 2009Date of Patent: December 4, 2012Assignee: Fujitsu LimitedInventor: Seiji Meki
-
Patent number: 8327212Abstract: A data processing device which performs a data transmission between semiconductor devices using a plurality of signal lines. In the data processing device, when there occurs an error in a data transmission from a transmitting device to a receiving device using a plurality of signal lines, data in which the error has occurred is stored. The stored data is compared bit by bit with non-erroneous data, thereby designating a bit in which error has occurred in the stored data.Type: GrantFiled: March 2, 2009Date of Patent: December 4, 2012Assignee: Fujitsu LimitedInventors: Junji Ichimiya, Hiroshi Nakayama, Shintarou Itozawa
-
Patent number: 8327308Abstract: An integrated circuit designing apparatus for designing a semiconductor integrated circuit. The designing includes verifying the timing based on delay information included in the design data, the delay information is extracted from results of placing and wiring of the semiconductor integrated circuit; determining whether each value of hold-time errors generated as a result of the timing verification is smaller than a criteria value; extracting, when the value of a hold-time error is smaller than the criteria value, a wiring line in which the hold-time error is improved by performing a wiring line extension process, the wiring line is included in a path having the hold-time error; calculating, for the extracted wiring line, a wiring line extension distance corresponding to an insertion delay value that improves the hold-time error; and performing the wiring line extension process to extend the extracted wiring line by the calculated wiring line extension distance.Type: GrantFiled: July 6, 2011Date of Patent: December 4, 2012Assignee: Fujitsu LimitedInventor: Koichi Nakagawa