Abstract: Adaptive image processing device performs image processing with a simple configuration on a composite image including areas having different characteristics by changing a process depending on the number of combined images in each area of the composite image configured by combining a plurality of images. The image processing device acquires a plurality of images and generates a composite image. When the composite image is generated, the image processing device realizes a process of determining the number of combined images for detecting the number of images to be combined for each area of the composite image and holding the number as information about the number of combined images, and an image processing parameter switching process for switching a parameter of image processing to be performed on each area of the composite image according to the information about the number of combined images.

Abstract: In the PLL circuit including a phase comparator, a charge pump circuit, a loop filter, and a voltage controlled oscillator, the loop band after the locking can be expanded in such a manner that, when the phase difference between a reference clock signal and a feedback clock signal is larger than a threshold value, an output current corresponding to the phase difference is outputted by reducing the change of the output current per unit amount of the phase difference, and that, when the phase difference is at most the threshold value, the output current corresponding to the phase difference is outputted by increasing the change of the output current per unit amount of the phase difference.

Abstract: A transmitting/receiving system includes a control field controlling a transmitting priority of a dynamic slot is included in each communication cycle, and a node of the transmitting/receiving system sets control information including a preferential usage request for a dynamic slot that the node transmits in the control field and notifies all nodes in the transmitting/receiving system of the preferential usage request for the dynamic slot.

Abstract: A radio transmission apparatus has a first duty adjustment circuit which changes a duty ratio of a clock signal, a second duty adjustment circuit which changes the duty ratio of the clock signal to a duty ratio different from the duty ratio of the clock signal changed by the first duty adjustment circuit, a first AND circuit which takes a logical product between a data signal and the clock signal having passed through the first duty adjustment circuit, and a second AND circuit which takes a logical product between an output signal of the first AND circuit and the clock signal having passed through inversion of the output of the second duty adjustment circuit to generate a pulse signal.

Abstract: In response to a route-changing event, original routes on the network are changed to new routes. A destination-reachable range is identified as a range from which packets can reach an information processing device specified by a destination address. Modification of forwarding data is performed for a neighbor communication device which is located outside the destination-reachable range and adjacent to a communication device in the destination-reachable range, so as to enable forwarding of packets to that communication device in the destination-reachable range. The modified forwarding data is then transmitted to the neighbor communication device. The modification made to the forwarding data results in an additional destination-reachable range, which is thus added to the destination-reachable range. Another cycle of processing is then performed on the basis of the expanded destination-reachable range.

Abstract: The packet forwarding apparatus of the present invention includes a packet buffer for temporarily storing packets to be forwarded, a timer for measuring the time of every predetermined unit period, a plurality of first queues corresponding to each of a plurality of address groups that form the packet buffer, a plurality of second queues that are provided corresponding to the property of the packets, a first controller for executing the writing of the packets, and a second controller for executing the discarding of the packets. According to this invention, through managing the first queues and the second queues, packets in the packet buffer can be discarded without the packets being read from the packet buffer.

Abstract: A process for producing a semiconductor device, includes: first melting by heating only a superior portion of a bump formed on an electrode on one principle surface of a semiconductor substrate; and second melting the entire bump by also heating an inferior portion of the bump.

Abstract: A semiconductor device has a multilayer interconnection structure, wherein the multilayer interconnection structure comprises at least a first interconnection layer and a second interconnection layer formed over the first interconnection layer, the first interconnection layer comprises a first conductor pattern embedded in a first interlayer insulation film and constituting a part of an interconnection pattern and a second, another interconnection pattern embedded in the first interlayer insulation film, the second interconnection layer comprises a third conductor pattern embedded in a second interlayer insulation film and constituting a part of said interconnection pattern, the third conductor pattern has an extension part in a part thereof so as to extend in a layer identical to the third conductor pattern, the third conductor pattern being electrically connected to the first conductor pattern at a first region of the extension part via a first via plug, the extension part making a contact with the second c

Abstract: A similarity analyzing device includes: an image acquisition section which acquires picked-up images with which image pick-up dates and/or times are associated; and an image registration section which registers a face image showing a picked-up face and with which an image pick-up date and/or time is associated. The device further includes: a degree of similarity calculation section which detects a face in each of picked-up images acquired by the image acquisition section and calculates the degree of similarity between the detected face and the face in the face image registered in the image registration section; and a degree of similarity reduction section in which the larger the difference between the image pick-up date and/or time associated with the picked-up image and that associated with the face image is, the more the degree of similarity of the face calculated by the degree of similarity calculation section is reduced.

Abstract: A value held in storage elements coupled to a clock buffer and variably set with a threshold voltage is read out in a state where an analyzing target circuit within an IC operates. An analyzing process specifies an impact of noise in a power supply or ground voltage of the clock buffer and a location where the impact is large, based on the threshold voltage and position information of the storage element from which the read out value has an inverted relationship to the set logic value and each storage element that is a read target. A constraint condition for placement of constituent elements of the IC and routing therein is created from results of the analyzing process, and a re-placement or re-routing process re-places or re-routes the constraint condition to reduce the noise.

Abstract: A control device is connected to a processor, a memory module, and a specification information storage memory for storing specification information indicating specifications of the memory module. The control device includes: a readout unit that reads the specification information from the specification information storage memory when power is turned on to the control device; a storage unit that stores the specification information read from the specification information storage memory; and a transfer unit that receives a specification information read instruction from the processor, and that transfers the specification information stored in the storage unit to the processor.

Abstract: A transmitting side device (10) and a receiving side device (20) are connected to each other via a bus (30) comprising TAG bits (31), data bits (32) and error detection/correction ECC bits (33). The transmitting side device (10) uses a redundant bit inversion circuit (14) to invert different bits of the ECC bits (33) corresponding to trigger signals (41 & 42). In the receiving side device (20), a determination circuit (24), which has received an error report signal (26) from an error detection/correction circuit (22), determines, from the position of an error bit in the ECC bits (33), which one of the trigger signals (41 & 42) has been transmitted from the transmitting side device (10).

Abstract: An electron microscope includes an electron gun for generating an electron beam, an accelerator for accelerating the electron beam to apply the electron beam to a sample, a spectroscope for selecting electrons having a specific energy out of the electron beam transmitted through the sample and losing an energy by an interaction with the sample, and a detector for detecting the electrons of the specific energy selected by the spectroscope and giving a transmission signal or a diffraction signal at a depth of the sample corresponding to a lost energy quantity of the electrons.

Abstract: A receiving circuit includes: a clock generating circuit to generate a plurality of clock signals in a cycle; an oversampling circuit to oversample input data based on the plurality of clock signals and output a plurality of samples of digital data in a unit interval; a data boundary determining circuit to detect a changing point of the digital data, determine data boundaries of the unit interval based on the changing point, and output digital data corresponding to a central data between the data boundaries; and a clock phase control circuit to control a phase of at least one of the plurality of clock signals so that a first number of the plurality of samples becomes a certain value when a second number of samples between the data boundaries is larger than a threshold value.

Abstract: Control points needed to generate a curve becoming the route of a deformable linear structure from respective pieces of passing point information defined at two passing points are arranged and the initial arrangement of control points needed to generate a curve is determined by performing re-arrangement of the control points, on the basis of a positional relation between the control points thus arranged. The curve between two points is re-generated from the initial arrangement thus determined while modifying the arrangement of one or more control points, the re-generated curves are then evaluated and a curve meeting a predetermined condition is extracted from among the curves.

Abstract: The RFID tag has a base sheet having a recess, a first element provided on the base sheet astride the recess, a second element which is provided between the first element and the base sheet and which is electrically connected to the first element, and a communication antenna which is provided on the base sheet and which is connected to at least any of the first element and the second element.

Abstract: A transmitting apparatus includes a detecting unit that detects deviation and balance relative to a specified bit rate of a frame signal input at a constant bit rate; a dividing unit that reads at constant intervals from a buffer storing the frame signal and outputs a signal divided into a plurality of segments having a predetermined data length; and a correcting unit that, based on the deviation and balance detected by the detecting unit, corrects the data length for the division by the dividing unit.

Abstract: A delay device that provides a delay amount to at least one of the in-phase signal and the quadrature signal, and a delay control section that controls the delay amount provided by the delay device based on a quality of the signals when the in-phase signal and the quadrature signal, to the at least one of which the delay amount is provided, at the delay device are converted into digital signals by the analog-digital converter, and the digital signal processing is carried out at the processor are provided. Thereby, the signal quality of recovered data at a receiving end of a multi-level phase modulation communication system is improved.

Abstract: A compound semiconductor device is provided with a substrate, an AlN layer formed over the substrate, an AlGaN layer formed over the AlN layer and larger in electron affinity than the AlN layer, another AlGaN layer formed over the AlGaN layer and smaller in electron affinity than the AlGaN layer. Furthermore, there are provided an i-GaN layer formed over the latter AlGaN layer, and an i-AlGaN layer and an n-AlGaN layer formed over the i-GaN layer.

Abstract: An image encoding control method for controlling processing for encoding data of an input moving image based on an interlace system comprises: a step of determining whether or not a chrominance-component motion vector generated based on the luminance-component motion specifies a reference prohibition region preset at least one of outside an upper boundary and outside a lower boundary of the reference image, for each combination of a field type of the region to be encoded and the field type of the reference image; and a step of prohibiting, when the chrominance-component motion vector generated based on the luminance-component motion vector specifies the reference prohibition region, the luminance-component motion vector from being output as a motion vector specifying a region that is most similar to the region to be encoded.